CN111223777B - GaN-based HEMT device and manufacturing method thereof - Google Patents

Abstract

The invention discloses a GaN-based HEMT device and a manufacturing method thereof. The manufacturing method comprises the steps of manufacturing a heterojunction, manufacturing a source electrode and a drain electrode which are matched with the heterojunction, wherein two-dimensional electron gas is formed in the heterojunction, and the source electrode and the drain electrode can be electrically connected through the two-dimensional electron gas; and further comprising the steps of growing an insulating layer directly on the heterojunction in situ at low temperature and growing a third semiconductor directly on the insulating layer in situ, the third semiconductor being capable of depleting a two-dimensional electron gas located thereunder; and manufacturing a grid electrode matched with the third semiconductor. After the heterojunction is formed by growth, the temperature is reduced, the insulating layer is directly grown on the heterojunction at low temperature in situ, the secondary pollution of the material can be avoided, the interface state density is reduced, the insulating layer with an amorphous structure can be formed, the spontaneous polarization and the piezoelectric polarization of the insulating layer material are eliminated, and the pollution to the growth of other structures of the device is avoided.

Description

GaN-based HEMT devices and manufacturing methods

Technical field

The present invention relates to a manufacturing method of a HEMT device, in particular to a GaN-based HEMT device and a manufacturing method thereof, and belongs to the field of semiconductor technology.

Background technique

GaN-based HEMT devices are a new type of HEMT device. Its working principle is mainly due to the spontaneous polarization and piezoelectric polarization of group III nitride materials, resulting in the formation of two-dimensional electron gas on the heterostructure interface. It has extremely high The electron concentration (up to 10 ¹³ /cm ² ) can be controlled by the gate voltage to control the current and form a field effect transistor. However, the HEMT with Schottky structure has large gate leakage and small gate voltage swing (maximum gate voltage 1V~2V). Therefore, it is necessary to prepare HEMT devices with a metal-insulating layer-semiconductor (MIS) structure. The introduction of the insulating layer can reduce gate leakage, increase the swing, and can play a role in protecting the barrier layer during the etching process. But on the one hand, because the GaN material system is not like the Si system, which can obtain a natural gate oxide layer with good interface and excellent quality through thermal oxidation, the gate dielectric layer and passivation layer can only be obtained through a variety of thin film deposition methods. On the other hand, GaN-based HEMT devices have a large number of surface states on the surface of the barrier layer. Therefore, when the device is working, these surface states will capture a large number of electrons and become negatively charged, thus reducing the channel electron concentration and resulting in a large output current of the device. The amplitude decreases, a phenomenon known as current collapse. Surface states are an important cause of the current collapse effect of HEMT devices, and surface passivation is one of the means to solve the current collapse effect. Passivating the dielectric layer on the surface of GaN-based HEMT can reduce the probability of surface state filling and reduce the degree of current collapse. Nowadays, researchers mostly use SiO ₂ , SiNx, Al ₂ O ₃ , HfO ₂ , Sc ₂ O _{3 ,} etc. as gate dielectric layers of HEMT devices. Commonly used passivation media include SiO ₂ , Sc ₂ O ₃ , MgO, etc. On the one hand These dielectric layer materials do not match Group III nitrides, and the growth methods of the dielectric layer and passivation layer are plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), and plasma enhanced atomic layer deposition. deposition method (PE-ALD), etc. The problem with these methods is that the heterojunction material needs to be taken out of the growth chamber and transferred to other dielectric layer deposition chambers, resulting in secondary contamination of the material, making the heterojunction material and There are inevitably a large number of interface states at the interface of the dielectric layer, which cause hysteresis in threshold voltage and current and current collapse problems during the operation of the device, which affects the promotion and application of the device. The in-situ growth method can avoid secondary pollution when producing a growth medium layer. However, for AlN, BN and the formed ternary quaternary compounds as dielectric layers, high-temperature in-situ growth obtains crystals, which have great spontaneous Polarization and piezoelectric polarization lead to the formation of a two-dimensional electron gas at the interface between the HEMT structure and the dielectric layer. The existence of this two-dimensional electron gas makes the device have dual channels, and causes the gate leakage current to seriously increase and weaken. Without the function of the dielectric layer in reducing leakage, it is difficult to increase the gate voltage swing, causing the dielectric layer to lose its due function. In addition, due to the effects of spontaneous polarization and piezoelectric polarization, the heterojunction interface of the GaN-based HEMT structure usually has a two-dimensional electron gas. It is a depletion-mode transistor structure that requires the application of a negative voltage to turn off, while the enhancement-mode The device does not require a negative voltage, which reduces circuit complexity and cost in the fields of microwave power amplifiers and low-noise power amplifiers; depletion-mode devices are in a normally open state, and in the field of digital fast circuit applications, enhancement-mode devices can form low-power complementarity Logic, simplified circuits, and enhanced devices can improve circuit safety, so the development of enhanced devices is imperative. At present, P-type GaN and InGaN are mostly used as pop-up layers to prepare enhancement-mode field-effect transistors. However, the acceptor atoms of P-type GaN and InGaN have large activation energy and are easily passivated by H, and the doping efficiency is only 0.1-1%. Moreover, the p-type leakage layer grows directly on the barrier layer. In order to reduce the resistivity during the device manufacturing process, the p-type leakage layer between the gate source and the gate drain must be etched. The etching process inevitably causes damage to the surface of the barrier layer. and damage, causing leakage current and current collapse to increase.

Contents of the invention

The main purpose of the present invention is to provide a GaN-based HEMT device and a manufacturing method thereof, thereby overcoming the deficiencies in the prior art.

In order to achieve the foregoing invention objectives, the technical solutions adopted by the present invention include:

Embodiments of the present invention provide a method for manufacturing a GaN-based HEMT device, including the step of forming a heterojunction. The heterojunction includes a first semiconductor and a second semiconductor. The second semiconductor is formed on the first semiconductor. and has a band gap wider than that of the first semiconductor, and a two-dimensional electron gas is formed in the heterojunction;

And the step of making a source electrode and a drain electrode that cooperate with the heterojunction, the source electrode and the drain electrode can be electrically connected through the two-dimensional electron gas; the manufacturing method also includes:

The step of growing an insulating layer directly on the heterojunction at low temperature in situ;

The step of growing a third semiconductor in situ directly on the insulating layer, the third semiconductor being able to deplete the two-dimensional electron gas located below it;

and making a gate that cooperates with the third semiconductor.

Furthermore, the growth temperature of the insulating layer is lower than the temperature at which the heterojunction is formed.

In some more specific embodiments, the manufacturing method includes: growing the insulating layer by metal-organic chemical vapor phase epitaxy, and the growth temperature of the insulating layer is 300°C to 800°C.

In some more specific embodiments, the manufacturing method includes: growing the insulating layer by molecular beam epitaxy, and the growth temperature of the insulating layer is 300°C to 600°C.

In some more specific embodiments, the manufacturing method includes: forming the heterojunction using any one of metal-organic chemical vapor phase epitaxy and molecular beam epitaxy.

Further, the insulating layer has an amorphous structure.

Preferably, the material of the insulating layer is selected from group III nitrides.

Preferably, the material of the insulating layer includes any one of AlN, BN, BAlN, BGaN and BAlGaN, but is not limited thereto.

Preferably, the thickness of the insulating layer is 5 to 50 nm.

Furthermore, the material of the third semiconductor is selected from P-type semiconductors.

Preferably, the material of the P-type semiconductor includes P-type BN, but is not limited thereto.

Further, the material of the first semiconductor is selected from group III nitrides.

Preferably, the material of the first semiconductor includes GaN, but is not limited thereto.

Further, the material of the second semiconductor is selected from group III nitrides.

Preferably, the second semiconductor is made of any one of AlGaN, AlInN, AlInGaN, AlGaN, AlInN and AlInGaN, but is not limited thereto.

In some more specific embodiments, the manufacturing method includes: processing the heterojunction by at least etching or ion implantation to form an isolation region within the heterojunction, thereby realizing a device. isolation.

Preferably, the etching thickness is 100-500 nm.

Preferably, the energy of the ion implantation is 10keV-200keV, and the implantation dose is 10 ¹³ cm ^-2 - 10 ¹⁵ cm ^-2 .

Embodiments of the present invention also provide GaN-based HEMT devices manufactured by the manufacturing method of GaN-based HEMT devices.

Embodiments of the present invention also provide a GaN-based HEMT device, which includes:

A heterojunction and a source, a drain, and a gate cooperated with the heterojunction. The heterojunction includes a first semiconductor and a second semiconductor. The second semiconductor is formed on the first semiconductor and has a width wider than The band gap of the first semiconductor, a two-dimensional electron gas formed in the heterojunction, and the source and drain can be electrically connected through the two-dimensional electron gas;

And, an insulating layer is formed on the heterojunction, the insulating layer is formed between the source electrode and the drain electrode, a third semiconductor is also formed on the insulating layer, and the third semiconductor is distributed under the gate electrode.

Further, the insulating layer has an amorphous structure.

Preferably, the material of the insulating layer is selected from group III nitrides.

Preferably, the material of the insulating layer includes any one of AlN, BN, BAlN, BGaN and BAlGaN, but is not limited thereto.

Preferably, the thickness of the insulating layer is 5 to 50 nm.

Furthermore, the material of the third semiconductor is selected from P-type semiconductors.

Preferably, the material of the P-type semiconductor includes P-type BN, but is not limited thereto.

Further, the material of the first semiconductor is selected from group III nitrides.

Preferably, the material of the first semiconductor includes GaN, but is not limited thereto.

Further, the material of the second semiconductor is selected from group III nitrides.

Preferably, the second semiconductor is made of any one of AlGaN, AlInN, AlInGaN, AlGaN, AlInN and AlInGaN, but is not limited thereto.

Further, an insertion layer is formed between the first semiconductor and the second semiconductor.

Preferably, the material of the insertion layer includes AlN, but is not limited thereto.

Further, the heterojunction is formed on the buffer layer, and the buffer layer is formed on the substrate.

Further, the substrate includes a homogeneous substrate or a heterogeneous substrate.

Preferably, the material of the homogeneous substrate includes GaN, but is not limited thereto.

Preferably, the material of the heterogeneous substrate includes any one of GaN, sapphire, Si, and silicon carbide, but is not limited thereto.

Compared with the existing technology, the manufacturing method provided by the present invention grows and forms the basic structure of the HEMT device in an epitaxial growth equipment (the basic structure of the HEMT device includes a heterojunction), then lowers the temperature and directly grows the basic structure of the HEMT device at low temperature. In-situ growth of the insulating layer; in-situ growth can avoid secondary pollution of materials and reduce the interface state density. Especially the low-temperature growth method can also make Group III nitrides such as AlN, BN, BAlN, BGaN or BAlGaN reach an amorphous state. The insulating layer with an amorphous structure is then formed, which is beneficial to eliminating the spontaneous polarization and piezoelectric polarization of the insulating layer material, so that there is no two-dimensional electron gas at the interface between the insulating layer and the barrier layer (i.e., the second semiconductor) of the HEMT device; in addition, using When the insulating layer is formed by in-situ growth, it will not cause pollution to the growth of other structures of the device; secondly, the insulating layer can also protect the barrier layer. P-type semiconductors are grown in-situ on the insulating layer and are etched. During the process, the barrier layer will not be etched, and the device structure will not be damaged; thirdly, the HEMT device structure using low-temperature in-situ growth to form the insulating layer and then growing the p-type semiconductor can form an amorphous in-situ While achieving in-situ passivation of the gate dielectric layer, the threshold voltage can be adjusted to form an enhancement device and avoid etching damage. It can effectively reduce gate leakage, increase gate swing and suppress current collapse, thereby achieving comprehensive performance of HEMT devices. effective improvement.

Description of the drawings

In order to explain the embodiments of the present invention or the technical solutions in the prior art more clearly, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings in the following description are only These are some embodiments recorded in the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without exerting creative efforts.

Figure 1 is a schematic diagram of the epitaxial structure of a GaN-based HEMT device in a typical embodiment of the present invention;

Figure 2 is a schematic structural diagram of a GaN-based HEMT device in a typical implementation case of the present invention;

Figure 3 is a schematic structural diagram of another GaN-based HEMT device in a typical implementation of the present invention.

Detailed ways

In view of the deficiencies in the prior art, the inventor of this case was able to propose the technical solution of the present invention after long-term research and extensive practice. The technical solution, its implementation process and principles will be further explained below.

Embodiments of the present invention provide a method for manufacturing a GaN-based HEMT device, including the step of forming a heterojunction. The heterojunction includes a first semiconductor and a second semiconductor. The second semiconductor is formed on the first semiconductor. and has a band gap wider than that of the first semiconductor, and a two-dimensional electron gas is formed in the heterojunction;

And the step of making a source electrode and a drain electrode that cooperate with the heterojunction, the source electrode and the drain electrode can be electrically connected through the two-dimensional electron gas; the manufacturing method also includes:

The step of growing an insulating layer directly on the heterojunction at low temperature in situ;

The step of growing a third semiconductor in situ directly on the insulating layer, the third semiconductor being able to deplete the two-dimensional electron gas located below it;

and making a gate that cooperates with the third semiconductor.

Furthermore, the growth temperature of the insulating layer is lower than the temperature at which the heterojunction is formed.

In some more specific embodiments, the manufacturing method includes: growing the insulating layer by metal-organic chemical vapor phase epitaxy, and the growth temperature of the insulating layer is 300°C to 800°C.

In some more specific embodiments, the manufacturing method includes: growing the insulating layer by molecular beam epitaxy, and the growth temperature of the insulating layer is 300°C to 600°C.

In some more specific embodiments, the manufacturing method includes: forming the heterojunction using any one of metal-organic chemical vapor phase epitaxy and molecular beam epitaxy.

Further, the insulating layer has an amorphous structure.

Preferably, the material of the insulating layer is selected from group III nitrides.

Preferably, the material of the insulating layer includes any one of AlN, BN, BAlN, BGaN and BAlGaN, but is not limited thereto.

Preferably, the thickness of the insulating layer is 5 to 50 nm.

Furthermore, the material of the third semiconductor is selected from P-type semiconductors.

Preferably, the material of the P-type semiconductor includes P-type BN, but is not limited thereto.

Further, the material of the first semiconductor is selected from group III nitrides.

Preferably, the material of the first semiconductor includes GaN, but is not limited thereto.

Further, the material of the second semiconductor is selected from group III nitrides.

Preferably, the second semiconductor is made of any one of AlGaN, AlInN, AlInGaN, AlGaN, AlInN and AlInGaN, but is not limited thereto.

In some more specific embodiments, the manufacturing method includes: processing the heterojunction by at least etching or ion implantation to form an isolation region within the heterojunction, thereby realizing a device. isolation.

Preferably, the etching thickness is 100-500 nm.

Preferably, the energy of the ion implantation is 10keV-200keV, and the implantation dose is 10 ¹³ cm ^-2 - 10 ¹⁵ cm ^-2 .

Embodiments of the present invention also provide GaN-based HEMT devices manufactured by the manufacturing method of GaN-based HEMT devices.

Embodiments of the present invention also provide a GaN-based HEMT device, which includes:

A heterojunction and a source, a drain, and a gate cooperated with the heterojunction. The heterojunction includes a first semiconductor and a second semiconductor. The second semiconductor is formed on the first semiconductor and has a width wider than The band gap of the first semiconductor, a two-dimensional electron gas formed in the heterojunction, and the source and drain can be electrically connected through the two-dimensional electron gas;

And, an insulating layer is formed on the heterojunction, the insulating layer is formed between the source electrode and the drain electrode, a third semiconductor is also formed on the insulating layer, and the third semiconductor is distributed under the gate electrode.

Further, the insulating layer has an amorphous structure.

Preferably, the material of the insulating layer is selected from group III nitrides.

Preferably, the material of the insulating layer includes any one of AlN, BN, BAlN, BGaN and BAlGaN, but is not limited thereto.

Preferably, the thickness of the insulating layer is 5 to 50 nm.

Furthermore, the material of the third semiconductor is selected from P-type semiconductors.

Preferably, the material of the P-type semiconductor includes P-type BN, but is not limited thereto.

Further, the material of the first semiconductor is selected from group III nitrides.

Preferably, the material of the first semiconductor includes GaN, but is not limited thereto.

Further, the material of the second semiconductor is selected from group III nitrides.

Preferably, the second semiconductor is made of any one of AlGaN, AlInN, AlInGaN, AlGaN, AlInN and AlInGaN, but is not limited thereto.

Further, an insertion layer is formed between the first semiconductor and the second semiconductor.

Preferably, the material of the insertion layer includes AlN, but is not limited thereto.

Further, the heterojunction is formed on the buffer layer, and the buffer layer is formed on the substrate.

Further, the substrate includes a homogeneous substrate or a heterogeneous substrate.

Preferably, the material of the homogeneous substrate includes GaN, but is not limited thereto.

Preferably, the material of the heterogeneous substrate includes any one of GaN, sapphire, Si, and silicon carbide, but is not limited thereto.

The technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present invention.

In some more specific implementations, a method of manufacturing a GaN-based HEMT device may include the following steps:

The basic structure of growing GaN-based HEMT devices. The basic structure of GaN-based HEMT devices includes a substrate, a buffer layer formed on the substrate, and a heterojunction formed on the buffer layer (the heterojunction includes a channel layer and a barrier. layer);

After the growth of the basic structure of the GaN-based HEMT device is completed, in the epitaxial growth equipment for growing the basic structure of the GaN-based HEMT device, an insulating layer (which can also be called dielectric layer), after growing the insulating layer, continue to grow the third semiconductor (i.e., p-type semiconductor or called p-type layer or called p-type leaking layer) in situ;

Process windows in the source and drain regions of the insulating layer, and then use the windows to make source electrodes and drain electrodes that are in electrical contact with the basic structure of the GaN-based HEMT device; wherein the source electrodes and drain electrodes can Electrical connection through a two-dimensional electron gas (2DEG) formed within the basic structure of the GaN-based HEMT device;

Make a gate electrode on the third semiconductor, and etch away the third semiconductor between the gate electrode and the source electrode, and between the gate electrode and the drain electrode.

The manufacturing method of a GaN-based HEMT device provided by the embodiment of the present invention uses an in-situ low-temperature method to grow an insulating layer as the dielectric layer and passivation layer of the GaN-based HEMT device. The in-situ growth can avoid secondary pollution of the material and minimize the interface. The density of states, especially the low-temperature growth method, can also make the insulating layer materials such as AlN, BN, BAlN, BGaN or BAlGaN form an amorphous structure, which is conducive to eliminating the spontaneous polarization and piezoelectric polarization of these materials, making the insulating layer and GaN-based There is no two-dimensional electron gas at the barrier layer interface of the basic structure of the HEMT device. In addition, there is no pollution to the growth of the device structure when the insulating layer is grown in situ. In addition, p-type BN is grown in situ on the insulating layer to deplete the two-dimensional electrons. The main advantage of using gas to prepare enhancement-mode devices is that BN is relatively easy to obtain p-type doped semiconductors (i.e., p-type semiconductors, or p-type layers). For example, the activation energy of Mg-doped BN to form a p-type semiconductor is very small, and When using a p-type GaN pop-up layer with a common structure to make an enhancement mode HEMT device, the etching of the p-type semiconductor between the gate, source and drain will inevitably damage the barrier layer, causing problems such as leakage current and current collapse; and the present invention The in-situ growth of p-type semiconductors on the insulating layer as stated in can prevent the etching process from directly damaging the barrier layer of the HEMT device and improve the electrical characteristics of the device. This low-temperature in-situ growth of the insulating layer can later grow the p-type semiconductor. The semiconductor HEMT device structure can not only form an amorphous in-situ gate dielectric layer and achieve in-situ passivation, but also adjust the threshold voltage to form an enhancement device and avoid etching damage, which can effectively reduce gate leakage and increase gate swing. and suppress current collapse, thereby effectively improving the overall performance of GaN-based HEMT devices.

It should be noted that the technical features of the above-described embodiments can be combined in any way. To simplify the description, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as these technical features are If there is no contradiction in the combination, it should be considered to be within the scope of this manual.

Specifically, a method for manufacturing a GaN-based HEMT device includes:

In a more specific embodiment of the present invention, a GaN-based HEMT manufacturing process includes the following steps:

1) The basic structure of GaN-based HEMT devices is grown in MOCVD or MBE epitaxial growth equipment. The basic structure of GaN-based HEMT devices includes growing on a homogeneous substrate (such as GaN) or a heterogeneous substrate (such as silicon, sapphire, silicon carbide) The buffer layer (thickness 20-30nm), GaN layer (i.e. the first semiconductor or channel layer, thickness 1um-4um) and barrier layer (i.e. the second semiconductor, thickness 10nm-50nm) are sequentially grown on the top. An AlN insertion layer can also be formed between the GaN layer and the barrier layer, and the thickness of the AlN insertion layer is 0.5nm-2nm);

2) Reduce the temperature in the reaction chamber of the MOCVD or MBE epitaxial growth equipment and adjust the temperature, gas pressure and source flow, and deposit in situ an insulating layer with an amorphous structure with a thickness of about 5 to 50 nm (the materials of the insulating layer include AlN, BN , BAlN, BGaN, BAlGaN, the low-temperature growth method can make Group III nitrides such as AlN, BN, BAlN, BGaN or BAlGaN reach an amorphous state), where in some more specific embodiments, the MOCVD epitaxial growth equipment in this step The temperature of the reaction chamber is adjusted between 300°C and 800°C. In this step, the temperature of the reaction chamber of the MBE epitaxial growth equipment is adjusted between 300°C and 600°C;

3) After growing the insulating layer, continue to grow the third semiconductor (such as p-type BN) in situ to form the epitaxial structure of the GaN-based HEMT device as shown in Figure 1;

4) Photolithography protects the device table, using etching (etching thickness 100-500nm) or ion implantation (ion implantation energy 10keV-200keV, implantation dose 10 ¹³ cm ^-2 -10 ¹⁵ cm ^-2 ) on the GaN-based HEMT A device isolation area is formed on the basic structure of the device to achieve isolation between devices; the GaN-based HEMT device structure obtained by etching isolation is shown in Figure 2; the GaN-based HEMT device structure obtained by ion implantation isolation is shown in Figure 3;

5) Etch away the third semiconductor between the gate and source, gate and drain by dry etching or wet etching;

6) Photoetch the source and drain patterns, and then etch the insulating layer through dry etching or wet etching to open holes for the source and drain electrodes;

7) In the source and drain regions, the source and drain electrodes are prepared by electron beam evaporation or sputtering. The source and drain metals include titanium (Ti), aluminum (Al), nickel (Ni), gold ( One or more alloys such as Au), platinum (Pt), etc.; then rapidly thermally annealed under high temperature and protective gas environment to form ohmic contact; the annealing temperature is generally between 500-950℃, and the annealing time is 10-120 seconds In between, the protective gas includes N ₂ or Ar;

8) Photo-etch the gate pattern, and deposit metal on the insulating layer (or called the insulating dielectric layer or dielectric layer) through electron beam evaporation or sputtering to form the gate; the gate metal includes nickel (Ni), gold One or more metals such as (Au), platinum (Pt), palladium (Pd), etc.

9) Use rapid thermal annealing equipment at 300-500°C for 10 minutes.

Compared with the existing technology, the manufacturing method provided by the present invention grows and forms the basic structure of the HEMT device in an epitaxial growth equipment (the basic structure of the HEMT device includes a heterojunction), then lowers the temperature and directly grows the basic structure of the HEMT device at low temperature. In-situ growth of the insulating layer; in-situ growth can avoid secondary pollution of materials and reduce the interface state density. Especially the low-temperature growth method can also make Group III nitrides such as AlN, BN, BAlN, BGaN or BAlGaN reach an amorphous state. The insulating layer with an amorphous structure is then formed, which is beneficial to eliminating the spontaneous polarization and piezoelectric polarization of the insulating layer material, so that there is no two-dimensional electron gas at the interface between the insulating layer and the barrier layer (i.e., the second semiconductor) of the HEMT device; in addition, using When the insulating layer is formed by the low-temperature in-situ growth method, it will not cause pollution to the growth of other structures of the device; secondly, the insulating layer can also protect the barrier layer. P-type semiconductors are grown in-situ on the insulating layer and are etched during engraving. During the etching process, the barrier layer will not be etched, and the device will not be damaged; thirdly, using low-temperature in-situ growth to form the insulating layer and then growing the P-type semiconductor HEMT device structure can form an amorphous in-situ While achieving in-situ passivation of the gate dielectric layer, the threshold voltage can be adjusted to form an enhancement device and avoid etching damage. It can effectively reduce gate leakage, increase gate swing and suppress current collapse, thereby achieving comprehensive performance of HEMT devices. effective improvement.

It should be understood that the above embodiments are only to illustrate the technical concepts and characteristics of the present invention. Their purpose is to enable those familiar with the technology to understand the content of the present invention and implement it accordingly, and cannot limit the scope of protection of the present invention. All equivalent changes or modifications made based on the spirit and essence of the present invention should be included in the protection scope of the present invention.

Claims (28)

1. A manufacturing method of a GaN-based HEMT device comprises the following steps:

a step of forming a heterojunction including a first semiconductor and a second semiconductor formed on the first semiconductor and having a band gap wider than that of the first semiconductor, the heterojunction having a two-dimensional electron gas formed therein;

and a step of manufacturing a source electrode and a drain electrode which are matched with the heterojunction, wherein the source electrode and the drain electrode can be electrically connected through the two-dimensional electron gas; the manufacturing method is characterized by further comprising the following steps:

directly growing an insulating layer on the heterojunction at low temperature in situ, wherein the insulating layer is of an amorphous structure, the insulating layer is made of any one of AlN, BN, BAlN, BGaN and BAlGaN, and two-dimensional electron gas does not exist at the interface between the insulating layer and the second semiconductor;

a step of growing a third semiconductor in situ directly on the insulating layer, the third semiconductor being capable of depleting two-dimensional electron gas located thereunder, the third semiconductor being selected from P-type semiconductors;

and manufacturing a grid electrode matched with the third semiconductor.

2. The method of manufacturing according to claim 1, wherein: the growth temperature of the insulating layer is lower than the temperature for manufacturing and forming the heterojunction.

3. A method of manufacturing according to claim 1 or 2, characterized by comprising: and growing the insulating layer by adopting a metal organic chemical vapor phase epitaxy mode, wherein the growth temperature of the insulating layer is 300-800 ℃.

4. A method of manufacturing according to claim 1 or 2, characterized by comprising: and growing the insulating layer by adopting a molecular beam epitaxy mode, wherein the growth temperature of the insulating layer is 300-600 ℃.

5. The method of manufacturing according to claim 1, characterized by comprising: the heterojunction is formed by adopting any one mode of metal organic chemical vapor phase epitaxy and molecular beam epitaxy.

6. The method of manufacturing according to claim 1, wherein: the thickness of the insulating layer is 5-50 nm.

7. The method of manufacturing according to claim 1, wherein: the third semiconductor material comprises P-type BN.

8. The method of manufacturing according to claim 1, wherein: the first semiconductor is made of III-nitride.

9. The method of manufacturing according to claim 8, wherein: the material of the first semiconductor comprises GaN.

10. The method of manufacturing according to claim 1, wherein: the material of the second semiconductor is selected from III group nitride.

11. The method of manufacturing according to claim 10, wherein: the material of the second semiconductor includes any one of AlGaN, alInN, alInGaN.

12. The method of manufacturing according to claim 1, further comprising: and processing the heterojunction at least by adopting an etching or ion implantation mode to form an isolation region in the heterojunction so as to realize isolation among devices.

13. The method of manufacturing according to claim 12, wherein: the thickness of the etching is 100-500nm.

14. The method of manufacturing according to claim 12, wherein: the energy of the ion implantation is 10keV-200keV, and the implantation dosage is 10 ¹³ cm ^-2 ～10 ¹⁵ cm ^-2 。

15. A GaN-based HEMT device formed by the method of fabricating a GaN-based HEMT device of any of claims 1-14.

16. The GaN-based HEMT device is characterized by comprising:

a heterojunction including a first semiconductor and a second semiconductor formed on the first semiconductor and having a band gap wider than that of the first semiconductor, and a source electrode, a drain electrode, and a gate electrode mated with the heterojunction, the heterojunction having a two-dimensional electron gas formed therein, the source electrode and the drain electrode being capable of being electrically connected by the two-dimensional electron gas;

and an insulating layer formed on the heterojunction, wherein the insulating layer is formed between the source electrode and the drain electrode, a third semiconductor is further formed on the insulating layer, the third semiconductor is distributed below the grid electrode, the insulating layer is of an amorphous structure, the insulating layer is made of any one of AlN, BN, BAlN, BGaN and BAlGaN, the insulating layer is formed by adopting a metal organic chemical vapor phase epitaxy mode, the growth temperature of the insulating layer is 300-800 ℃, or the insulating layer is formed by adopting a molecular beam epitaxy mode, the growth temperature of the insulating layer is 300-600 ℃, two-dimensional electron gas does not exist at the interface between the insulating layer and the second semiconductor, and the third semiconductor is selected from P-type semiconductors.

17. The GaN-based HEMT device of claim 16, wherein: the thickness of the insulating layer is 5-50 nm.

18. The GaN-based HEMT device of claim 16, wherein: the third semiconductor material comprises P-type BN.

19. The GaN-based HEMT device of claim 16, wherein: the first semiconductor is made of III-nitride.

20. The GaN-based HEMT device of claim 19, wherein: the material of the first semiconductor comprises GaN.

21. The GaN-based HEMT device of claim 16, wherein: the material of the second semiconductor is selected from III group nitride.

22. The GaN-based HEMT device of claim 21, wherein: the material of the second semiconductor includes any one of AlGaN, alInN, alInGaN.

23. The GaN-based HEMT device of claim 16, wherein: an interposer is also formed between the first semiconductor and the second semiconductor.

24. The GaN-based HEMT device of claim 23, wherein: the material of the insertion layer comprises AlN.

25. The GaN-based HEMT device of claim 16, wherein: the heterojunction is formed on a buffer layer formed on a substrate.

26. The GaN-based HEMT device of claim 25, wherein: the substrate comprises a homogeneous substrate or a heterogeneous substrate.

27. The GaN-based HEMT device of claim 26, wherein: the material of the homogeneous substrate comprises GaN.

28. The GaN-based HEMT device of claim 26, wherein: the material of the heterogeneous substrate comprises any one of sapphire, si and silicon carbide.