CN117497414A - Preparation method of gallium oxide field effect transistor with high electron mobility and transistor - Google Patents

Abstract

The application relates to a preparation method of a gallium oxide field effect transistor with high electron mobility and a transistor, wherein the method comprises the following steps: with Fe-dope Ga ₂ O ₃ The method comprises the steps of epitaxially growing a buffer layer, a channel layer and a barrier layer on a substrate sequentially from bottom to top, wherein the barrier layer is an n-type doped AlGaO barrier layer and an unintentionally doped barrier layer, and the channel layer is an unintentionally doped high-electron-mobility semiconductor channel layer; depositing a regrowth mask layer on the barrier layer; etching the regrowth region; regrowing a source-drain region in the regrowth region, and removing the mask; fabrication in source drain regionSource drain ohmic electrode; isolating the active region and the inactive region; depositing gate metal electrode to obtain AlGaO/high electron mobility semiconductor/Ga ₂ O ₃ A field effect transistor. The application is realized by the method that Ga ₂ O ₃ And a high electron mobility semiconductor material is added into the field effect transistor to prepare the field effect transistor device with high mobility, high voltage resistance and low electric leakage.

Description

High electron mobility gallium oxide field effect transistor preparation method and transistor

Technical field

The present application relates to the field of radio frequency technology, and specifically to a method for preparing a high electron mobility gallium oxide field effect transistor and a transistor.

Background technique

Gallium oxide (Ga ₂ O ₃ ) material is an emerging ultra-wide bandgap semiconductor material. The most common crystal structures include α, β, γ, δ, ε and transition state κ phase, with an energy band gap of 4.8-5.2. eV, the breakdown electric field is as high as 8MV/cm, which is 2.5 times that of GaN and more than 3 times that of SiC. Because the Ga ₂ O ₃ material has the advantages of high withstand voltage and low power consumption, it will have broad application value in the preparation of high-temperature, high-frequency, and high-power power electronic devices in the future.

However, the electron mobility of Ga ₂ O ₃ material is low, with a theoretical limit of only 300cm ² /V·s. Due to epitaxy and process reasons, the maximum electron mobility measured at room temperature for Ga ₂ O ₃ field effect transistors currently reported is The rate is only 180cm ² /V·s. Compared with field effect transistors of other materials, its low electron mobility limits its application in high power and high frequency.

Among other semiconductors, there are many materials whose electron mobility is significantly better than Ga ₂ O ₃ . Taking GaN as an example, it has a high electron mobility of -1200cm ² /V·s and is composed of AlGaN/GaN heterojunction. The 2DEG electron mobility of the high electron mobility field effect transistor can reach up to 2200cm ² /V·s, and the lattice mismatch between GaN and Ga ₂ O ₃ is small, which can achieve quasi-homoepitaxial growth. In addition, it is composed of Materials such as variable composition InAlGaN and AlGaN can also flexibly participate in energy band adjustment projects, bringing more possibilities to the design of Ga ₂ O ₃ field effect transistors.

The existing technical solution 1 is a Ga ₂ O ₃ metal oxide field effect transistor. A low-resistance source-drain contact is formed through heavy n-type doped Ga ₂ O ₃ contact with the metal, and a part of the Ga ₂ O ₃ trench is etched in the area below the gate. channel to increase the gate control capability, and then use Al ₂ O ₃ dielectric to isolate the gate metal from the channel, reduce the reverse gate leakage of the device, and improve the switching ratio of the device.

However, the electron mobility of the transistor device prepared by the prior art 1 is low, which is limited by the inherent characteristics of the Ga ₂ O ₃ material. At present, the mobility of this type of field effect transistor is low, and most of the reported devices are under 100 cm ² / About V·s.

The existing technical solution 2 uses the AlGaO/Ga ₂ O ₃ heterojunction to form a two-dimensional electron gas, and combines it with the delta doping method of the AlGaO barrier layer to increase the electron mobility of the field effect transistor.

However, compared with the gallium oxide MOSFET, the electron mobility of the transistor device prepared through the existing technical solution 2 has been greatly improved, but the highest only reaches 180 cm ² /V·s, which is still very low.

Contents of the invention

Based on the above statement, this application provides a high electron mobility to solve the technical problem of low electron mobility of field effect transistors.

The technical solutions of this application to solve the above technical problems are as follows:

A method for preparing a high electron mobility gallium oxide field effect transistor, including the following steps:

Step S1: Using a gallium oxide high-resistance homogeneous substrate, specifically Fe-dope Ga ₂ O ₃ as the substrate, epitaxially grow a buffer layer, a channel layer and a barrier layer on the substrate from bottom to top, as described The barrier layer is an n-type doped AlGaO barrier layer and an unintentionally doped AlGaO barrier layer, and the channel layer is an unintentionally doped high electron mobility semiconductor channel layer, wherein the AlGaO The specific composition is (Al _x Ga _1-x ) ₂ O ₃ , 0＜x≤0.3;

Step S2: deposit a regrowth mask layer on the channel layer;

Step S3, etching the re-growth area;

Step S4: Re-grow the source and drain regions in the re-growth region, and remove the mask;

Step S5: Make source and drain ohmic electrodes in the source and drain regions;

Step S6, isolate the active area and the passive area;

Step S7: Deposit a gate metal electrode to prepare an AlGaO/high electron mobility semiconductor/Ga ₂ O ₃ field effect transistor.

On the basis of the above technical solution, this application can also make the following improvements.

In some embodiments, the thickness of the substrate is 375um-675um.

In some embodiments, MOCVD (Metal Organic Chemical Vapor Deposition), MBE (Molecular Beam Epitaxy) or HVPE (Hydride Vapor Phase Epitaxy) are used to sequentially epitaxially grow a buffer layer, a channel layer and a potential layer on the substrate from bottom to top. barrier layer.

In some embodiments, the buffer layer is an unintentionally doped Ga ₂ O ₃ buffer layer, and the high electron mobility semiconductor is GaN, GaAs, AlN, InP, diamond, Si, graphene, etc. Preferably, the thickness of the buffer layer ranges from 300nm to 600nm, the thickness of the channel layer ranges from 20nm to 300nm, and the thickness of the barrier layer ranges from 12nm to 40nm, including an n-type doped barrier layer ranging from 2nm to 2nm. 10nm, unintentionally doped barrier layer 10nm~30nm. More preferably, the thickness of the buffer layer ranges from 400nm to 500nm, the thickness of the channel layer ranges from 20nm to 300nm, and the thickness of the barrier layer ranges from 12nm to 25nm, including an n-type doped barrier layer of 2nm. ~5nm, unintentionally doped barrier layer 10nm ~ 20nm.

In some embodiments , the thickness of the substrate ranges from 375um to 675um.

In some embodiments, in order to ensure good contact between each channel and the source and drain electrodes, selective etching and regrowth are used to form the source and drain electrodes. Specifically, a mask layer is first grown on the wafer, and then the source and drain regions are etched by photolithography. The mask is then etched and regrown, and the pattern of the photoresist is transferred to the regrown mask to be etched. Remove the photoresist when finished. Preferably, the mask layer includes but is not limited to various SiO ₂ , SiNx, Al ₂ O ₃ media or composite media formed from various combinations thereof, etc.

Preferably, in step S3 and the step of etching the regrowth area, Cl-based gas is used to etch the barrier layer and channel layer from top to bottom in ICP, RIE and other equipment.

In some embodiments, the step S4 is to re-grow the source and drain regions in the re-growth region, remove the mask, and use MOCVD and MBE to re-grow the etching region to grow heavily doped n-type Ga ₂ O ₃ or GaN. The growth layer, as shown in Figure 6(a), is then removed by wet method, as shown in Figure 6(b);

In some embodiments, after completing the secondary epitaxy, source and drain ohmic electrodes are produced in the source and drain regions. Specifically, photolithography is performed to define the source and drain electrode patterns, followed by metal deposition, and finally metal stripping is performed to produce the source and drain electrodes; preferably, In this step, the metal system for depositing metal is commonly used Ti/Pt/Au as an example; preferably, in this step, if the regrowth doping concentration is not high enough to directly form a good ohmic contact, annealing can also be used. Improve to form ohmic contact, the annealing temperature range is 400℃-600℃, the annealing atmosphere is nitrogen, the annealing time is 30s-1min; the structural cross-section of the electrode preparation is shown in Figure 7. In an alternative embodiment of the present application, n-type ion implantation, such as Si, Sn, and Se plasma, is used for the ohmic contact in the source and drain regions, followed by high-temperature activation, and finally Ti/Pt/Au metal is deposited at 400°C-600°C. Annealing for 30s-60s forms ohmic contact.

In some embodiments, in the step S6 of isolating the active area and the passive area, the active area and the passive area are isolated by ion implantation. Preferably, the ion is B, N, Fe or Ar.

In some embodiments, in the step S6 of isolating the active area and the passive area, the active area and the passive area are isolated by etching.

Use photoresist, dielectric, metal, etc. as an etching mask to protect the active area, and use Cl-based gas to etch the unprotected area in etching equipment such as ICP and RIE. After the etching is completed, wet Remove the etching mask and isolate the active and passive areas.

In some embodiments, in the step S7 of depositing the gate metal electrode, the metal is Ni/Au. After the gate electrode is deposited, it is peeled off to finally complete the production of the field effect transistor, as shown in Figure 7; preferably, the third step A layer of metal Ni can also be replaced with other high work function metals; more preferably, the high work function metals include but are not limited to Pt, W, Ir, WN, TiW, Pd, etc.

Compared with the existing technology, the technical solution of this application has the following beneficial technical effects:

The method for preparing a high electron mobility gallium oxide field effect transistor provided by this application effectively improves the electron mobility of the Ga ₂ O ₃ transistor by adding a high electron mobility semiconductor material to the Ga ₂ O ₃ field effect transistor, thereby producing a high mobility transistor. , high withstand voltage, low leakage field effect transistor devices.

Description of drawings

Figure 1 is a schematic cross-sectional view of a Ga ₂ O ₃ metal oxide field effect transistor in the prior art;

Figure 2 is a schematic cross-sectional view of an AlGaO/Ga ₂ O ₃ heterojunction field effect transistor in the prior art;

Figure 3 is a schematic diagram of the epitaxial structure of a gallium oxide field effect transistor provided by an embodiment of the present application;

Figure 4 is a schematic diagram of the regrowth mask and patterning of the source and drain regions provided by the embodiment of the present application;

Figure 5 is a schematic diagram of the source-drain etching re-growth area provided by the embodiment of the present application;

Figure 6(a)-Figure 6(b) are schematic diagrams of source and drain region regrowth and hard mask removal provided by embodiments of the present application;

Figure 7 is a schematic diagram of photolithography, deposition and stripping of ohmic electrodes in the source and drain regions provided by an embodiment of the present application;

Figure 8 is a schematic diagram of ion implantation isolation provided by an embodiment of the present application;

FIG. 9 is a schematic diagram of gate metal electrode production according to an embodiment of the present application.

In the picture: 1. AlGO barrier layer; 2. Si-doped AlGaO barrier layer; 3. Unintentionally doped GaN channel layer; 4. Unintentionally doped Ga ₂ O ₃ buffer layer; 5. Ga ₂ O ₃ substrate layer; 6. Regrowth mask layer; 7. Heavy doped n-type Ga ₂ O ₃ or GaN regrowth layer; 8. Source electrode; 9. Drain electrode; 10. Gate electrode.

Detailed ways

In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are given in the accompanying drawings. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing specific embodiments only and is not intended to limit the application.

Embodiment 1: The high electron mobility semiconductor is GaN.

Step 1. Prepare the epitaxial substrate, as shown in Figure 3:

Fe-dope Ga ₂ O ₃ substrate layer 5 is selected as an example, with a thickness of 375um; then an unintentionally doped Ga ₂ O ₃ buffer layer 4 is grown by MOCVD to a thickness of 300-600 nm; an unintentionally doped GaN channel layer 3. The thickness is 20nm; the delta-doped AlGaO barrier layer, specifically the Si-doped AlGaO barrier layer 2, has a thickness of 2nm. Here, Si doping is used as an example, and the unintentionally doped AlGaO barrier layer 1, The thickness is 10 nm, and the specific composition of AlGaO is (Al _x Ga _1-x ) ₂ O ₃ , 0<x≤0.3.

Step 2: Deposit the regrowth mask layer 6 on the barrier layer, as shown in Figure 4:

In order to ensure good contact between each channel and the source and drain electrodes, the source and drain electrodes are made by selective etching and regrowth. First, grow a 300nm _SiO2 mask layer on the wafer, then expose the source and drain areas through photolithography, then etch and re-grow the mask, transfer the photoresist pattern to the re-growth mask, and wait for the etching to be completed. Then remove the photoresist.

Step 3. Etch the regrowth area, as shown in Figure 5:

Use a regrowth mask as an etching mask for AlGaO and GaN, and use Cl-based gas to etch the regrowth area in the ICP equipment.

Step 4. Re-grow the source and drain areas, as shown in Figure 6:

Then, MOCVD is used to re-grow the etched area to grow a heavily doped n-type Ga ₂ O ₃ or GaN re-growth layer 7, and then the re-growth mask is removed using a wet method.

Step 5. Make source and drain ohmic electrodes in the source and drain areas, as shown in Figure 7:

After completing the secondary epitaxy, photolithography defines the source and drain electrode patterns, and then deposits metal. The metal system takes the commonly used Ti/Pt/Au as an example. Finally, metal stripping is performed to complete the production of source electrode 8 and drain electrode 9.

Step 6. Ion implantation isolation, as shown in Figure 8:

After completing the ohmic contact, use the ion implantation method to isolate the active area and the passive area, and the implanted ions are B.

Step 7. Gate electrode production, as shown in Figure 9:

After completing the ion implantation isolation, the gate metal electrode is deposited, the metal is Ni/Au, and the first layer of metal Ni is deposited. After the gate electrode 10 is deposited, it is peeled off to finally complete the production of the field effect transistor device.

Embodiment 2: The high electron mobility semiconductor is GaAs.

Step 1. Prepare epitaxial substrate

Fe-dope Ga ₂ O ₃ substrate is selected as an example, with a thickness of 375um; then an unintentionally doped Ga ₂ O ₃ buffer layer is grown by MOCVD, with a thickness of 300-600nm; an unintentionally doped high electron mobility semiconductor The channel layer, with a thickness of 20nm, is GaAs here; the delta-doped AlGaO barrier layer, with a thickness of 2nm, taking Si doping as an example here, and the unintentionally doped AlGaO barrier layer, with a thickness of 10nm, in which AlGaO The specific composition is (Al _x Ga _1-x ) ₂ O ₃ , 0<x≤0.3.

Step 2: Deposit a re-growth mask layer on the barrier layer

In order to ensure good contact between each channel and the source and drain electrodes, the source and drain electrodes are made by selective etching and regrowth. First, a 300nm SiO ₂ mask layer is grown on the wafer, and then the source and drain regions are exposed through photolithography. Then, the regrowth mask is etched, the photoresist pattern is transferred to the regrowth mask, and the photoresist is removed after the etching is completed.

Step 3. Etch the regrowth area

Use a regrowth mask as an etching mask for AlGaO and GaN, and use Cl-based gas to etch the regrowth area in the ICP equipment.

Step 4. Regrowth of source and drain areas

MOCVD is then used to re-grow the etched area to grow a heavily doped n-type Ga ₂ O ₃ or GaN re-growth layer, and then the re-growth mask is removed using a wet method.

Step 5. Make source and drain ohmic electrodes in the source and drain areas.

After completing the secondary epitaxy, photolithography defines the source and drain electrode patterns, and then deposits metal. The metal system takes the commonly used Ti/Pt/Au as an example. Finally, metal stripping is performed to complete the production of the source and drain electrodes. If the regrowth doping concentration is not high enough to directly form a good ohmic contact, it can also be improved through annealing. The annealing temperature can be 400℃-600℃, the annealing atmosphere is nitrogen, and the annealing time is 30s-1min. Structural cross-section of electrode preparation.

Step 6. Ion implantation isolation

After completing the ohmic contact, use the ion implantation method to isolate the active area and the passive area, and the implanted ions are B.

Step 7. Gate electrode production

After completing the ion implantation isolation, the gate metal electrode is deposited, the metal is Ni/Au, and the first layer of metal Ni is deposited. After the gate electrode is deposited, it is peeled off to finally complete the production of the field effect transistor device.

Embodiment 3: The high electron mobility semiconductor is InP.

Step 1. Prepare epitaxial substrate

Fe-dope Ga ₂ O ₃ substrate is selected as an example, with a thickness of 375um; then an unintentionally doped Ga ₂ O ₃ buffer layer is grown by MOCVD to a thickness of 300-600nm; an unintentionally doped high electron mobility semiconductor trench Channel layer, with a thickness of 20nm, GaAs is used here; delta-doped AlGaO barrier layer, with a thickness of 2nm, taking Si doping as an example here, and unintentionally doped AlGaO barrier layer, with a thickness of 10nm, where the specific details of AlGaO The composition is (Al _x Ga _1-x ) ₂ O ₃ , 0<x≤0.3.

Step 2: Deposit a re-growth mask layer on the barrier layer

In order to ensure good contact between each channel and the source and drain electrodes, the source and drain electrodes are made by selective etching and regrowth. First, a 300nm _SiO2 mask layer is grown on the wafer, then the source and drain areas are exposed through photolithography, and then the regrowth mask is etched to transfer the photoresist pattern to the regrowth mask. Remove the photoresist after etching is complete.

Step 3. Etch the regrowth area

Use a regrowth mask as an etching mask for AlGaO and GaN, and use Cl-based gas to etch the regrowth area in the ICP equipment.

Step 4. Regrowth of source and drain areas

MOCVD is then used to re-grow the etched area to grow a heavily doped n-type Ga ₂ O ₃ or GaN re-growth layer, and then the re-growth mask is removed using a wet method.

Step 5. Make source and drain ohmic electrodes in the source and drain areas.

After completing the secondary epitaxy, photolithography defines the source and drain electrode patterns, and then deposits metal. The metal system takes the commonly used Ti/Pt/Au as an example. Finally, metal stripping is performed to complete the production of the source and drain electrodes. If the regrowth doping concentration is not high enough to directly form a good ohmic contact, it can also be improved through annealing. The annealing temperature can be 400℃-600℃, the annealing atmosphere is nitrogen, and the annealing time is 30s-1min. Structural cross-section of electrode preparation.

Step 6. Ion implantation isolation

After completing the ohmic contact, use the ion implantation method to isolate the active area and the passive area, and the implanted ions are B.

Step 7. Gate electrode production

After completing the ion implantation isolation, the gate metal electrode is deposited, the metal is Ni/Au, and the first layer of metal Ni is deposited. After the gate electrode is deposited, it is peeled off to finally complete the production of the field effect transistor device.

Embodiment 4 : Compared with Embodiment 1, the difference of this embodiment is that the etching method is used to isolate the active area and the passive area.

Step 1. Prepare epitaxial substrate

Fe-dope Ga ₂ O ₃ substrate is selected as an example, with a thickness of 375um; then an unintentionally doped Ga ₂ O ₃ buffer layer is grown by MOCVD to a thickness of 300-600nm; an unintentionally doped high electron mobility semiconductor trench Channel layer, the thickness is 20nm, GaN is used here; delta-doped AlGaO barrier layer, the thickness is 2nm, Si-doped is used as an example here, it can also be Sn, Ge, etc., as well as unintentionally doped AlGaO barrier layer , the thickness is 10nm, and the specific composition of AlGaO is (Al _x Ga _1-x ) ₂ O ₃ , 0<x≤0.3.

Step 2: Deposit a re-growth mask layer on the barrier layer

In order to ensure good contact between each channel and the source and drain electrodes, the source and drain electrodes are made by selective etching and regrowth. First, a mask layer is grown on the wafer, then the source and drain areas are exposed through photolithography, and then the re-growth mask is etched, and the pattern of the photoresist is transferred to the re-growth mask, and the etching is completed. Then remove the photoresist.

Step 3. Etch the regrowth area

Use a regrowth mask as an etching mask for AlGaO and GaN, and use Cl-based gas to etch the regrowth area in the ICP equipment.

Step 4. Regrowth of source and drain areas

MOCVD is then used to re-grow the etched area to grow a heavily doped n-type Ga ₂ O ₃ or GaN re-growth layer, and then the re-growth mask is removed using a wet method.

Step 5. Make source and drain ohmic electrodes in the source and drain areas.

After completing the secondary epitaxy, the source and drain electrode patterns are defined by photolithography, and then metal is deposited. The metal system is commonly used Ti as an example. Finally, metal stripping is performed to complete the production of the source and drain electrodes.

Step 6. Use etching method to complete the isolation of active area and passive area;

Step 7. Gate electrode production.

After completing the ion implantation isolation, the gate metal electrode is deposited, the metal is Ni/Au, and the first layer of metal Ni is deposited. After the gate electrode is deposited, it is peeled off to finally complete the production of the field effect transistor device.

Comparative Example 1

A Ga ₂ O ₃ metal oxide field effect transistor _{is produced} by contacting heavily n-type doped Ga 2 O 3 with metal to form a low-resistance source-drain contact, and etching part of the Ga ₂ O ₃ channel in the area below the gate.

Comparative Example 2

A two-dimensional electron gas is formed through the AlGaO/Ga ₂ O ₃ heterojunction, and combined with the delta doping method of the AlGaO barrier layer, an AlGaO/Ga ₂ O ₃ heterojunction field effect transistor is produced.

Table 1 Comparison table of electron mobility of field effect transistor devices prepared in various embodiments and comparative examples

The method for preparing a high electron mobility gallium oxide field effect transistor provided in this application is based on the Ga ₂ O ₃ material system and proposes an AlGaO/high electron mobility semiconductor/Ga ₂ O ₃ field effect transistor scheme, using a semiconductor with high electron mobility As the channel layer of the Ga ₂ O ₃ field effect transistor, the prepared Ga ₂ O ₃ field effect transistor has the following technical effects:

(1) High mobility: Using semiconductors with high electron mobility as the channel layer of Ga ₂ O ₃ field effect transistors solves the problem of low electron mobility of Ga ₂ O ₃ materials and improves the output power and frequency characteristics of the device. .

(2) High withstand voltage: Ga ₂ O ₃ has a bandgap width of up to 5eV and a critical breakdown field strength of up to 8MV/cm. Using it as a barrier layer can effectively improve the withstand voltage characteristics of the device;

(3) Low leakage: Taking the 3.4eV bandgap width of GaN as an example, since its bandgap width is smaller than Ga ₂ O ₃ , the band step difference of the AlGaO/Ga ₂ O ₃ heterojunction can be further increased and the confinement of 2DEG can be increased properties, reduce the leakage of field effect transistors, improve the switching ratio of the device, reduce the operating loss of the device, and improve the power efficiency of the device.

The above are only preferred embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the protection of the present application. within the range.

Claims (9)

1. A method for preparing a gallium oxide field effect transistor with high electron mobility, comprising the following steps:

with Fe-dope Ga ₂ O ₃ The method comprises the steps of epitaxially growing a buffer layer, a channel layer and a barrier layer on a substrate sequentially from bottom to top, wherein the channel layer is an unintentionally doped high electron mobility semiconductor channel layer;

depositing a regrowth mask layer on the barrier layer;

etching the regrowth region;

regrowing a source-drain region in the regrowth region, and removing the mask;

manufacturing a source-drain ohmic electrode in the source-drain region;

isolating the active region and the inactive region;

depositing gate metal electrode to obtain AlGaO/high electron mobility semiconductor/Ga ₂ O ₃ A field effect transistor.

2. The method of manufacturing a high electron mobility gallium oxide field effect transistor according to claim 1, wherein the high electron mobility semiconductor is GaN, gaAs, alN, inP, diamond, si or graphene.

3. The method of manufacturing a high electron mobility gallium oxide field effect transistor according to claim 2, wherein the substrate has a thickness ranging from 375um to 675um, the buffer layer has a thickness ranging from 300nm to 600nm, the channel layer has a thickness ranging from 20nm to 300nm, the barrier layer has a thickness ranging from 12nm to 40nm, and the barrier layer comprises an n-type doped barrier layer ranging from 2nm to 10nm and an unintentionally doped barrier layer ranging from 10nm to 30nm.

4. The method for manufacturing a gallium oxide field effect transistor with high electron mobility according to claim 1, wherein the mask layer includes but is not limited to various kinds of SiO ₂ 、SiNx、Al ₂ O ₃ A medium or a composite medium formed from a plurality of combinations thereof.

5. The method of manufacturing a high electron mobility gallium oxide field effect transistor according to claim 1, wherein in the step of etching the regrowth region, a Cl-based gas is used to etch the barrier layer and the channel layer from top to bottom.

6. The method of manufacturing a high electron mobility gallium oxide field effect transistor according to claim 1, wherein in the step of isolating the active region and the inactive region, the active region and the inactive region are isolated by an ion implantation method.

7. The method of manufacturing a high electron mobility gallium oxide field effect transistor according to claim 6, wherein the ion is B, N, fe or Ar.

8. The method of manufacturing a high electron mobility gallium oxide field effect transistor according to claim 1, wherein in the step of depositing a gate metal electrode, the metal is Ni/Au.

9. A transistor prepared by the method of preparing a high electron mobility gallium oxide field effect transistor according to any one of claims 1 to 8.