JP2011003808A - Field effect transistor and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a field effect transistor exhibiting normally-off characteristics and operable at a high voltage.
A field effect transistor 10 of the present invention includes a nitride semiconductor multilayer body 15 having a nitrogen polarity, a gate electrode 16, a source electrode 17, and a drain electrode 18. The nitride semiconductor multilayer body 15 includes: The electron supply layer 12, the electron transit layer 13, and the barrier layer 14 are epitaxially laminated in the above order on the substrate 11, and the gate electrode 16 is disposed on the barrier layer 14. The nitride semiconductor multilayer body 15 other than the lower part of the gate electrode 16 has a recess structure, the source electrode 17 and the drain electrode 18 are disposed on the bottom surface of the recess structure, and the electron transit layer 12 and the A heterojunction 19 is formed at the interface with the electron supply layer 13.
[Selection] Figure 1

Description

  The present invention relates to a field effect transistor and a method for manufacturing the field effect transistor.

  A nitride semiconductor such as a GaN crystal is a polar crystal in which the arrangement of gallium (Ga) and nitrogen (N) is asymmetric along the c-axis and grows on a nonpolar substrate, for example, a sapphire (0001) plane However, it takes either the Ga polarity or the nitrogen polarity. Due to the performance and stability of growth during crystal formation, the above-described epitaxial multilayer body grown with the Ga polarity is generally used for electronic devices using nitride semiconductors (see, for example, Patent Document 1). ).

  In the field effect transistor using the above-described epitaxial multilayer grown with Ga polarity, a two-dimensional electron gas is formed between the electron transit layer and the electron supply layer, and this functions as a channel. With this channel, the electron traveling speed can be increased, and a sufficient gain can be provided up to the microwave / millimeter wave region. Such a field effect transistor is referred to as a high electron mobility transistor (HEMT). Examples of the combination of the electron transit layer and the electron supply layer include a combination of a GaN layer and an AlGaN layer.

The above-described field effect transistor can be used, for example, in a power control device. This power control transistor must have a normally-off (enhancement) characteristic in which no drain current flows when no gate voltage is applied (Vg = 0 V). Moreover, in order to ensure a high operating voltage, the gate leakage current must be sufficiently reduced. However, in a conventional field effect transistor using an epitaxial multilayer grown with Ga polarity, it is considered difficult to realize normally-off characteristics due to the following problems.
If an epitaxially grown AlN layer is formed as the gate insulating film, reduction of the interface state at the interface between the AlN and the underlying semiconductor and the density of trap levels in the AlN can be expected. However, when an AlN layer is formed, a large amount of positive polarization charge is generated at the interface with the underlying semiconductor, and the interface potential is lowered. As a result, the AlN layer is unlikely to function as a potential barrier. Moreover, since electrons are accumulated as carriers at this interface, it is difficult to realize normally-off characteristics.
In addition, in the region of the semiconductor layer where the electrode is not located above, the electron transit supply layer needs to have a certain thickness so that carriers are not depleted when Vg = 0V. Therefore, in order to realize the normally-off characteristic, it is necessary to form a gate recess and shorten the channel remaining distance considerably. Although the threshold voltage (Vth) varies depending on the channel remaining distance, it is difficult to precisely control the etching depth in normal dry etching. For this reason, the threshold voltage (Vth) varies and it is difficult to realize normally-off characteristics.

  Therefore, an enhancement (normally off) type device (field effect transistor) using a nitride semiconductor having nitrogen polarity has been proposed (see Patent Documents 2 and 3). Patent Document 2 describes a “smart cut method” by which a GaN substrate having a nitrogen polarity can be easily manufactured.

  FIG. 13A to FIG. 13C schematically show a method for manufacturing a GaN substrate having nitrogen polarity by this smart cut method. 13A to 13C, the same portions are denoted by the same reference numerals. As shown in FIG. 13A, first, a transition layer (nucleation layer) 133 is formed on a substrate 132 made of SiC, sapphire, Si, or the like, and a GaN layer (buffer material layer) 134 is grown on the Ga surface thereon. In this state, hydrogen atoms 135 are implanted to a desired depth to form an implantation region 136. The hydrogen atom acts to break the bond between Ga and nitrogen. Thereby, the GaN layer 134 can be separated with the implantation region 136 as a boundary.

  Next, in this state, as shown in FIG. 13B, a silicon (Si) wafer 131a is bonded onto the GaN layer 134 via a silicon dioxide bonding layer 131b. Next, an annealing strip is performed along the implantation region 136 to divide the GaN layer 134 as shown in FIG. 13C. As a result, the substrate 131 composed of the Si wafer 131a, the silicon dioxide bonding layer 131b, and the nitrogen polar GaN body 131c can be obtained. Since the nitrogen polarity GaN body 131c has nitrogen polarity, the substrate 131 is a nitrogen polarity GaN substrate.

  FIG. 14 shows an example of a field effect transistor using this nitrogen-polar GaN substrate. In this figure, the same parts as those in FIGS. 13A to 13C are denoted by the same reference numerals. As shown in FIG. 14, the field effect transistor 140 includes a GaN layer 141, an AlGaN layer 142, and a GaN layer 143 in the above order on the nitrogen-polar GaN body 131c. The GaN layer 141 is a buffer layer, the AlGaN layer 142 is a first group III nitride semiconductor body, and the GaN layer 143 is a second group III nitride semiconductor body. A gate electrode 146 is formed on the GaN layer 143 via a gate barrier material 144. A source electrode 147 and a drain electrode 148 are formed on the GaN layer 143. A recess 149 is formed between the gate electrode 146 and the source electrode 147 and between the gate electrode 146 and the drain electrode 148, and an oxide film body is formed in the recess 149. As described above, the field effect transistor 140 is a HEMT having a nitrogen polarity, and such a HEMT is referred to as an inverse HEMT (Inverse-HEMT). In this inverse HEMT, for example, a semiconductor material having a high electron affinity is used on the gate electrode side of the heterojunction and a semiconductor material having a low electron affinity is used on the substrate side of the heterojunction, such as a combination of GaN / AlGaN. This is the opposite of the case of a field effect transistor when a semiconductor having Ga polarity is used.

  The epitaxial multilayer structure in this field effect transistor has a polarization structure suitable for enhancement (normally off) characteristics. Further, in this field effect transistor, the recess structure is opposite to the case where the recess structure has Ga polarity, and the recess is formed in a region other than the region under the gate electrode. That is, since it is not necessary to form a recess in the region under the gate electrode, the threshold voltage (Vth) described above does not vary as in the case of having Ga polarity. Therefore, the threshold voltage (Vth) can be uniquely determined by the profile during epitaxial growth.

JP 2007-103955 A Special table 2009-503810 gazette Special table 2009-509343 gazette

  As described above, the power control transistor is required to operate at a high voltage. In a field effect transistor, “avalanche breakdown” occurs when a high drain voltage is applied. In the field effect transistors described in Patent Documents 2 and 3, when this “avalanche breakdown” occurs, electrons and holes are generated. Since the field effect transistors described in Patent Documents 2 and 3 do not have a discharge path for escaping the holes, the holes are accumulated in the channel during high voltage operation, and the operating voltage is lowered due to insufficient withstand voltage. There is a problem to do. This problem has been found for the first time by the present inventors.

  An object of the present invention is to provide a field effect transistor that exhibits normally-off characteristics and can operate at a high voltage, and a method for manufacturing the same.

In order to achieve the above object, the field effect transistor of the present invention comprises:
A nitride semiconductor multilayer body having nitrogen polarity, a gate electrode, a source electrode, and a drain electrode,
The nitride semiconductor multilayer body is a multilayer body in which an electron supply layer, an electron transit layer, and a barrier layer are epitaxially stacked in the above order on a substrate,
The gate electrode is disposed on the barrier layer;
The nitride semiconductor multilayer body other than the lower part of the gate electrode has a recess structure,
The source electrode and the drain electrode are disposed on a bottom surface of the recess structure;
A heterojunction is formed at an interface between the electron transit layer and the electron supply layer.

In addition, the method for producing the field effect transistor of the present invention includes:
A nitride semiconductor multilayer body forming step of forming a nitride semiconductor multilayer body having a nitrogen polarity by laminating an electron supply layer, an electron transit layer and a barrier layer on the substrate in the order described above by epitaxial growth;
Forming a gate electrode on the barrier layer; and
A recess structure forming step of forming a recess structure in the nitride semiconductor multilayer body other than the lower portion of the gate electrode;
And an electrode forming step of forming a source electrode and a drain electrode on the bottom surface of the recess structure.

  The field effect transistor of the present invention exhibits normally-off characteristics and can be operated at a high voltage. The field effect transistor of the present invention having such excellent performance can be manufactured by the method for manufacturing a field effect transistor of the present invention. However, the method of manufacturing the field effect transistor of the present invention is not limited to the method of manufacturing the field effect transistor of the present invention.

It is sectional drawing which shows the structure of an example in Embodiment 1 of the field effect transistor of this invention. It is a graph which shows the relationship between the layer thickness direction of the electron supply layer in the said example, and Al composition. It is a graph which shows the relationship between the layer thickness direction of the barrier layer in the said example, and Al composition. It is sectional drawing which shows 1 process of the manufacturing method in the said example. It is sectional drawing which shows the other process of the said manufacturing method. It is sectional drawing which shows the other process of the said manufacturing method. It is sectional drawing which shows the other process of the said manufacturing method. It is sectional drawing which shows the structure of the other example in Embodiment 1 of the field effect transistor of this invention. It is sectional drawing which shows the structure of the other example in Embodiment 1 of the field effect transistor of this invention. It is sectional drawing which shows the structure of the other example in Embodiment 1 of the field effect transistor of this invention. It is sectional drawing which shows the structure of an example in Embodiment 2 of the field effect transistor of this invention. It is sectional drawing which shows the structure of the other example in Embodiment 2 of the field effect transistor of this invention. It is a graph which shows an example of the relationship between the layer thickness direction of the barrier layer in the said example, and Al composition. It is a graph which shows the other example of the relationship between the layer thickness direction of the barrier layer in the said example, and Al composition. It is a graph which shows the relationship between the depth (layer thickness direction) and energy level in Example 1 of this invention. It is a graph which shows the relationship between the depth (layer thickness direction) and energy level in Example 2 of this invention. It is a graph which shows the relationship between the depth (layer thickness direction), conduction band energy, and carrier concentration in Example 1 of this invention. It is sectional drawing which shows 1 process of the manufacturing method of the GaN board | substrate which has nitrogen polarity. It is sectional drawing which shows the other process of the said manufacturing method. It is sectional drawing which shows the other process of the said manufacturing method. It is sectional drawing which shows an example of the conventional field effect transistor.

  Hereinafter, the field effect transistor and the method for producing the field effect transistor of the present invention will be described in detail. However, the present invention is not limited to the following embodiments.

(Embodiment 1)
FIG. 1 shows an example of the configuration of the field effect transistor of this embodiment. As illustrated, the field effect transistor 10 includes a nitride semiconductor multilayer body 15 having a nitrogen polarity, a gate electrode 16, a source electrode 17, and a drain electrode 18. The nitride semiconductor multilayer body 15 is a multilayer body in which an AlGaN layer 12, a GaN layer 13, and an AlN layer 14 are epitaxially stacked in the above order on a GaN substrate 11 having nitrogen polarity. The gate electrode 16 is provided on the AlN layer 14. A recess structure is formed in the nitride semiconductor multilayer body 15 at a portion other than the lower portion of the gate electrode 16 up to the upper end of the GaN layer 13. The source electrode 17 and the drain electrode 18 are provided on the bottom surface (on the GaN layer 13) of the recess structure. A heterojunction 19 is formed at the interface between the GaN layer 13 and the AlGaN layer 12, and a two-dimensional electron gas (2DEG) is formed on the GaN layer 13 side in the vicinity of the heterojunction 19. Yes. In the field effect transistor 10 of the present embodiment, an inverse HEMT (Inverse-HEMT) structure is formed. At the interface, the electron affinity of the gate electrode side layer (GaN layer 13) is larger than the electron affinity of the substrate side layer (AlGaN layer 12). That is, it is the opposite of the above-described field effect transistor having Ga polarity. The magnitude relationship of the electron affinity may be the opposite of the above.

In the field effect transistor of this embodiment, as described above, the AlN layer is formed on the GaN layer. For this reason, negative polarization charge is generated at the interface, and the valence band potential of the AlN layer is increased. As a result, the field effect transistor of the present embodiment exhibits normally-off characteristics. In addition, since the AlN layer effectively functions to insulate the gate electrode, it is possible to reduce gate leakage current.
Furthermore, in the field effect transistor of this embodiment, as described above, the nitride semiconductor multilayer body epitaxially stacked in the order described above is formed on a GaN substrate having nitrogen polarity. As a result, the valence band potential immediately below the gate electrode rises to a level substantially close to the Fermi level from the gate electrode to the AlN layer. As a result, holes generated by the above-mentioned “avalanche breakdown” can be discharged from the gate electrode when the gate bias (Vg) is off (Vg = 0 V). The transistor can be operated at a high voltage. In the field effect transistor of this embodiment, when the gate bias is on (Vg> 0 V), holes are injected from the gate electrode and carrier electrons increase. As a result, for example, the maximum drain current (Imax) or mutual conductance (gm) characteristics are improved.

The GaN substrate having the nitrogen polarity can be obtained by, for example, the “smart cut method” described above. In the field effect transistor of this embodiment, a GaN substrate having nitrogen polarity is used as the substrate, but the present invention is not limited to this example. The substrate only needs to be able to form a nitride semiconductor multilayer body having nitrogen polarity epitaxially stacked thereon. As the substrate, in addition to the GaN substrate having the nitrogen polarity, for example, a zirconium diboride (ZrB ₂ ) substrate perfectly lattice-matched with Al _0.15 Ga _0.85 N, a C-plane 6H—SiC substrate, Examples include sapphire (0001) substrates and Si (111). A method of forming the nitride semiconductor multilayer body on these substrates will be described later.

The AlGaN layer is formed of, for example, a material represented by Al _y Ga _1-y N (0 <y <1). The y represents an aluminum (Al) composition. The Al composition indicates, for example, the number of Al atoms contained in AlGaN. In the AlGaN layer, for example, the Al composition may be modulated in the layer thickness direction as shown in FIG. In this figure, the same parts as those in FIG. In this example, the Al composition on the substrate 11 side is 0.15 (Al _0.15 Ga _0.85 N), and the Al composition on the GaN layer 13 side is 0.2 (Al _0.2 Ga _0.8 N), and the Al composition increases linearly from the substrate 11 side toward the GaN layer 13 side. By doing so, it is possible to use the increase in conduction band potential due to the negative polarization charge, and to obtain normally-off characteristics with certainty. 2 is linear, the present invention is not limited to this example. For example, the Al composition may be modulated stepwise. In the field effect transistor of this embodiment, an AlGaN layer is used as the electron supply layer, but the present invention is not limited to this example. The electron supply layer only needs to be able to supply electrons, for example. Examples of the electron supply layer include an InAlN layer in addition to the AlGaN layer. The InAlN layer is formed of, for example, a material represented by In _z Al _1-z N (0 ≦ z ≦ 0.34). The z represents an indium (In) composition. The In composition indicates, for example, the number of In atoms contained in InAlN. The In composition may be modulated in the layer thickness direction, similar to the Al composition described above.

  In the field effect transistor of this embodiment, the AlGaN layer used as the electron supply layer also serves as a buffer layer. Thus, since the AlGaN layer can be used as a buffer layer, the buffer layer can have a high breakdown voltage. The field effect transistor of the present embodiment is not limited to this example, and the buffer layer may be a separate independent layer.

  In the field effect transistor of this embodiment, a GaN layer is used as the electron transit layer, but the present invention is not limited to this example. The electron transit layer is, for example, an undoped nitride semiconductor layer. Examples of the electron transit layer include an InGaN layer in addition to the GaN layer. In the field effect transistor of this embodiment, since the GaN layer is used as the electron transit layer, the GaN layer is used as an ohmic contact between the source electrode and the drain electrode. By using the GaN layer as the ohmic contact, for example, ohmic contact can be reduced. This effect is due to M.M. H. Wong et al. "N-Face Metal-Insulator-Semiconductor High-Electron-Mobility Transistors With AlN Back-Barrier," EDL, Vol. 29, no. 10, Oct. 2008, pp. 1101-1104.

In the field effect transistor of this embodiment, an AlN layer is used as the barrier layer, but the present invention is not limited to this example. The barrier layer is, for example, a layer using a material having a wide band gap energy. The band gap energy of the barrier layer is uniquely determined by the material forming the barrier layer. For example, in the case of an AlN layer, the band gap energy is about 6.2 eV. Examples of the barrier layer include an AlGaN layer and an InAlN layer in addition to the AlN layer. For example, Al _x Ga _1-x N (0.2 <x ≦ 1) may be used as the formation material of the AlGaN layer. When x = 1, it is AlN. For example, In _z Al _1-z N (z ≦ 0.05) may be used as the formation material of the InAlN layer. The thickness of the AlN layer is, for example, in the range of 1 to 40 nm, preferably in the range of 5 to 30 nm, and more preferably in the range of 10 to 20 nm.

The barrier layer may be doped p-type, for example. By the p-type doping of the barrier layer, for example, the valence band potential on the gate electrode side is further increased, and normally-off characteristics are improved. Although the density | concentration of the p-type dopant in the said barrier layer is not specifically limited, For example, it is the range of 1 * 10 < ¹⁷ > -1 * 10 < ²² > cm < ^-3 >. By setting the concentration of the p-type dopant in the above range, for example, the effect of discharging holes from the gate electrode when Vg = 0V and the effect of injecting holes from the gate electrode when Vg> 0V are remarkable. Become. The concentration of the p-type dopant is preferably in the range of 5 × 10 ^{18 to} 5 × 10 ²⁰ cm ⁻³ , and more preferably in the range of 1 × 10 ¹⁹ to 1 × 10 ²⁰ cm ⁻³ .

When the AlGaN layer is used as the barrier layer, for example, the Al composition of the AlGaN layer may be modulated in the layer thickness direction as shown in FIG. In this figure, the same parts as those in FIG. In this example, the Al composition on the GaN layer 13 side is 0.2 (Al _0.2 Ga _0.8 N), the Al composition on the gate electrode 16 side is 1 (AlN), and the GaN layer 13 The Al composition increases stepwise from the side toward the gate electrode 16 side. By doing so, negative polarization charges are generated in the AlGaN layer, and the valence band potential is further increased. As a result, normally-off characteristics are improved. Note that although the modulation of the Al composition shown in FIG. 3 is stepped, the present invention is not limited to this example, and for example, the Al composition may be linearly modulated.

  In the field effect transistor of this embodiment, for example, when the barrier layer is an AlGaN layer and the electron supply layer is an AlGaN layer, the Al composition of the AlGaN layer of the barrier layer is the AlGaN layer of the electron supply layer. It is larger than the Al composition.

  Any of the gate electrode, the source electrode, and the drain electrode can be conventionally known. The material for forming the gate electrode is not particularly limited, and examples thereof include Ni / Au. A material for forming the source electrode and the drain electrode is not particularly limited, and examples thereof include Ti / Mo / Au.

As described above, in the field effect transistor of this embodiment, the recess structure is formed up to the upper end of the GaN layer (electron transit layer). The purpose of forming the recess structure will be described below.
In the field effect transistor of the present embodiment, the structure of the nitride semiconductor multilayer body has a normally-off characteristic structure. Therefore, when Vg = 0 V, the above-described 2DEG is not formed, and carriers are in a depleted state. It has become. In this state, even if a gate voltage is applied (Vg> 0 V), it is difficult to form carriers by 2DEG in a region other than the lower portion of the gate electrode, and the device is not turned on.
Therefore, the aforementioned recess structure is formed in a region other than the lower portion of the gate electrode. In this case, the above-described recess structure is opposite to the case of having Ga polarity, and as shown in FIG. Therefore, since it is not necessary to form a recess structure in the region below the gate electrode, the aforementioned threshold voltage (Vth) does not vary as in the case of having Ga polarity. As a result, the threshold voltage (Vth) can be uniquely determined by, for example, a profile during epitaxial growth.

  Next, a method for manufacturing the field effect transistor according to the present embodiment will be described with reference to FIGS. 4A to 4D. 4A shows the nitride semiconductor multilayer body forming step, FIG. 4B shows the gate electrode forming step, FIG. 4C shows the recess structure forming step, and FIG. 4D shows the electrode forming step. 4A to 4D, the same parts as those in FIG.

[Nitride semiconductor multilayer body forming process]
First, the nitride semiconductor multilayer body forming step will be described. As shown in FIG. 4A, on the GaN substrate 11 having nitrogen polarity, as an electron supply layer that also serves as a buffer layer, the AlGaN layer 12 is used as an electron transit layer, the GaN layer 13 is used as a barrier layer, and the AlN layer 14 is used as a barrier layer. The layers are stacked in this order by epitaxial growth. In this way, the nitride semiconductor multilayer body 15 is formed. The GaN substrate 11 having the nitrogen polarity is produced as follows, for example. That is, first, an N-rich AlN layer is grown as a nucleation layer on a C-plane 6H—SiC substrate by plasma-assisted molecular beam epitaxy (MBE). On this, a 5000ＧａＮ (500 nm) GaN buffer layer is epitaxially grown with nitrogen polarity. In the growth of the GaN buffer layer, for example, in the first step of 1000 mm (100 nm), the high-speed growth reduces the spiral transition, and in the second step of 4000 mm (400 nm), the low-speed growth recovers the surface morphology. To implement. In this step, for example, as described above, the Al composition of the AlGaN layer 12 may be modulated in the layer thickness direction. Further, when an AlGaN layer is used as the barrier layer, the Al composition may be modulated in the layer thickness direction as described above. As the modulation method, a conventionally known method can be applied.

[Gate electrode formation process]
Next, the gate electrode forming process will be described. First, a conductive layer for forming a gate electrode is deposited on the entire surface of the nitride semiconductor multilayer body 15 on the AlN layer 14 side. Next, the conductive layer surface is patterned using a resist. Thereafter, the conductive layer is removed, for example, by reactive ion etching (RIE), leaving a portion corresponding to the gate electrode. In this way, the gate electrode 16 is formed as shown in FIG. 4B. As the material for the conductive layer and the resist, for example, a conventionally known material can be used.

[Recess structure forming process]
Next, the recess structure forming step will be described. After the gate electrode formation step, dry etching is performed using, for example, chlorine gas, BCl ₃ gas, or the like. In this way, as shown in FIG. 4C, a recess structure is formed up to the upper end of the GaN layer 13 in a portion other than the lower portion of the gate electrode 16 of the nitride semiconductor multilayer body 15.

[Electrode formation process]
Next, the electrode forming process will be described. After the recess structure forming step, patterning is performed using a resist, for example, and an ohmic electrode forming material is deposited. Thereafter, as shown in FIG. 4D, the source electrode 17 and the drain electrode 18 are formed by, for example, lift-off processing. In this manner, the field effect transistor of this embodiment can be manufactured. However, the method of manufacturing the field effect transistor of this embodiment is not limited to this example.

The manufacturing method of the field effect transistor of this embodiment other than the above manufacturing method will be described below. Here, the case of growing on a heterogeneous substrate (heteroepi substrate) other than the C-plane 6H—SiC substrate will be described. Examples of the heteroepi substrate include a sapphire (0001) substrate, a Si (111) substrate, and a ZrB ₂ substrate.

First, a method using the sapphire (0001) substrate will be described. A GaN layer is grown on the sapphire (0001) substrate by metal organic vapor phase epitaxy (MOVPE). In this case, the polarity of the GaN layer can be controlled by, for example, coaxial direct collision ion scattering spectroscopy CAICISS (Coaxial Impact-Collision Ion Scattering Spectroscopy). The polarity of the GaN layer is determined, for example, by “substrate surface treatment in a growth furnace” and “growing a buffer layer at a low temperature” in the MOVEP method. When the surface of the sapphire (0001) substrate is treated with, for example, H ₂ and then nitrided with NH ₃ at 600 ° C. or higher, AlO _t N _1-t is unevenly formed on the surface. Is done. From the first principle calculation, it is suggested that when a GaN layer or an AlN layer is grown on this AlO _t N _1-t , it grows stably with nitrogen polarity.

  Next, a polarity control method using the MBE method will be described. When a GaN layer is grown on the sapphire (0001) substrate by MBE, the surface of the sapphire (0001) substrate is nitrided with N radicals generated by high-frequency plasma (FR plasma). Since the N radical is highly reactive with the sapphire surface, nitriding proceeds even when the substrate temperature is about 200 ° C. In this state, when an AlN layer is grown on the substrate, it is suggested from the first principle calculation that the AlN layer grows stably with a nitrogen polarity due to Al being insufficient on the surface of the substrate. For example, when a GaN layer is directly grown at a high temperature (˜700 ° C.) on the substrate having a nitrided surface, the GaN layer always has a nitrogen polarity. The polarity of this GaN layer can be determined by a reflection high energy electron diffraction (RHEED) pattern. In Ga polarity, 2 × 2, 5 × 5, 6 × 4, and 1 × 1 structures appear depending on temperature and V / III ratio, whereas in N polarity, 1 × 1, 3 × 3, 6 A x6, c (6 x 12) structure appears.

  When the Si (111) substrate is used, the polarity of the GaN layer can be controlled by whether or not an AlN buffer layer is grown on the Si (111) substrate. When a GaN layer is grown without growing the AlN buffer layer, a hexagonal columnar structure characteristic of nitrogen polarity is observed.

In the case of using the ZrB ₂ substrate, it is suggested from the first principle calculation that when a GaN layer is grown on the ZrB ₂ substrate, it grows stably with nitrogen polarity. The feature of the ZrB ₂ crystal is, for example, Y. Yamada-Takamura et al. Phys. Rev. Lett. 95, 266105 (2005). It is reported in. The ZrB ₂ crystal has the same hexagonal crystal structure as the GaN crystal. The lattice mismatch between the a-axis lattice constant of the ZrB ₂ crystal and the a-axis lattice constant of the GaN crystal is as extremely small as 0.6%. The ZrB ₂ crystal is perfectly lattice matched to the Al _0.25 Ga _0.75 N crystal.

  In the field effect transistor of this embodiment, for example, the recess structure may be formed partway through the electron transit layer. FIG. 5 shows an example of the configuration of this field effect transistor. In this figure, the same parts as those in FIG. As shown in FIG. 5, in the field effect transistor 50, the recess structure is formed partway through the GaN layer 53. A heterojunction 59 is formed at the interface between the GaN layer 53 and the AlGaN layer 12. Except for these points, the field effect transistor 50 has a configuration similar to that of the field effect transistor 10 described above. Even in this case, the same effects as those of the field effect transistor 10 described above can be obtained.

  In order to form the recess structure, for example, in the recess structure formation process, the dry etching is performed to the middle of the GaN layer 53 in a portion other than the lower portion of the gate electrode 16 of the nitride semiconductor multilayer body 55. Good. Except for this point, the field effect transistor 50 can be manufactured in the same manner as the field effect transistor 10 described above. However, the manufacturing method of this field effect transistor 50 is not limited to this example.

In the field effect transistor of this embodiment, for example, an n ⁺ conductive region may be formed under at least one of the source electrode and the drain electrode. FIG. 6 shows an example of the configuration of this field effect transistor. In this figure, the same parts as those in FIG. As shown in FIG. 6, in this field effect transistor 60, there are n ⁺ conductive regions 61a in the vicinity of the lower portions of the source electrode 17 and the drain electrode 18 and in the vicinity of the entire GaN layer 53 and the upper end portion of the AlGaN layer 12, respectively. N ⁺ conductive region 61b is formed. Except for this point, the field effect transistor 60 has a configuration similar to that of the field effect transistor 50 described above. By doing in this way, contact resistance with the said source electrode and said drain electrode which are ohmic electrodes can be reduced. In this field effect transistor, an n ⁺ conductive region is formed below the both electrodes. However, the present invention is not limited to this example, and the n ⁺ conductive region can be the source electrode or the drain electrode. It may be formed only at the lower part of either of the above.

Both the n ⁺ conductive regions can be formed, for example, by performing the n ⁺ conductive region forming step after the recess structure forming step. In the n ⁺ conductive region forming step, ions are implanted into the portion corresponding to the region where the electrodes are to be formed in the bottom surface of the recess structure, for example, and an activation annealing is performed. Except for this point, the field effect transistor 60 can be manufactured in the same manner as the field effect transistor 50 described above. However, the manufacturing method of this field effect transistor 60 is not limited to this example. Examples of the ions include ²⁸ Si ⁺ , ²⁹ Si ⁺ , ³² S ⁺ , ¹³⁰ Te ⁺ , ¹⁶ O ^{+ and the} like. Conditions such as the temperature and time of the activation annealing may be appropriately set according to, for example, the type of ions.

  The field effect transistor of this embodiment may further include a gate insulating layer, for example. FIG. 7 shows a configuration of an example of this field effect transistor. In the figure, the same parts as those in FIG. As shown in FIG. 7, the field effect transistor 70 has a gate insulating layer 71 formed between the gate electrode 16 and the AlN layer 14. Except for this point, the field effect transistor 70 has the same configuration as the field effect transistor 60 described above. The band gap energy of the gate insulating layer is, for example, 5 eV or more. By forming such a gate insulating layer, for example, the potential barrier under the gate electrode can be increased, and the gate leakage current can be further reduced.

Examples of the material of the gate insulating layer include SiO ₂ , Si ₃ N ₄ , Al ₂ O ₃ , HfO ₂ , ZrO ₂ , AlN, (AlGa) ₂ O _{3 and the} like. The gate insulating layer has a thickness of, for example, 100 to 800 mm (10 to 80 nm). When the gate insulating layer is provided, the AlN layer is preferably doped p-type. By doing in this way, for example, the effect of discharging the above-described holes can be achieved more reliably.

  The gate insulating layer can be formed, for example, by performing a gate insulating layer forming step after the above-described nitride semiconductor multilayer body forming step. The gate insulating layer forming step is performed using a simple method that is not epitaxial growth such as chemical vapor deposition (CVD) or atomic layer deposition (ALD) using the above-described materials, for example. Except for this point, the field effect transistor 70 can be manufactured in the same manner as the field effect transistor 60 described above. However, the manufacturing method of this field effect transistor 70 is not limited to this example.

(Embodiment 2)
FIG. 8A shows a configuration of an example of the field effect transistor of this embodiment. In the figure, the same parts as those in FIG. As shown in FIG. 8A, in this field effect transistor 80, as a barrier layer of the nitride semiconductor multilayer body 85, an i-AlGaN layer 84b and an Al _x Ga _1-x N layer (0 <x ≦ 1) 84a are From the GaN layer 53 to the gate electrode 16, two barrier layers 84 stacked in the above order are formed. Except for this point, the field effect transistor 80 has the same configuration as the field effect transistor 60 described above. By doing so, the potential barrier as the barrier layer can be increased, and the gate leakage current can be further reduced.

In the field effect transistor of the present embodiment, the two barrier layers include the Al _x Ga _1-x N layer (0 <x ≦ 1) and the i-AlGaN layer as described above. It is not limited to examples. As in this example, the two barrier layers may be distinguished by whether or not they are undoped. For example, the two barrier layers may be distinguished by the difference in material of the layers to be formed. Alternatively, it may be a layer distinguished by stacking by modulating the Al composition. The two barrier layers may be a combination thereof. The multilayer barrier layer is not limited to two barrier layers, and may be, for example, three or more barrier layers.

In the Al _x Ga _1-x N layer (0 <x ≦ 1), for example, the Al composition may be modulated in the layer thickness direction as shown in FIG. 9A. In this figure, the same parts as those in FIG. In this example, the Al composition on the i-AlGaN layer 84b side is 0.2 (Al _0.2 Ga _0.8 N), the Al composition on the gate electrode 16 side is 1 (AlN), and the GaN The Al composition increases stepwise from the layer 53 side toward the gate electrode 16 side. Al composition of the i-AlGaN layer 84b is _{0.2 (i-Al 0.2 Ga 0.8} N). By doing so, negative polarization charges are generated in the AlGaN layer, and the valence band potential is further increased. As a result, normally-off characteristics are improved. 9A is stepped, the present invention is not limited to this example. For example, as shown in FIG. 9B, the Al composition may be linearly modulated. In this figure, the same parts as those in FIG.

The Al _x Ga _1-x N layer (0 <x ≦ 1) may be doped p-type, for example. Since the Al _x Ga _1-x N layer (0 <x ≦ 1) is doped p-type, for example, the valence band potential on the gate electrode side is further increased, and the normally-off characteristics are further improved. The concentration of the _Al x _{Ga 1-x} N layer (0 <x ≦ 1) in the p-type dopant is not particularly limited, for example, in the range of ^{1 × 10 17 ~1 × 10 22} cm -3. By setting the concentration of the p-type dopant in the above range, for example, the effect of discharging holes from the gate electrode when Vg = 0V and the effect of injecting holes from the gate electrode when Vg> 0V are remarkable. Become. The concentration of the p-type dopant is preferably in the range of 5 × 10 ^{18 to} 5 × 10 ²⁰ cm ⁻³ , and more preferably in the range of 1 × 10 ¹⁹ to 1 × 10 ²⁰ cm ⁻³ .

  In the field effect transistor of this embodiment, the above-described nitride semiconductor multilayer body forming step is performed, for example, so as to form the two barrier layers. The two barrier layers can be formed by, for example, a conventionally known method. Except for this point, the field effect transistor of this embodiment can be manufactured in the same manner as the field effect transistor 60 described above. However, the manufacturing method of the field effect transistor of this embodiment is not limited to this example.

  In the field effect transistor of this embodiment, for example, the recess structure may be formed partway through the barrier layer. FIG. 8B shows a configuration of an example of this field effect transistor. In this figure, the same parts as those in FIG. As shown in FIG. 8B, in the field effect transistor 90, the recess structure is formed partway through the i-AlGaN layer 94 b of the two barrier layers 94 in the nitride semiconductor multilayer body 95. Except for this point, the field effect transistor 90 has the same configuration as the field effect transistor 80 described above. By doing so, in this field effect transistor, for example, variations in ON resistance can be reduced.

  The above-described effects of this field effect transistor are exhibited as follows, for example. In the recess structure, the sheet carrier density of the channel formed in the 2DEG other than the lower portion of the gate electrode varies depending on the depth to be formed. As a result, the ON resistance may vary. Here, as described above, since the recess structure is formed partway through the i-AlGaN layer, variations in the sheet carrier density can be reduced, and as a result, variations in the ON resistance can be reduced. In this case, the Al composition of the AlGaN layer 12 and the i-AlGaN layer 94 is preferably the same.

  In order to form the recess structure, for example, in the recess structure formation process, the dry etching is performed on the portion of the nitride semiconductor multilayer body 95 other than the lower portion of the gate electrode 16 to the middle of the i-GaAlN layer 94b. Just do it. Except for this point, the field effect transistor 90 can be manufactured in the same manner as the field effect transistor 80 described above. However, the manufacturing method of this field effect transistor 90 is not limited to this example.

  As described above, the field effect transistor of the present invention exhibits normally-off characteristics and can operate at a high voltage. Therefore, the field effect transistor of the present invention includes, for example, a power control transistor and a microwave communication base station transistor. However, its use is not limited and can be applied to a wide range of fields.

  Next, examples of the present invention will be described. The present invention is not limited or restricted by the following examples.

[Example 1]
A field effect transistor 80 shown in FIG. 8A was produced. The configuration of the field effect transistor 80 used in Example 1 will be described below.

[Production of field effect transistor]
(1) Step of forming a nitride semiconductor multilayer body First, an N-rich AlN layer is grown as a nucleation layer on a C-plane 6H-SiC substrate by plasma-assisted MBE, and a GaN buffer layer is formed thereon with a thickness. Epitaxial growth was performed with a nitrogen polarity at 5000 mm (500 nm). In this way, a GaN substrate 11 having nitrogen polarity was produced. On the substrate 11 by plasma assisted MBE, as an electron supply layer which also serves as a buffer _layer, an _{i-Al x Ga 1-x} N layer 12 was grown to the thickness of 10000 Å (1000 nm). The Al composition x of the i-Al _x Ga _1-x N layer 12 is changed from x buf (↓) = 0.15 to x buf (↑) = 0.20 from the substrate 11 side toward the upper end. Modulated linearly. On this, an i-GaN layer 53 was grown as an electron transit layer with a thickness of 170 mm (17 nm). Next, an i-Al _0.2 Ga _0.8 N layer 84b was grown as a barrier layer on this with a thickness of 80 mm (8 nm). Further, an i-Al _x Ga _1-x N layer 84a was grown as a barrier layer with a thickness of 100 mm (10 nm) thereon. In this layer, i-Al _0.2 Ga _0.8 N has a thickness of 10 mm (1 nm), i-Al _0.4 Ga _0.6 N has a thickness of 10 mm (1 nm), and i-Al _0.6 Ga _0.4 N was grown to a thickness of 10 mm (1 nm), i-Al _0.8 Ga _0.2 N was grown to a thickness of 10 mm (1 nm), and i-AlN was grown to a thickness of 10 mm (1 nm). In this way, a nitride semiconductor multilayer body 85 (radial size: 3 inches (7.62 cm)) having nitrogen polarity was formed. The profile of this nitride semiconductor multilayer body is shown in Table 1.

(2) Gate Electrode Formation Step First, Ni / Au was deposited on the entire surface of the nitride semiconductor multilayer body 85 on the side of the barrier layer 84a in order to form a gate electrode and alignment marks. On this Ni / Au vapor deposition surface, it patterned using the resist. Thereafter, the deposited Ni / Au was removed by RIE, leaving portions such as the gate electrode and the first mark portion. Thus, the gate electrode 16 was formed.

(3) Recess Structure Formation Step In this state, dry etching was performed using chlorine gas and BCl ₃ gas to the depth where the i-GaN layer 53 remains at 130 mm (13 nm). In this way, a recess structure was formed. Table 3 shows the profile of the recess structure.

(4) n ⁺ conductive region forming step In this state, ²⁸ Si ⁺ is implanted by ion implantation into the portion corresponding to the region where the source electrode and drain electrode are to be formed in the bottom surface of the recess structure, and activated. Annealing (1150 ° C., 3 minutes) was performed. In this way, n ⁺ conductive regions 61a and 61b were formed.

(5) Electrode formation process In this state, it patterned using the resist and vapor-deposited Ti / Mo / Au as an ohmic electrode. A source electrode 17 and a drain electrode 18 were formed by lift-off processing. In this manner, the field effect transistor 80 of this example was produced.

[Example 2]
In the nitride semiconductor multilayer body forming step, the same procedure as in Example 1 was performed except that a p-Al _x Ga _1-x N layer 84a was formed instead of the i-Al _x Ga _1-x N layer 84a. Thus, the field effect transistor 80 of this example was manufactured. As an acceptor impurity (p-type dopant), magnesium was doped at a concentration of 1 × 10 ¹⁸ cm ⁻³ on an ionization base. In this layer, p-Al _0.2 Ga _0.8 N has a thickness of 10 mm (1 nm), p-Al _0.4 Ga _0.6 N has a thickness of 10 mm (1 nm), and p-Al _0.6 Ga _0.4 N was grown in the above order with a thickness of 10 mm (1 nm), p-Al _0.8 Ga _0.2 N with a thickness of 10 mm (1 nm), and p-AlN with a thickness of 10 mm (1 nm). The profile of this nitride semiconductor multilayer body is shown in Table 2.

[Evaluation of field effect transistor]
The electric characteristics of the field effect transistors of Example 1 and Example 2 were evaluated. As a result, in Example 1, the threshold voltage (Vth) was 3.5 to 4.0 V, and the withstand voltage (BVgd) was 500 V. In Example 2, Vth was 6.5 V, and BVgd was 650 V. That is, it was confirmed that the field effect transistors of both examples exhibited normally-off characteristics and were operable at a high voltage.

In Example 1, the gate leakage current (Ig) was 10 ⁻⁷ A / cm ² or less, and the gate leakage current was relatively low. In Example 2, Ig was suppressed to a low level of 10 ⁻⁸ to 10 ⁻⁹ A / cm ^2, which is comparable to the conventional MIS structure. Further, the maximum drain current (Imax) was 250 mA / mm in Example 1, and 350 mA / mm in Example 2. It should be noted that the on-resistance in both examples was not a problem, and it was confirmed that the carriers of channels other than those immediately below the gate were not depleted even at zero bias (Vg = 0 V).

  Next, the field effect transistors of Example 1 and Example 2 were analyzed in detail by numerical calculation. In both examples, the numerical calculation was performed on the assumption that the donor or acceptor was all ionized, and the Schrödinger equation and the Poisson equation were combined to obtain a self-consistent solution. Through this analysis, a one-dimensional conduction band / valence band potential incorporating a quantum mechanical effect and a carrier concentration of electrons or holes were obtained. In the carrier statistics, two-dimensional quantum statistics were adopted for two-dimensional electron gas (2DEG), and Fermi-Dirac statistics were adopted for bulk electrons and holes. For the polarization effect, an amber model was adopted, and the polarization charge was introduced as a fixed charge.

  FIG. 10 shows the distribution of the conduction band and valence band potential below the gate electrode of Example 1 in the depth direction (layer thickness direction). In this figure, the same parts as those in FIG. As shown in FIG. 10, when the gate bias (Vg) is 0 to 2 V, only the surface region of the potential changes. On the other hand, when Vg = 4V, the potential level of the heterojunction 59 portion is lower than the Fermi level (0V). Here, it can be seen that carrier electrons are generated by 2DEG and a channel is formed.

  In the case of Vg = 0 V, the valence band potential below the gate electrode rises to a level almost close to the Fermi level from directly under the gate electrode to the barrier layers 84a and 84b. As a result, in the field effect transistor of Example 1, holes generated by “avalanche breakdown” generated when operated at a high voltage are discharged from the gate electrode when Vg = 0 V, and can be operated at a high voltage. Conceivable.

FIG. 11 shows the distribution of the conduction band and valence band potential below the gate electrode of Example 2 in the depth direction (layer thickness direction). In this figure, the same parts as those in FIG. As shown in FIG. 11, when Vg is 0 to 4 V, only the surface region of the potential changes. On the other hand, when Vg = 7V, the potential level of the heterojunction 59 portion is lower than the Fermi level (0V). Here, it can be seen that carrier electrons are generated by 2DEG and a channel is formed. When Vg is a relatively low positive bias, the potential below the gate electrode is kept at 4 to 5 eV. This is presumably because the potential of the barrier layer was raised by p-type doping of the barrier layer. As a result, Vth is considered to be 6.5V. Furthermore, the potential barrier below the gate electrode is effectively thickened. For this reason, it is considered that Ig was suppressed to a low level of 10 ⁻⁸ to 10 ⁻⁹ A / cm ^2, which is comparable to the MIS structure.

  Further, when Vg = 0 V, the valence band potential below the gate electrode is raised to a level substantially close to the Fermi level from directly under the gate electrode to the barrier layers 84a and 84b. As a result, in the field effect transistor of Example 2, holes generated by “avalanche breakdown” generated when operated at a high voltage are discharged from the gate electrode when Vg = 0 V, and can be operated at a high voltage. Conceivable. In Example 2, Imax is higher than that in Example 1. This is probably because holes are injected from the gate electrode when Vg> 0V. As a result of holes being injected from the gate electrode, it is considered that the electron carriers are increased by the amount of holes injected to maintain the electrical neutral condition, and the maximum drain current Imax and the mutual conductance gm characteristics are improved.

  FIG. 12 shows the distribution of the conduction band and valence band potential in the depth direction (layer thickness direction) of the portion having the recess structure other than the lower portion of the gate electrode. In this figure, the same parts as those in FIG. As shown in FIG. 12, it can be seen that carriers are formed in the heterojunction 59 even when Vg = 0V. Since the electrode side is the GaN layer 53 having a high electron affinity at the interface of the heterojunction 59, ohmic contact can be easily obtained. Since the substrate side is the AlGaN layer 12 having a small electron affinity, it can be seen that the buffer layer has a high withstand voltage and the channel confinement effect is also good.

10, 50, 60, 70, 80, 90 Field effect transistor 11 GaN substrate having nitrogen polarity (substrate)
12 AlGaN layer (electron supply layer)
13, 53 GaN layer (electron transit layer)
14 AlN layer (barrier layer)
15, 55, 85, 95 Nitride semiconductor multilayer body 16 Gate electrode 17 Source electrode 18 Drain electrode 19, 59 Heterojunction 61a, 61b n ⁺ Conductive region 71 Gate insulating layers 84, 94 Two barrier layers (multiple barrier layers) )
84a Al _x Ga _1-x N layer (0 <x ≦ 1)
84b, 94b i-AlGaN layer 131 Nitrogen polar GaN substrate 131a Silicon (Si) wafer 131b Silicon dioxide bonding layer 131c Nitrogen polar GaN body 132 Substrate 133 Transition layer (nucleation layer)
GaN layer having 134 Ga polarity (buffer material layer)
135 Hydrogen atom 136 Injection region 140 Conventional field effect transistor 141 GaN layer (buffer layer)
142 AlGaN layer (first group III semiconductor body)
143 GaN layer (second group III semiconductor body)
144 Gate barrier material 146 Gate electrode 147 Source electrode 148 Drain electrode 149 Recess (oxide film body)

Claims (25)

A nitride semiconductor multilayer body having nitrogen polarity, a gate electrode, a source electrode, and a drain electrode,
The nitride semiconductor multilayer body is a multilayer body in which an electron supply layer, an electron transit layer, and a barrier layer are epitaxially stacked in the above order on a substrate,
The gate electrode is disposed on the barrier layer;
The nitride semiconductor multilayer body other than the lower part of the gate electrode has a recess structure,
The source electrode and the drain electrode are disposed on a bottom surface of the recess structure;
A field effect transistor, wherein a heterojunction is formed at an interface between the electron transit layer and the electron supply layer.   2. The field effect transistor according to claim 1, wherein the barrier layer includes at least one layer selected from the group consisting of an AlN layer, an AlGaN layer, and an InAlN layer.   3. The field effect transistor according to claim 1, wherein the barrier layer is doped p-type. 4. The field effect transistor according to claim 1, wherein an impurity concentration of the barrier layer is in a range of 1 × 10 ¹⁷ to 1 × 10 ²² cm ⁻³ .   5. The field effect transistor according to claim 1, wherein the recess structure is formed halfway in a layer thickness direction of the electron transit layer. 6.   6. The field effect transistor according to claim 1, wherein the electron transit layer is a GaN layer, and the electron supply layer is an AlGaN layer.   6. The field effect transistor according to claim 1, wherein the electron transit layer is an InGaN layer, and the electron supply layer is an AlGaN layer. The barrier layer is an AlGaN layer, and the electron supply layer is an AlGaN layer;
The field effect transistor according to claim 1, wherein an Al composition of the AlGaN layer of the barrier layer is larger than an Al composition of the AlGaN layer of the electron supply layer. The electron supply layer is an AlGaN layer;
The Al composition of the AlGaN layer of the electron supply layer is modulated in the layer thickness direction,
The field effect transistor according to any one of claims 1 to 8, wherein an Al composition on the electron transit layer side is larger than an Al composition on the substrate side. The barrier layer is an AlGaN layer;
The Al composition of the AlGaN layer of the barrier layer is modulated in the layer thickness direction,
The field effect transistor according to any one of claims 1 to 9, wherein an Al composition on the gate electrode side is larger than an Al composition on the electron transit layer side. The field effect transistor according to claim 1, wherein an n ⁺ conductive region is formed below at least one of the drain electrode and the source electrode.   The field effect transistor according to any one of claims 1 to 11, wherein the electron affinity of the electron transit layer is larger than the electron affinity of the electron supply layer.   The field effect transistor according to any one of claims 1 to 12, wherein the electron affinity of the electron supply layer is larger than the electron affinity of the barrier layer. Furthermore, a gate insulating layer having a band gap energy of 5 eV or more is provided.
The field effect transistor according to any one of claims 1 to 13, wherein the gate insulating layer is formed between the gate electrode and the barrier layer. Wherein the substrate, GaN substrate having a nitrogen polarity, a sapphire substrate, ZrB ₂ substrate, according to any one of 6H-SiC substrate, Si (111) from claim 1, characterized in that either the substrate 14 Field effect transistor.   The field effect transistor according to claim 1, wherein the barrier layer has a multilayer structure. The multilayer structure includes an AlN layer and the AlGaN layer;
The AlN layer is formed on the gate electrode side;
The field effect transistor according to claim 16, wherein the AlGaN layer is formed on the electron transit layer side. The Al composition of the AlGaN layer is modulated in the layer thickness direction,
The field effect transistor according to claim 17, wherein the Al composition on the AlN layer side is larger than the Al composition on the electron transit layer side.   19. The field effect transistor according to claim 17, wherein the recess structure is formed partway along the thickness direction of the AlGaN layer. A nitride semiconductor multilayer body forming step of forming a nitride semiconductor multilayer body having a nitrogen polarity by laminating an electron supply layer, an electron transit layer and a barrier layer on the substrate in the order described above by epitaxial growth;
Forming a gate electrode on the barrier layer; and
A recess structure forming step of forming a recess structure in the nitride semiconductor multilayer body other than the lower portion of the gate electrode;
An electrode forming step of forming a source electrode and a drain electrode on the bottom surface of the recess structure.   21. The method of manufacturing a field effect transistor according to claim 20, wherein in the recess structure forming step, the recess structure is formed partway through the electron transit layer. Furthermore, the area corresponding to the lower portion of the at least one electrode of the drain electrode and the source electrode, the electric field according to claim 20 or 21, wherein the containing n ⁺ conductive region formation step of forming an n ⁺ conductivity region Effect transistor manufacturing method.   The gate insulating layer forming step of forming a gate insulating layer having a band gap energy of 5 eV or more on the barrier layer of the nitride semiconductor multilayer body. A method for producing the field effect transistor according to 1.   24. The method of manufacturing a field effect transistor according to claim 20, wherein the barrier layer is formed in a multilayer in the nitride semiconductor multilayer body forming step.   25. The method of manufacturing a field effect transistor according to claim 24, wherein in the recess structure forming step, a recess structure is formed partway through the barrier layer.

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