CN118841449B - A lateral variable doping channel enhancement type gallium oxide MOS device and its preparation method - Google Patents
A lateral variable doping channel enhancement type gallium oxide MOS device and its preparation method Download PDFInfo
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Abstract
The invention discloses a transverse variable doped channel enhanced gallium oxide MOS device and a preparation method thereof, and relates to the technical field of semiconductor devices, wherein the device comprises a Fe doped semi-insulating substrate, an unintentional doped UID layer and a Si doped conductive channel region from bottom to top in sequence; the left side of the Si doped conductive channel region is provided with a p-doped region, the left side of the p-doped region is provided with an n+ region, the right side of the Si doped conductive channel region is provided with an n+ region, and the upper side of the Si doped conductive channel region is provided with source metal, gate dielectric, drain metal and gate metal. The device and the preparation method thereof have the advantages that the stability of the device in a high-temperature environment is improved due to the transverse plane structure of the grid electrode, the excellent balance between low resistance and high voltage resistance is realized through the optimization of the internal doping gradient, the application range is expanded, the leakage current of the formed pn junction is effectively turned off when the pn junction is not turned on, and the electrical performance of the device is improved.
Description
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to a transverse variable doped channel enhanced gallium oxide MOS device and a preparation method thereof.
Background
Gallium oxide (GaN) semiconductor materials have shown great potential for application in high frequency, high power electronic devices due to their excellent thermal stability, high electron mobility and large energy gap characteristics. The existing GaN-based MOS devices mostly adopt a longitudinal structure, and although the devices perform well in high-voltage application, the complicated manufacturing flow and the limitation on the grid control precision are still barriers to technical progress. In addition, conventional vertical structure devices are prone to current leakage and breakdown problems at high voltages, limiting further improvement in device performance.
Under such circumstances, the present invention proposes a lateral metamorphic channel enhancement gallium oxide MOS device. The novel structure adopts a transverse plane gate design, effectively improves the reliability of the gate, optimizes the structure of the conducting channel through a transverse variable doping technology, and realizes the dual advantages of low on-resistance and high withstand voltage. In addition, the design adopts a specific doping gradient and a pn structure, so that leakage current in a non-conducting state is effectively inhibited, and the switching ratio and the overall performance of the device are remarkably improved.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides a transverse variable doped channel enhanced gallium oxide MOS device and a preparation method thereof, so as to solve the problems in the background art.
In order to achieve the purpose, the invention provides the technical scheme that the lateral variable doped channel enhanced gallium oxide MOS device comprises an Fe doped semi-insulating substrate, wherein the Fe doped semi-insulating substrate is positioned at the bottommost end of the device, an unintentional doped UID layer is arranged above the Fe doped semi-insulating substrate, and a Si doped conductive channel region is arranged above the unintentional doped UID layer;
a p-doped region is arranged on the left side of the Si doped conductive channel region, an n+ region is arranged on the left side of the p-doped region, an n-type doped region is arranged on the right side of the Si doped conductive channel region, and an n+ region is arranged on the right side of the n-type doped region;
and a source metal and a drain metal are respectively arranged above the n+ region, a gate dielectric positioned above the Si doped conductive channel region, the n-type doped region and the p-doped region is arranged between the source metal and the drain metal, and a gate metal is arranged above the gate dielectric.
Further optimizing the technical scheme, the p-doped region is arranged not only in the Si doped conductive channel region, but also in the unintentional doped UID layer;
the unintentionally doped UID layer, although not intentionally doped, has a low concentration of Si doping due to diffusion, forming a pn junction by the distribution of the p-doped region inside it.
Further optimizing the technical scheme, the thickness of the Fe doped semi-insulating substrate is 2 mu m, the thickness of the unintentionally doped UID layer is 600nm, the thickness of the Si doped conductive channel region is 100nm, the thickness of the p-doped region is 400nm, and the thickness of the gate dielectric is 20nm.
Further optimizing the technical scheme, the doping concentration of the unintentionally doped UID layer is 2×10 16cm-3, the doping concentration of the Si doped conductive channel region is 1×10 17cm-3, the doping concentration of the n+ region is 8×10 18cm-3, the doping concentration of the n-type doped region is 2×10 18cm-3, and the doping concentration of the p-doped region is 5×10 18cm-3.
Further optimizing the technical scheme, the source electrode metal and the drain electrode metal are both of Ti-Au double-layer metal structures, the grid electrode metal is made of Ni materials, the grid electrode medium is made of alumina materials, and the thickness of the grid electrode medium is 20nm.
The preparation method of the transverse variable doped channel enhanced gallium oxide MOS device is based on the transverse variable doped channel enhanced gallium oxide MOS device, and comprises the following specific steps:
s1, growing an unintentional doping UID layer on a Fe doped semi-insulating substrate by adopting a hydride vapor phase epitaxy method;
s2, epitaxially growing a layer of Si doped conductive channel region above the unintentionally doped UID layer by adopting an MOCVD method;
S3, depositing a barrier layer on the Si doped conductive channel region, etching a through hole of the n+ region, and carrying out Mg ion implantation on the Si doped conductive channel region, wherein the ion implantation energy is 10-40kev;
s4, removing the barrier layer formed in the step S3, depositing a new barrier layer on the Si doped conductive channel region and the n+ region, etching a through hole of the n-type doped region, and carrying out Si ion implantation on the Si doped conductive channel region, wherein the ion implantation energy is 10-40kev;
S5, removing the barrier layer formed in the step S4, depositing a new barrier layer on the Si doped conductive channel region, the n-type doped region and the n+ region, etching a through hole of the p-doped region, and carrying out Si ion implantation on the Si doped conductive channel region, wherein the ion implantation energy is 10-140kev;
S6, removing the barrier layer in the step S5, redepositing a new barrier layer on the n+ region, and etching out a region of the gate dielectric;
S7, removing the barrier layer in the step S6, redepositing a new barrier layer on the gate dielectric, and etching a source metal through hole and a drain metal through hole;
S8, removing the barrier layer in the step S7, depositing a new barrier layer, etching out the area of the gate metal, and depositing the gate metal.
In the step S1, the growth condition is 900 ℃, the mole fraction of GaCl is 0.5, the air inlet speed of O 2 is 0.03m/S, the mole fraction of O 2 is 0.5, the air inlet speed of the separation gas N 2 is 2.8m/S, and the distance between the Fe doped semi-insulating substrate and the nozzle is 15cm.
In step S2, under the growth condition of 860 ℃, triethyl gallium is adopted as the organic source, high-purity oxygen is adopted as the reaction source, siH 4 is adopted as the doped Si source, and high-purity argon is adopted as the carrier gas of the organic source and the doping gas.
In step S6, the metal organic matter of aluminum is gasified at 1200 ℃ and then is introduced into the gallium oxide material reaction chamber together with the carrier gas and the oxygen to perform chemical reaction, and the reaction product is deposited on the upper surface of the device to form the aluminum oxide film.
In step S7, a magnetron sputtering method is adopted along the through hole, in an argon atmosphere, high pressure generates glow discharge to argon, and the high pressure impacts the Ti metal target, so that the sputtering time of the Ti metal target on the upper surface of the device is 5min, and after 5min, the Ti metal target is replaced to be an Au metal target, and the sputtering time is 1min.
Compared with the prior art, the invention provides a transverse variable doped channel enhanced gallium oxide MOS device and a preparation method thereof, and the device has the following beneficial effects:
The transverse plane structure of the grid electrode improves the stability and the reliability of the device under a high-temperature environment, the excellent balance between low resistance and high voltage resistance is realized through the optimization of an internal doping gradient, the application range of the device is expanded, the formed pn junction effectively turns off leakage current when not turned on, the electrical performance of the device is obviously improved, particularly the performance in high-voltage application is improved, the device not only provides important improvement on the structure of the traditional GaN device, but also opens up a new path for the development of high-performance electronic devices.
Drawings
Fig. 1 is a schematic cross-sectional view of a lateral metamorphic channel enhancement gallium oxide MOS device according to the present invention;
fig. 2 is a schematic cross-sectional view of a device in step S1 in a method for fabricating a lateral-variation-doped-channel-enhanced gallium oxide MOS device according to the present invention;
fig. 3 is a schematic cross-sectional view of a device in step S2 in the method for fabricating a lateral-variation-doped-channel-enhanced gallium oxide MOS device according to the present invention;
fig. 4 is a schematic cross-sectional view of a device in step S3 in the method for fabricating a lateral-variation-doped-channel-enhanced gallium oxide MOS device according to the present invention;
fig. 5 is a schematic cross-sectional view of a device in step S4 in the method for fabricating a lateral-variation-doped-channel-enhanced gallium oxide MOS device according to the present invention;
fig. 6 is a schematic cross-sectional view of a device in step S5 in a method for fabricating a lateral-variation-doped-channel-enhanced gallium oxide MOS device according to the present invention;
Fig. 7 is a schematic cross-sectional view of a device in step S6 in a method for fabricating a lateral-variation-doped-channel-enhanced gallium oxide MOS device according to the present invention;
Fig. 8 is a schematic cross-sectional view of a device in step S7 in a method for fabricating a lateral-variation-doped-channel-enhanced gallium oxide MOS device according to the present invention;
fig. 9 is a schematic cross-sectional view of a device in step S8 in a method for fabricating a lateral-variation-doped-channel-enhanced gallium oxide MOS device according to the present invention.
In the figure, a semi-insulating substrate is doped with 1 and Fe, a UID layer is doped unintentionally, a conductive channel region is doped with 3 and Si, a region 4 and n+ is doped with 5 and n-type doping regions, a region 6 and p-doping region, a source electrode metal, a gate electrode medium 8, a gate electrode metal 9, a gate electrode metal 10 and a drain electrode metal.
Detailed Description
The technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the embodiments of the present invention, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Examples
Referring to fig. 1, a lateral variable doped channel enhanced gallium oxide MOS device is disclosed, in which a lateral variable doped channel is adopted, and the on-resistance of the device can be reduced and the withstand voltage of the device can be improved by constructing a concentration gradient of a conducting channel, and the device comprises a Fe doped semi-insulating substrate 1, wherein the Fe doped semi-insulating substrate 1 is positioned at the bottommost end of the device, and is used for supporting the device to complete the subsequent process and reduce the substrate leakage of the device, an unintentionally doped UID layer 2 is arranged above the Fe doped semi-insulating substrate 1, and is a buffer layer of the device substrate and structure, so that defects of the device substrate are prevented from being introduced into a Si doped conducting channel region 3, but due to the diffusion effect of the Si doped conducting channel region 3, low concentration doping is generated in the device, and the unintentionally doped UID layer 2 is provided with a Si doped conducting channel region 3 above the device, and is a gate control region of the device.
The left side of the Si doped conductive channel region 3 is provided with a p-doped region 6 for realizing the low on-resistance and high withstand voltage of the device, the left side of the p-doped region 6 is provided with an n+ region 4, the right side of the Si doped conductive channel region 3 is provided with an n-type doped region 5, and the right side of the n-type doped region 5 is provided with an n+ region 4. The n + region 4 is to form a low resistance ohmic contact with the source and drain and to reduce the low resistance of the device from the source (and drain) to the device gate control conduction channel, reducing the on-resistance of the device as a whole.
Wherein the p-doped region 6 is arranged not only in the Si doped conductive channel region 3 but also in the unintentionally doped UID layer 2. Although the unintentionally doped UID layer 2 is not intentionally doped, there is a low concentration of Si doping due to diffusion, and a pn junction is formed by the distribution of the p-doped region 6 inside thereof. The leakage current of the unintentionally doped UID layer 2 is turned off when the device is not turned on, and the switching ratio of the device is improved.
A source metal 7 and a drain metal 10 are respectively arranged above the n+ region 4, a gate dielectric 8 positioned above the Si doped conductive channel region 3, the n-type doped region 5 and the p-doped region 6 is arranged between the source metal 7 and the drain metal 10, and a gate metal 9 is arranged above the gate dielectric 8.
When the positive voltage is applied to the grid electrode of the device, the p-doped region 6 starts to be in inversion from the side close to the grid electrode, an electron channel is formed, and a full-electron conducting channel from the source electrode to the drain electrode is formed, so that the device is conducted.
The source metal 7 and the drain metal 10 are both in a Ti-Au double-layer metal structure, which is because the difference of work functions of Ti metal and gallium oxide is small, ohmic contact is easier to form, au is used for performing anti-oxidation treatment on the surface of the device, and the gate metal 9 is selected for improving the high temperature resistance of the gate of the device. The gate metal 9 is Ni material, the gate dielectric is alumina material, and the thickness of the gate dielectric is 20nm.
The thickness of the Fe doped semi-insulating substrate 1 is 2 μm, the thickness of the unintentionally doped UID layer 2 is 600nm, the thickness of the Si doped conductive channel region 3 is 100nm, the thickness of the p-doped region 6 is 400nm, and the thickness of the gate dielectric 8 is 20nm.
Wherein the doping concentration of the unintentionally doped UID layer 2 is 2×10 16cm-3, the doping concentration of the Si doped conductive channel region 3 is 1×10 17cm-3, the doping concentration of the n+ region 4 is 8×10 18cm-3, the doping concentration of the n-doped region 5 is 2×10 18cm-3, and the doping concentration of the p-doped region 6 is 5×10 18cm-3.
Examples
The preparation method of the transverse variable doped channel enhanced gallium oxide MOS device is based on the preparation method of the transverse variable doped channel enhanced gallium oxide MOS device in the first embodiment, and comprises the following specific steps:
S1, as shown in FIG. 2, a layer of unintentionally doped UID layer 2 is grown on an Fe doped semi-insulating substrate 1 by adopting a hydride vapor phase epitaxy method.
The growth conditions were 900 ℃, the mole fraction of GaCl was 0.5, the air intake rate of O 2 was 0.03m/s, the mole fraction of O 2 was 0.5, the air intake rate of the spacer N 2 was 2.8m/s, and the distance from the Fe-doped semi-insulating substrate 1 to the nozzle was 15cm.
S2, as shown in fig. 3, epitaxially growing a layer of Si doped conductive channel region 3 above the unintentionally doped UID layer 2 by adopting an MOCVD method.
Under the growth condition of 860 ℃, triethyl gallium (TEGa) is adopted as an organic source, high-purity oxygen (6N) is adopted as a reaction source, siH 4 is adopted as a doped Si source, and high-purity argon (6N) is adopted as a carrier gas of the organic source and doping gas.
S3, as shown in FIG. 4, a barrier layer is deposited on the Si doped conductive channel region 3, through holes of the n+ region 4 are etched, mg ion implantation is carried out on the Si doped conductive channel region 3, and the ion implantation energy is 10-40kev.
S4, as shown in FIG. 5, removing the barrier layer formed in the step S3, depositing a new barrier layer on the Si-doped conductive channel region 3 and the n+ region 4, etching a through hole of the n-type doped region 5, and carrying out Si ion implantation on the Si-doped conductive channel region 3, wherein the ion implantation energy is 10-40kev.
S5, as shown in FIG. 6, removing the barrier layer formed in the step S4, depositing a new barrier layer on the Si doped conductive channel region 3, the n-type doped region 5 and the n+ region 4, etching a through hole of the p-doped region 6, and carrying out Si ion implantation on the Si doped conductive channel region 3, wherein the ion implantation energy is 10-140kev.
S6, as shown in FIG. 7, removing the barrier layer in the step S5, redepositing a new barrier layer on the n+ region 4, and etching out the region of the gate dielectric 8.
After gasifying the metal organic matters of aluminum under the condition of 1200 ℃ (in order to improve the deposition speed of the aluminum oxide), introducing the gasified metal organic matters of the aluminum and oxygen (the ratio of the metal organic matters of the aluminum to the oxygen is 1:1) into a square gallium oxide material reaction chamber together, and carrying out chemical reaction, wherein the reaction product is deposited on the upper surface of a device to form an aluminum oxide film.
S7, as shown in FIG. 8, removing the barrier layer in the step S6, redepositing a new barrier layer on the gate dielectric 8, and etching the source metal 7 and drain metal 10 through holes.
And (3) in a magnetron sputtering mode along the through hole, generating glow discharge to argon under high pressure in an argon atmosphere, striking the Ti metal target, enabling the Ti metal target to be splashed and deposited on the upper surface of the device for 5min, and replacing the Ti metal target into the Au metal target after 5min, wherein the sputtering time is 1min.
S8, as shown in FIG. 9, removing the barrier layer in the step S7, depositing a new barrier layer, etching the area of the gate metal 9, and depositing the gate metal 9.
The beneficial effects of the invention are as follows:
The transverse plane structure of the grid electrode improves the stability and the reliability of the device under a high-temperature environment, the excellent balance between low resistance and high voltage resistance is realized through the optimization of an internal doping gradient, the application range of the device is expanded, the formed pn junction effectively turns off leakage current when not turned on, the electrical performance of the device is obviously improved, particularly the performance in high-voltage application is improved, the device not only provides important improvement on the structure of the traditional GaN device, but also opens up a new path for the development of high-performance electronic devices.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.
Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made therein without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (9)
1. The transverse variable doped channel enhanced gallium oxide MOS device is characterized by comprising an Fe doped semi-insulating substrate, wherein the Fe doped semi-insulating substrate is positioned at the bottommost end of the device, an unintentional doped UID layer is arranged above the Fe doped semi-insulating substrate, and a Si doped conductive channel region is arranged above the unintentional doped UID layer;
a p-doped region is arranged on the left side of the Si doped conductive channel region, an n+ region is arranged on the left side of the p-doped region, an n-type doped region is arranged on the right side of the Si doped conductive channel region, and an n+ region is arranged on the right side of the n-type doped region;
A source metal and a drain metal are respectively arranged above the n+ region, a gate dielectric above the Si doped conductive channel region, the n-type doped region and the p-doped region is arranged between the source metal and the drain metal, and a gate metal is arranged above the gate dielectric;
the p-doped region is arranged not only in the Si doped conductive channel region but also in the unintentionally doped UID layer;
the unintentionally doped UID layer, although not intentionally doped, has a low concentration of Si doping due to diffusion, forming a pn junction by the distribution of the p-doped region inside it.
2. A lateral metamorphic channel enhancement gallium oxide MOS device according to claim 1, wherein the Fe-doped semi-insulating substrate has a thickness of 2 μm, the unintentionally doped UID layer has a thickness of 600nm, the Si-doped conductive channel region has a thickness of 100nm, the p-doped region has a thickness of 400nm, and the gate dielectric has a thickness of 20nm.
3. The lateral metamorphic channel enhancement gallium oxide MOS device of claim 1, wherein the unintentional doped UID layer has a doping concentration of 2 x 10 16cm-3, the Si doped conductive channel region has a doping concentration of 1 x 10 17cm-3, the n+ region has a doping concentration of 8 x 10 18cm-3, the n-doped region has a doping concentration of 2 x 10 18cm-3, and the p-doped region has a doping concentration of 5 x 10 18cm-3.
4. The lateral variable doped channel enhancement gallium oxide MOS device according to claim 1, wherein the source metal and the drain metal are both of a Ti-Au double-layer metal structure, the gate metal is Ni material, the gate dielectric is alumina material, and the thickness of the gate dielectric is 20nm.
5. A method for preparing a lateral metamorphic channel enhancement type gallium oxide MOS device, based on the lateral metamorphic channel enhancement type gallium oxide MOS device according to any one of claims 1 to 4, characterized by comprising the following specific steps:
s1, growing an unintentional doping UID layer on a Fe doped semi-insulating substrate by adopting a hydride vapor phase epitaxy method;
s2, epitaxially growing a layer of Si doped conductive channel region above the unintentionally doped UID layer by adopting an MOCVD method;
S3, depositing a barrier layer on the Si doped conductive channel region, etching a through hole of the n+ region, and carrying out Mg ion implantation on the Si doped conductive channel region, wherein the ion implantation energy is 10-40kev;
s4, removing the barrier layer formed in the step S3, depositing a new barrier layer on the Si doped conductive channel region and the n+ region, etching a through hole of the n-type doped region, and carrying out Si ion implantation on the Si doped conductive channel region, wherein the ion implantation energy is 10-40kev;
S5, removing the barrier layer formed in the step S4, depositing a new barrier layer on the Si doped conductive channel region, the n-type doped region and the n+ region, etching a through hole of the p-doped region, and carrying out Si ion implantation on the Si doped conductive channel region, wherein the ion implantation energy is 10-140kev;
S6, removing the barrier layer in the step S5, redepositing a new barrier layer on the n+ region, and etching out a region of the gate dielectric;
S7, removing the barrier layer in the step S6, redepositing a new barrier layer on the gate dielectric, and etching a source metal through hole and a drain metal through hole;
S8, removing the barrier layer in the step S7, depositing a new barrier layer, etching out the area of the gate metal, and depositing the gate metal.
6. The method according to claim 5, wherein in the step S1, the growth condition is 900 ℃, the mole fraction of GaCl is 0.5, the air intake speed of O 2 is 0.03m/S, the mole fraction of O 2 is 0.5, the air intake speed of the spacer N 2 is 2.8m/S, and the distance between the Fe-doped semi-insulating substrate and the nozzle is 15cm.
7. The method for manufacturing a lateral variable doped channel enhancement type gallium oxide MOS device according to claim 5, wherein in the step S2, under the condition that the growth condition is 860 ℃, triethylgallium is adopted as the organic source, high-purity oxygen is adopted as the reaction source, siH 4 is adopted as the doped Si source, and high-purity argon is adopted as the carrier gas of the organic source and the doped gas.
8. The method for manufacturing a lateral variable doped channel enhancement type gallium oxide MOS device according to claim 5, wherein in the step S6, after the metal organic matter of aluminum is gasified at 1200 ℃, the gasified metal organic matter is introduced into a gallium oxide material reaction chamber together with oxygen by using a carrier gas to perform a chemical reaction, and a reaction product is deposited on the upper surface of the device to form an aluminum oxide film.
9. The method for manufacturing a lateral variable doped channel enhanced gallium oxide MOS device according to claim 5, wherein in step S7, a magnetron sputtering method is adopted along the through hole, in an argon atmosphere, high pressure is used for generating glow discharge to argon, the Ti metal target is impacted, so that the Ti metal target is sputtered and deposited on the upper surface of the device for 5min, and after 5min, the Ti metal target is replaced to be an Au metal target, and the sputtering time is 1min.
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| JP2010245484A (en) * | 2009-03-17 | 2010-10-28 | Ricoh Co Ltd | Mos transistor, semiconductor device having built-in mos transistor, and electronic equipment using semiconductor device |
| CN113066857A (en) * | 2021-03-24 | 2021-07-02 | 中国科学技术大学 | High-quality factor gallium oxide transistor and preparation method thereof |
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| CN113066857A (en) * | 2021-03-24 | 2021-07-02 | 中国科学技术大学 | High-quality factor gallium oxide transistor and preparation method thereof |
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