CN118693159B - An enhanced trench gate gallium oxide switch device and a method for preparing the same - Google Patents
An enhanced trench gate gallium oxide switch device and a method for preparing the same Download PDFInfo
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Abstract
The invention discloses an enhanced trench gate gallium oxide switching device and a preparation method thereof, which relate to the technical field of semiconductors and comprise drain metal, wherein a gate dielectric is arranged in the middle part above the drain metal, an n+ substrate is arranged on the outer side of the gate dielectric, the high-voltage source device is characterized in that a current blocking layer is arranged above the n+ substrate, a Si-low resistance layer is arranged above the current blocking layer, an n+ source region is arranged above the Si-low resistance layer, source metal is arranged above the n+ source region, and gate metal is arranged in a medium groove of the gate medium. By adopting a longitudinal bottom-up structural design and combining a trench gate technology, the control capability of a gate is effectively enhanced, and meanwhile, by introducing a Si-low resistance layer below an n+ source region, the on-resistance is obviously reduced; the wide band gap gallium oxide material of the current blocking layer enables the device to bear higher voltage, reduces leakage current, improves the performance of the device and reduces manufacturing cost.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to an enhanced trench gate gallium oxide switching device and a preparation method thereof.
Background
In the field of power electronics, the performance requirements for switching devices are continually increasing, especially in high voltage and high frequency applications. Conventional silicon-based semiconductor devices do not perform well in high voltage and high temperature environments due to their physical performance limitations, which limits their use in advanced power conversion and management systems. With the technological development, gallium oxide (Ga 2O3) semiconductor materials are considered as ideal substitute materials over conventional silicon devices by virtue of their wide energy gap, high electron mobility and excellent thermal stability. However, existing gallium oxide switching devices still have some drawbacks in terms of manufacturing process and structural design. For example, conventional gallium oxide devices often suffer from limited voltage endurance, high on-resistance, and insufficient gate control capability, all of which limit their potential for use in high performance power electronic systems.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides an enhanced trench gate gallium oxide switching device and a preparation method thereof, so as to solve the problems in the prior art.
In order to achieve the above purpose, the present invention provides the following technical solutions: an enhanced trench gate gallium oxide switching device comprises drain metal, wherein the drain metal is positioned at the bottommost end of the device, a grid dielectric is arranged in the middle of the upper part of the drain metal, an n+ substrate positioned above the drain metal is arranged on the outer side of the grid dielectric, a current blocking layer positioned on the outer side of the grid dielectric is arranged above the n+ substrate, a Si-low resistance layer is arranged above the current blocking layer, an n+ source region positioned on the outer side of the grid dielectric is arranged above the Si-low resistance layer, and source metal is arranged above the n+ source region;
And gate metal is arranged in the dielectric groove of the gate dielectric, and the gate metal is flush with the n+ source region and the height of the gate dielectric.
Further optimizing the technical scheme, the device is a longitudinal device, and the device adopts a trench gate structure.
Further optimizing the technical scheme, the grid dielectric is high-K dielectric alumina, and the grid metal is Al-Au alloy.
According to the technical scheme, the current blocking layer is undoped gallium oxide, and the corresponding withstand voltage class is 160-3300V.
Further optimizing the technical scheme, the thickness of the drain metal is 800nm, the thickness of the n+ substrate is 1200nm, the thickness of the current blocking layer is 10-20 mu m, the thickness of the Si-low resistance layer is 600nm, and the thickness of the n+ source region is 200nm.
According to the technical scheme, the thickness of the bottom of the dielectric groove of the gate dielectric is 30nm higher than that of the n+ substrate, and the width of the side wall of the dielectric groove of the gate dielectric is 20nm.
Further optimizing the technical scheme, the doping concentration of the n+ substrate is 2×10 18cm-3, the doping concentration of the Si-low-resistance layer is 1×10 17cm-3, and the doping concentration of the n+ source region is 2×10 18cm-3.
The preparation method of the enhanced trench gate gallium oxide switching device is based on the enhanced trench gate gallium oxide switching device and comprises the following specific steps:
S1, depositing a protective layer above beta-type gallium oxide material of an n+ substrate, etching a through hole of a gate dielectric, etching gallium oxide along the through hole to form the gate dielectric, depositing aluminum oxide along the through hole, gasifying metal organic matters of aluminum at 1200 ℃ and then introducing the gasified metal organic matters into a gallium oxide material reaction chamber together with oxygen by using carrier gas to perform chemical reaction, and depositing a reaction product to form an aluminum oxide film;
S2, growing a current blocking layer above the gallium oxide material of the n+ substrate beta by adopting a hydride vapor phase epitaxy method;
S3, depositing a barrier layer above the current barrier layer, etching a through hole of the gate dielectric again, and etching gallium oxide along the through hole to form a dielectric groove of the gate dielectric;
S4, carrying out alumina deposition on the medium groove along the through hole in the step S3, gasifying metal organic matters of aluminum at 800 ℃, and then introducing the gasified metal organic matters into a gallium oxide material reaction chamber together by using carrier gas and oxygen to carry out chemical reaction, wherein a reaction product is deposited to form an alumina film;
S5, etching a through hole of the grid metal, generating glow discharge on argon by high pressure in an argon atmosphere along the through hole in a magnetron sputtering mode, and striking a metal target material to enable the metal target material to be splashed and deposited in the medium groove;
s6, removing the barrier layer formed in the step S3, redepositing a new barrier layer on the gate metal, etching a Si-low-resistance layer area, and implanting Si ions into the Si-low-resistance layer with implantation energy of 70-270kev;
S7, implanting Sn ions above the Si-low-resistance layer along the Si-low-resistance layer region, wherein the implantation energy is 10-70kev, and forming an n+ source region;
S8, removing the barrier layer formed in the step S3, redepositing a new barrier layer on the n+ source region, etching a source metal region, and depositing source metal.
Further optimizing the technical scheme, in the steps S1 and S4, dry etching is adopted, the radio frequency power is 600W, the chamber air pressure is 1.5Pa, the etching gas is sulfur hexafluoride and argon, and the flow ratio of the sulfur hexafluoride to the argon is 2:1.
Further optimizing the technical scheme, wherein in the step S2, the growth condition is 900 ℃, and the mole fraction of GaCl is 0.5; the air inlet speed of O 2 is 0.03m/s; the mole fraction of O 2 is 0.5; the air inlet speed of the separation air N 2 is 2.8m/s; the distance between the n+ substrate and the nozzle was 15cm.
Compared with the prior art, the invention provides an enhanced trench gate gallium oxide switching device and a preparation method thereof, and the enhanced trench gate gallium oxide switching device has the following beneficial effects:
According to the enhanced trench gate gallium oxide switching device and the preparation method thereof, the longitudinal bottom-up structural design is adopted, the trench gate technology is combined, the control capability of a gate is effectively enhanced, and meanwhile, the on-resistance is remarkably reduced by introducing the Si-low-resistance layer below the n+ source region; the wide band gap gallium oxide material of the current blocking layer enables the device to bear higher voltage, reduces leakage current, improves the performance of the device and reduces manufacturing cost.
Drawings
Fig. 1 is a schematic cross-sectional view of an enhanced trench gate gallium oxide switching device according to the present invention;
Fig. 2 is a schematic cross-sectional view of a device in step S1 in a method for fabricating an enhanced trench gate gallium oxide switching device according to the present invention;
fig. 3 is a schematic cross-sectional view of a device in step S2 in the method for manufacturing an enhanced trench gate gallium oxide switching device according to the present invention;
Fig. 4 is a schematic cross-sectional view of a device in step S3 in the method for manufacturing an enhanced trench gate gallium oxide switching device according to the present invention;
fig. 5 is a schematic cross-sectional view of a device in step S4 in the method for manufacturing an enhanced trench gate gallium oxide switching device according to the present invention;
fig. 6 is a schematic cross-sectional view of a device in step S5 in the method for manufacturing an enhanced trench gate gallium oxide switching device according to the present invention;
Fig. 7 is a schematic cross-sectional view of a device in step S6 in the method for manufacturing an enhanced trench gate gallium oxide switching device according to the present invention;
Fig. 8 is a schematic cross-sectional view of a device in step S7 in the method for manufacturing an enhanced trench gate gallium oxide switching device according to the present invention;
fig. 9 is a schematic cross-sectional view of a device in step S8 in a method for manufacturing an enhanced trench gate gallium oxide switching device according to the present invention.
In the figure: 1. a drain metal; 2. a gate dielectric; 3. an n+ substrate; 4. a current blocking layer; 5. a Si-low resistance layer; 6. an n+ source region; 7. a source metal; 8. and (3) gate metal.
Detailed Description
The technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the embodiments of the present invention, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Embodiment one:
Referring to fig. 1, an enhanced trench gate gallium oxide switching device is a vertical device, and has the characteristic of high withstand voltage, and the device adopts a trench gate structure, so that the gate has strong device control capability.
The device comprises a drain metal 1, wherein the drain metal 1 is positioned at the bottommost end of the device, a gate dielectric 2 is arranged in the middle of the upper side of the drain metal 1, an n+ substrate 3 positioned above the drain metal 1 is arranged on the outer side of the gate dielectric 2, a current blocking layer 4 positioned on the outer side of the gate dielectric 2 is arranged above the n+ substrate 3, a Si-low resistance layer 5 is arranged above the current blocking layer 4, an n+ source region 6 positioned on the outer side of the gate dielectric 2 is arranged above the Si-low resistance layer 5, and a source metal 7 is arranged above the n+ source region 6. And a gate metal 8 is arranged in the dielectric groove of the gate dielectric 2, and the gate metal 8 is flush with the n+ source region 6 and the height of the gate dielectric 2.
The gate dielectric 2 is high-K dielectric alumina, and the gate metal 8 is an al—au alloy. The grid dielectric 2 is longitudinally distributed in all thickness ranges of the device, and the grid dielectric 2 distributed in the n+ substrate 3 can bear high voltage from the substrate, so that the voltage shock resistance of the grid electrode of the device to the drain electrode is improved, and the reliability of the device is improved. The gate dielectric 2 adopts high-K dielectric alumina, so that the gate leakage current of the device can be effectively inhibited, the off-state leakage current of the device is reduced, and the gate reliability of the device is improved.
The current blocking layer 4 is undoped gallium oxide, and the corresponding voltage withstand class is 160V-3300V.
In this embodiment, the thickness of the drain metal 1 is 800nm, the thickness of the n+ substrate 3 is 1200nm, the thickness of the current blocking layer 4 is 10-20 μm, the thickness of the Si-low resistance layer 5 is 600nm, and the thickness of the n+ source region 6 is 200nm. The thickness of the bottom of the dielectric groove of the gate dielectric 2 is 30nm higher than that of the n+ substrate 3, and the width of the side wall of the dielectric groove of the gate dielectric 2 is 20nm.
The thickness of the drain metal 1 and the n+ substrate 3 is designed to ensure the supportability of the drain metal 1 and the n+ substrate 3 during the process preparation to satisfy the preparation of the thick current blocking layer 4.
The thickness of the gate dielectric 2 is designed because the drain electrode has to have a large positive voltage when the device is turned off, and enough thickness of the gate dielectric 2 is necessary to ensure that the large voltage of the drain electrode does not break through the gate dielectric 2 at the bottom of the device.
In this embodiment, the doping concentration of the n+ substrate 3 is 2×10 18cm-3, the doping concentration of the Si-low resistance layer 5 is 1×10 17cm-3, and the doping concentration of the n+ source region 6 is 2×10 18cm-3.
Because the p-type doping is difficult to realize in the gallium oxide at the present stage and the p-type leakage current is large, the p-type doping structure is not arranged in the device, the manufacturing process cost of the device can be reduced, and the leakage current of the device is reduced; because the cost of the n+ doping of the device increases sharply with the increase of depth, the device adopts the structure of the n+ source region 6 and the Si-low resistance layer 5 so as to reduce the on-resistance of the device.
Meanwhile, the voltage withstand capability of the device is realized by virtue of the current blocking layer 4, compared with a pn junction structure formed by p-type doping, the wide bandgap gallium oxide of the current blocking layer 4 has smaller electric leakage and stronger voltage withstand capability, and when a positive voltage is applied to a grid electrode, the deep trench grid can realize the formation of a conductive channel from an n+ source region 6 to a Si-low resistance layer 5 to a drain electrode on the left side and the right side of the grid electrode, so that the low-resistance conduction of the device is realized.
The n+ source region 6 is used to form an ohmic contact with the source metal 7, but as the depth increases, the cost of the gallium oxide n+ doping increases rapidly, so that a Si-low resistance layer 5 is built under the n+ source region 6, reducing the on-resistance of the device at a lower cost.
Embodiment two:
The preparation method of the enhanced trench gate gallium oxide switching device is based on the preparation method of the enhanced trench gate gallium oxide switching device in the first embodiment, and comprises the following specific steps:
S1, as shown in FIG. 2, a protective layer is deposited above a beta-type gallium oxide material of an n+ substrate 3, a through hole of a grid dielectric 2 is etched, gallium oxide is etched along the through hole to form the grid dielectric 2, the etching depth is 1.2 mu m, then aluminum oxide deposition is carried out on the grid dielectric 2 along the through hole, an aluminum metal organic matter is gasified under the condition of 1200 ℃ (in order to improve the aluminum oxide deposition speed), and then a carrier gas (generally argon) and oxygen (the ratio of the aluminum metal organic matter to the oxygen is 1:1) are used for introducing the aluminum metal organic matter and the oxygen together into a square gallium oxide material reaction chamber to carry out chemical reaction, and a product of the reaction is deposited to form an aluminum oxide film;
S2, as shown in FIG. 3, growing a current blocking layer 4 above the gallium oxide material of the n+ substrate 3β by adopting a hydride vapor phase epitaxy method;
The growth condition is 900 ℃, and the mole fraction of GaCl is 0.5; the air inlet speed of O 2 is 0.03m/s; the mole fraction of O 2 is 0.5; the air inlet speed of the separation air N 2 is 2.8m/s; the distance between the n+ substrate 3 and the nozzle is 15cm;
s3, as shown in FIG. 4, a barrier layer is deposited above the current barrier layer 4, a through hole of the gate dielectric 2 is etched again, and gallium oxide is etched along the through hole to form a dielectric groove of the gate dielectric 2;
S4, as shown in FIG. 5, carrying out alumina deposition on the medium groove along the through hole in the step S3, gasifying metal organic matters of aluminum at 800 ℃, then introducing the gasified metal organic matters into a gallium oxide material reaction chamber together with oxygen by using carrier gas, carrying out chemical reaction, and depositing a reaction product to form an alumina film;
S5, as shown in FIG. 6, etching a through hole of the grid metal 8, generating glow discharge to argon by high pressure in an argon atmosphere along the through hole in a magnetron sputtering mode, and striking a metal target material to enable the metal target material to be splashed and deposited in the medium groove;
S6, as shown in FIG. 7, removing the barrier layer formed in the step S3, redepositing a new barrier layer on the gate metal 8, etching out the Si-low resistance layer 5 area, and implanting Si ions into the Si-low resistance layer 5 with implantation energy of 70-270kev;
s7, as shown in FIG. 8, sn ion implantation is adopted above the Si-low resistance layer 5 along the Si-low resistance layer 5 area, and the implantation energy is 10-70kev, so that an n+ source region 6 is formed;
s8, as shown in FIG. 9, removing the barrier layer formed in the step S3, redepositing a new barrier layer on the n+ source region 6, etching the source metal 7 region, and depositing the source metal 7.
In the embodiment, dry etching is adopted for etching, the radio frequency power is 600W, the chamber pressure is 1.5Pa, etching gas is sulfur hexafluoride and argon, and the flow ratio of sulfur hexafluoride to argon is 2:1.
The beneficial effects of the invention are as follows:
According to the enhanced trench gate gallium oxide switching device and the preparation method thereof, the longitudinal bottom-up structural design is adopted, the trench gate technology is combined, the control capability of a gate is effectively enhanced, and meanwhile, the on-resistance is remarkably reduced by introducing the Si-low-resistance layer below the n+ source region; the wide band gap gallium oxide material of the current blocking layer enables the device to bear higher voltage, reduces leakage current, improves the performance of the device and reduces manufacturing cost.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.
Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made therein without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (9)
1. The enhanced trench gate gallium oxide switching device is characterized by comprising drain metal, wherein the drain metal is positioned at the bottommost end of the device, a gate dielectric is arranged in the middle of the upper part of the drain metal, an n+ substrate positioned above the drain metal is arranged on the outer side of the gate dielectric, a current blocking layer positioned on the outer side of the gate dielectric is arranged above the n+ substrate, a Si-low resistance layer is arranged above the current blocking layer, an n+ source region positioned on the outer side of the gate dielectric is arranged above the Si-low resistance layer, and a source metal is arranged above the n+ source region;
grid metal is arranged in the dielectric groove of the grid dielectric, and the grid metal is flush with the n+ source region and the height of the grid dielectric;
The preparation method of the device comprises the following specific steps:
S1, depositing a protective layer above beta-type gallium oxide material of an n+ substrate, etching a through hole of a gate dielectric, etching gallium oxide along the through hole to form the gate dielectric, depositing aluminum oxide along the through hole, gasifying metal organic matters of aluminum at 1200 ℃ and then introducing the gasified metal organic matters into a gallium oxide material reaction chamber together with oxygen by using carrier gas to perform chemical reaction, and depositing a reaction product to form an aluminum oxide film;
S2, growing a current blocking layer above the gallium oxide material of the n+ substrate beta by adopting a hydride vapor phase epitaxy method;
S3, depositing a barrier layer above the current barrier layer, etching a through hole of the gate dielectric again, and etching gallium oxide along the through hole to form a dielectric groove of the gate dielectric;
S4, carrying out alumina deposition on the medium groove along the through hole in the step S3, gasifying metal organic matters of aluminum at 800 ℃, and then introducing the gasified metal organic matters into a gallium oxide material reaction chamber together by using carrier gas and oxygen to carry out chemical reaction, wherein a reaction product is deposited to form an alumina film;
S5, etching a through hole of the grid metal, generating glow discharge on argon by high pressure in an argon atmosphere along the through hole in a magnetron sputtering mode, and striking a metal target material to enable the metal target material to be splashed and deposited in the medium groove;
s6, removing the barrier layer formed in the step S3, redepositing a new barrier layer on the gate metal, etching a Si-low-resistance layer area, and implanting Si ions into the Si-low-resistance layer with implantation energy of 70-270kev;
S7, implanting Sn ions above the Si-low-resistance layer along the Si-low-resistance layer region, wherein the implantation energy is 10-70kev, and forming an n+ source region;
S8, removing the barrier layer formed in the step S3, redepositing a new barrier layer on the n+ source region, etching a source metal region, and depositing source metal.
2. An enhanced trench gate gallium oxide switching device according to claim 1, wherein the device is a vertical device and the device employs a trench gate structure.
3. The enhancement mode trench-gate gallium oxide switching device of claim 1, wherein the gate dielectric is high K dielectric alumina and the gate metal is an Al-Au alloy.
4. The enhancement mode trench-gate gallium oxide switching device of claim 1, wherein the current blocking layer is undoped gallium oxide and has a withstand voltage rating of 160 v-3300 v.
5. An enhanced trench-gate gallium oxide switching device according to claim 1, wherein the drain metal has a thickness of 800nm, the n+ substrate has a thickness of 1200nm, the current blocking layer has a thickness of 10-20 μm, the Si-low resistance layer has a thickness of 600nm, and the n+ source region has a thickness of 200nm.
6. The enhancement mode trench-gate gallium oxide switching device of claim 1, wherein the gate dielectric has a dielectric trench bottom thickness 30nm greater than the thickness of the n+ substrate and a dielectric trench sidewall width of 20nm.
7. The enhancement mode trench-gate gallium oxide switching device according to claim 1, wherein the n+ substrate has a doping concentration of 2 x 10 18cm-3, the Si-low resistance layer has a doping concentration of 1 x 10 17cm-3, and the n+ source region has a doping concentration of 2 x 10 18cm-3.
8. The enhancement mode trench gate gallium oxide switching device according to claim 1, wherein in steps S1 and S4, dry etching is adopted for etching, the radio frequency power is 600W, the chamber pressure is 1.5Pa, the etching gas is sulfur hexafluoride and argon, and the flow ratio of sulfur hexafluoride to argon is 2:1.
9. The enhancement mode trench-gate gallium oxide switching device according to claim 1, wherein in step S2, the growth condition is 900 ℃ and the molar fraction of GaCl is 0.5; the air inlet speed of O 2 is 0.03m/s; the mole fraction of O 2 is 0.5; the air inlet speed of the separation air N 2 is 2.8m/s; the distance between the n+ substrate and the nozzle was 15cm.
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