CN107437566B - Semiconductor longitudinal double-diffusion metal oxide semiconductor field effect transistor with composite dielectric layer wide band gap and manufacturing method thereof - Google Patents

Abstract

The invention provides a wide-band-gap longitudinal double-diffused metal oxide semiconductor field effect transistor (VDMOS) with a Composite Dielectric Layer (CDL) and a manufacturing method thereof. When the device is turned off, the SIPOS column and the High K dielectric layer have uniform electric fields, and the electric fields in the drift region of the device are uniformly distributed through electric field modulation. Meanwhile, the SIPOS column and the High K dielectric layer assist in depleting the drift region, so that the depletion capability of the drift region of the device is greatly improved, the doping concentration of the drift region of the device is increased, and the on-resistance is reduced. When the device is started, the side wall of the drift region is provided with a majority carrier accumulation layer, so that the on-resistance of the device is further reduced.

Description

A longitudinal double-diffused metal oxide semi-conductor with a wide-bandgap semiconductor composite dielectric layer Conductor field effect transistor and method of making the same

technical field

The present invention relates to the field of semiconductor devices, in particular to a trench type vertical double-diffused metal oxide semiconductor field effect transistor.

Background technique

Wide bandgap semiconductor materials have the characteristics of large forbidden band width, high critical breakdown electric field, high thermal conductivity and high electron saturation drift velocity, so they have very broad application prospects in the field of high power, high temperature and high frequency power electronics. At present, among the field effect transistors with wide band gap semiconductor typical SiC as the substrate, the vertical double diffused metal oxide semiconductor field effect transistor (VDMOS) is one of the widely studied objects. In 1985, a trench (Trench) MOS structure was proposed by D. Ueda et al. Using the U-shaped trench structure makes the conduction channel of the device change from horizontal to vertical, which effectively eliminates the resistance of the JFET, greatly increases the density of the original cell, and improves the current handling capability of the device. However, in the high-voltage application field of power devices, as the breakdown voltage of the device increases, the thickness of the power VDMOS epitaxial layer continues to increase, and the doping concentration of the drift region gradually decreases, resulting in the on-resistance of the device. increase, so that the conduction loss of the device increases.

SUMMARY OF THE INVENTION

The invention proposes a vertical double-diffused metal oxide semiconductor field effect transistor (VDMOS) with a wide band gap semiconductor with a composite dielectric layer (Composite Dielectric Layer, CDL), aiming to further optimize the breakdown voltage and specific conduction of the wide band gap semiconductor VDMOS device. The paradox of resistance.

The technical scheme of the present invention is as follows:

A longitudinal double-diffused metal-oxide-semiconductor field effect transistor with a wide-bandgap semiconductor compound dielectric layer, comprising:

The substrate of semiconductor material, which doubles as a drain region;

A drift region formed by epitaxial growth on the substrate;

Left and right base regions formed by doping on the top surface of the drift region;

Doping on the upper portion of the base region is in contact with the source region and the channel substrate respectively formed;

a source electrode formed on the upper surface of the contact between the source region and the channel substrate;

a drain formed on the lower surface of the drain region;

What is different from the existing VDMOS is:

The materials of the substrate and the drift region are wide-bandgap semiconductor materials, and the trenches are etched between the left and right base regions, and the trenches pass through the drift region to the drain region of the substrate in the longitudinal direction; The aspect ratio is determined according to the length and width of the drift region of the device, and the length of the drift region is determined according to the breakdown voltage requirements;

The gate insulating layer and the oxygen-doped semi-insulating polysilicon layer are sequentially formed on the sidewalls of the trench, so that the longitudinal ends of the semi-insulating polysilicon layer are connected to the gate and drain ends of the device; the longitudinal surface of the semi-insulating polysilicon layer corresponds to the base region It is a heavily doped region; a gate corresponding to the base region is formed on the longitudinal surface of the semi-insulating polysilicon layer.

High K dielectric is filled in the trench whose surface becomes a semi-insulating polysilicon layer, and the height of the High K dielectric and the longitudinal direction of the drift region is the same.

On the basis of the above scheme, the present invention has also made the following optimizations:

The relative permittivity of High K materials is 100-2000.

The width of the High K dielectric in the lateral direction (that is, the width of the trench whose surface becomes the semi-insulating polysilicon layer) is 0.2-5 μm.

The thickness of the gate insulating layer is determined according to the threshold voltage, and the typical value is 0.02-0.1 μm.

The doping concentration of the substrate of the wide-bandgap semiconductor material is the concentration of general material preparation or doping, and the typical value ranges from 1×10 ¹³ cm ^-3 to 1×10 ¹⁵ cm ^-3 .

When the breakdown voltage is required to be 1200V, the aspect ratio is 10:1 to 20:1; when the breakdown voltage is required to be 600V, the aspect ratio is 5:1-10:1.

The thickness of the semi-insulating polysilicon layer is 0.2 to 1.5 μm. The oxygen doping ratio of the semi-insulating polysilicon layer is 15% to 35%, and the corresponding resistivity thereof is 10 ⁹ to 10 ¹¹ Ω·cm.

The doping concentration of the heavily doped region in the semi-insulating polysilicon layer is 10 ¹⁸ -10 ²⁰ cm ^-3 .

The wide band gap semiconductor material can be selected from gallium nitride, silicon carbide, diamond, etc.

A method for making the above composite dielectric layer vertical double-diffused metal oxide semiconductor field effect transistor based on a wide band gap semiconductor substrate, comprising the following steps:

1) Take the substrate of the wide-bandgap semiconductor material as the drain region;

2) forming an epitaxial layer on the substrate as a drift region;

3) forming a base region by ion implantation in the upper part of the drift region;

4) Etch the trench in the base region so that the trench passes down through the drift region to the drain region;

5) forming a gate insulating layer on the sidewall of the trench;

6) depositing a semi-insulating polysilicon layer outside the gate insulating layer and doped with oxygen;

7) Filling the High K medium in the region corresponding to the drift region longitudinally in the trench;

8) Doping the base region to form contact between the source region and the channel substrate;

9) heavily doping the area corresponding to the base region on the surface of the semi-insulating polysilicon layer in the trench, and depositing polysilicon to form a gate;

10) The contact surface of the source region and the channel substrate forms a source electrode;

11) A drain is formed on the surface of the drain region.

The beneficial effects of the technical solution of the present invention are as follows:

Using deep trench technology, a semi-insulating polysilicon (SIPOS) layer is formed on the sidewall of the drift region of the VDMOS device, and its two ends are respectively connected to the gate electrode and the drain electrode of the device (connecting to the drain region can be regarded as being connected to the drain electrode). The voids in the middle of the SIPOS layer are partially filled with High K material. When the device is turned off, the composite dielectric layer composed of SIPOS and High K has a uniform electric field. Through the electric field modulation, the overall electric field in the drift region of the device becomes uniform. At the same time, the composite dielectric layer increases the depletion capability of the device. In the case of the SIPOS layer or only the High K layer, the depletion capability of the device is enhanced, that is, the doping concentration of the device drift region is greatly increased, and the device has a lower conduction loss when the device is turned on. When the device is turned on, the composite dielectric layer accumulates more majority carriers on the device drift region, and the on-resistance of the device is further reduced.

In conclusion, CBL VDMOS device based on wide band gap semiconductor material has higher withstand voltage and lower conduction loss under the same drift region length compared with traditional wide band gap semiconductor VDMOS and silicon-based VDMOS devices. , CBL VDMOS devices have better performance.

Description of drawings

FIG. 1 is a schematic structural diagram (front view) of an embodiment of the present invention, and the device structure is mirror-symmetrical along the dotted line in the figure.

Description of reference numbers:

1-source; 2-gate insulating layer; 3-semi-insulating polysilicon layer; 4-gate; 5-High K material; 6-drain; 7-substrate drain region; 8-drift region; 9-base region ; 10-channel substrate contact; 11-source region.

Detailed ways

As shown in Figure 1, the vertical double-diffused metal-oxide-semiconductor field effect transistor based on the wide band gap semiconductor composite dielectric layer includes:

In the substrate drain region 7 of the wide band gap semiconductor material, the doping concentration is determined according to the growth conditions and doping process of the wide band gap semiconductor, and the typical value ranges from 1×10 ¹² cm ^-3 to 1×10 ¹⁵ cm ^-3 ;

The drift region 8 formed by the epitaxial layer on the substrate;

a base region 9 formed by doping on the drift region;

Etch a trench on the base region, and the trench goes down through the drift region to the drain region of the substrate;

The gate insulating layer 2 formed on the sidewall of the trench has a thickness of 0.02-0.1 μm;

An oxygen-doped semi-insulating polysilicon layer 3 is deposited outside the gate insulating layer; the thickness of the semi-insulating polysilicon layer is 0.2-1.5 μm; the oxygen-doping ratio of the semi-insulating polysilicon layer is 15%-35%, and its corresponding resistivity is 10 ⁹ ～10 ¹¹ Ω·cm;

Fill the high K dielectric material in the area corresponding to the drift region 8 in the longitudinal direction in the trench, and the relative permittivity is 100-1000; the width of the High K dielectric in the lateral direction is 0.2-5 μm;

Doping on the base region forms the source region 11 and the channel substrate contact 10 respectively;

Performing high-concentration doping (for example, 10 ¹⁸ -10 ²⁰ cm ^-3 ) on the surface of the semi-insulating polysilicon layer 3 corresponding to the base region in the longitudinal direction, and forming the gate 4;

A source electrode is formed on the source region 11 and the channel substrate contact 10 .

The SIPOS layer is formed on the sidewall of the drift region of the VDMOS device by using the deep trench technology, and its two ends are respectively connected to the gate electrode and the drain electrode of the device (connecting to the drain region can be regarded as being connected to the drain electrode). The voids in the middle of the SIPOS layer are partially filled with High K material. When the device is turned off, the composite dielectric layer composed of SIPOS and High K has a uniform electric field. Through the electric field modulation, the overall electric field in the drift region of the device becomes uniform. At the same time, the composite dielectric layer increases the depletion capability of the device. In the case of the SIPOS layer or only the High K layer, the depletion capability of the device is enhanced, that is, the doping concentration of the device drift region is greatly increased, and the device has a lower conduction loss when the device is turned on. When the device is turned on, the composite dielectric layer accumulates more majority carriers on the device drift region, and the on-resistance of the device is further reduced.

Taking the N-channel wide-bandgap semiconductor VDMOS as an example, it can be prepared by the following steps:

1) The substrate of the wide band gap semiconductor material is used as the drain region;

2) forming an N-type drift region on the epitaxial layer on the drain region of the substrate;

3) A P-type base region is formed on the N-type drift region by ion implantation;

4) Etch a trench on the P-type base region, and pass through the drift region below the trench to the drain region of the substrate; the aspect ratio of the trench is determined according to the length and width of the drift region of the device, and the length of the drift region is determined according to the breakdown The voltage requirements are determined; when the breakdown voltage is required to be 1200V, the aspect ratio is 10:1 to 20:1; when the breakdown voltage is required to be 600V, the aspect ratio is 5:1-10:1;

5) forming a gate insulating layer on the sidewall of the trench;

6) A thin SIPOS layer is deposited outside the gate insulating layer and doped with oxygen;

7) Filling the High K dielectric material in the longitudinal drift zone region in the trench;

8) respectively forming source region and channel substrate contacts by ion implantation in the base region;

9) Doping the SIPOS layer with high concentration by ion implantation in the trench, that is, the outer region of the base region;

10) depositing polysilicon in the base region region inside the trench to form a gate electrode;

11) A passivation layer is deposited on the surface of the device, and the contact hole is etched;

12) depositing metal and etching to form source and gate electrodes;

13) A drain electrode is formed on the drain region of the substrate.

Through Sentaurus simulation, the performance of the novel device proposed by the present invention is greatly improved compared with the traditional device, and the on-resistance of the novel device is reduced by 60% under the same breakdown voltage of the two devices.

Of course, the wide-bandgap semiconductor VDMOS in the present invention can also be a P-type channel, and its structure is equivalent to that of an N-channel VDMOS, which should be regarded as belonging to the protection scope of the claims of the present application, and will not be repeated here.

The above are only the preferred embodiments of the present invention. It should be pointed out that for those skilled in the art, without departing from the technical principle of the present invention, several improvements and replacements can be made. These improvements and replacements The solution also falls within the protection scope of the present invention.

Claims (10)

1. A longitudinal double-diffused metal-oxide-semiconductor field effect transistor with a wide-bandgap semiconductor compound dielectric layer, comprising: The substrate of semiconductor material, which doubles as a drain region; A drift region formed by epitaxial growth on the substrate; Left and right base regions formed by doping on the top surface of the drift region; Doping on the upper portion of the base region is in contact with the source region and the channel substrate respectively formed; a source electrode formed on the upper surface of the contact between the source region and the channel substrate; a drain formed on the lower surface of the drain region; It is characterized by: The material of the substrate and the drift region is a wide band gap semiconductor material, a trench is formed by etching between the left and right base regions, and the trench passes through the drift region to the drain region of the substrate in the longitudinal direction; The aspect ratio is determined according to the length and width of the drift region of the device, and the length of the drift region is determined according to the breakdown voltage requirements of the device; The gate insulating layer and the oxygen-doped semi-insulating polysilicon layer are sequentially formed on the sidewalls of the trench, so that the longitudinal ends of the semi-insulating polysilicon layer are connected to the gate and drain ends of the device; the longitudinal surface of the semi-insulating polysilicon layer corresponds to the base region is a heavily doped region, and a gate is formed in the heavily doped region; High K dielectric is filled in the trench whose surface becomes a semi-insulating polysilicon layer, and the height of the High K dielectric and the longitudinal direction of the drift region is the same. 2 . The vertical double-diffused metal-oxide-semiconductor field effect transistor with a wide-bandgap semiconductor compound dielectric layer according to claim 1 , wherein the relative permittivity of the High K material is 100-2000. 3 . 3 . The vertical double-diffused metal-oxide-semiconductor field effect transistor with a wide band gap semiconductor with a composite dielectric layer according to claim 2 , wherein the width of the High K dielectric in the lateral direction is 0.2-5 μm. 4 . 4 . The vertical double-diffused metal-oxide-semiconductor field effect transistor with a wide-bandgap semiconductor compound dielectric layer according to claim 1 , wherein the thickness of the gate insulating layer is set according to the threshold voltage, and the typical value is 0.02-0.1 μm. 5 . 5 . The longitudinal double-diffused metal-oxide-semiconductor field effect transistor with a wide-bandgap semiconductor compound dielectric layer according to claim 1 , wherein the doping concentration of the substrate is 1×10 ¹³ cm ⁻³ to 1×10 ¹⁵ . cm ^-3 . 6 . The vertical double-diffused metal-oxide-semiconductor field effect transistor with a wide-bandgap semiconductor compound dielectric layer according to claim 1 , wherein: when the breakdown voltage is required to be 1200V, the aspect ratio of the trench is 10:1～ 20:1; when the breakdown voltage is 600V, the aspect ratio of the trench is 5:1-10:1. 7 . The vertical double-diffused metal oxide semiconductor field effect transistor with a wide band gap semiconductor with a composite dielectric layer according to claim 1 , wherein the thickness of the semi-insulating polysilicon layer is 0.2-1.5 μm; The ratio is 15% to 35%, and the corresponding resistivity is 10 ⁹ to 10 ¹¹ Ω·cm. 8 . The vertical double-diffused metal-oxide-semiconductor field effect transistor with a wide-bandgap semiconductor compound dielectric layer according to claim 1 , wherein the doping concentration of the heavily doped region in the semi-insulating polysilicon layer is 10 ¹⁸ - 10 . 10 ²⁰ cm ^-3 . 9 . The vertical double-diffused metal-oxide-semiconductor field effect transistor with a wide-bandgap semiconductor with a composite dielectric layer according to claim 1 , wherein the wide-bandgap semiconductor material is gallium nitride, silicon carbide or diamond. 10 . 10. A method for manufacturing the wide band gap semiconductor vertical double-diffused metal oxide semiconductor field effect transistor with composite dielectric layer according to claim 1, comprising the following steps: 1) Take the substrate of the wide-bandgap semiconductor material as the drain region; 2) forming an epitaxial layer on the substrate as a drift region; 3) forming a base region by ion implantation in the upper part of the drift region; 4) Etch the trench in the base region so that the trench passes down through the drift region to the drain region; 5) forming a gate insulating layer on the sidewall of the trench; 6) depositing a semi-insulating polysilicon layer outside the gate insulating layer; 7) Filling the High K medium in the region corresponding to the drift region longitudinally in the trench; 8) Doping the base region to form contact between the source region and the channel substrate; 9) heavily doping the area corresponding to the base region on the surface of the semi-insulating polysilicon layer in the trench, and depositing polysilicon to form a gate; 10) The contact surface of the source region and the channel substrate forms a source electrode; 11) A drain is formed on the surface of the drain region.

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