CN106158973A - A kind of accumulation type DMOS - Google Patents
A kind of accumulation type DMOS Download PDFInfo
- Publication number
- CN106158973A CN106158973A CN201610532247.7A CN201610532247A CN106158973A CN 106158973 A CN106158973 A CN 106158973A CN 201610532247 A CN201610532247 A CN 201610532247A CN 106158973 A CN106158973 A CN 106158973A
- Authority
- CN
- China
- Prior art keywords
- doped region
- type
- region
- trench
- heavily doped
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
- H10D30/66—Vertical DMOS [VDMOS] FETs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
- H10D30/66—Vertical DMOS [VDMOS] FETs
- H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
- H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
- H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
- H10D62/112—Constructional design considerations for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layers, e.g. by using channel stoppers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
技术领域technical field
本发明涉及功率半导体器件技术领域,具体涉及到一种积累型DMOS(双扩散金属氧化物半导体场效应晶体管)。The invention relates to the technical field of power semiconductor devices, in particular to an accumulation type DMOS (double diffused metal oxide semiconductor field effect transistor).
背景技术Background technique
功率MOS器件的发展是在MOS器件自身优点的基础上,努力提高耐压和降低损耗的过程。The development of power MOS devices is based on the advantages of MOS devices, and strives to improve withstand voltage and reduce losses.
VDMOS兼有双极晶体管和普通MOS器件的优点。与双极晶体管相比,它的开关速度快,开关损耗小;输入阻抗高,驱动功率小;频率特性好;跨导高度线性。特别值得指明出的是,大电流时它具有负的温度系数,没有双极功率器件的二次击穿问题,安全工作区大。但是对于VDMOSFET结构而言,由于其内部JFET区的存在,使VDMOS的导通电阻较大。TRENCHMOSFET结构上采用U型沟槽结构,导电沟道为纵向沟道,消除了JFET区电阻,所以其导通电阻更小。VDMOS has the advantages of both bipolar transistors and ordinary MOS devices. Compared with bipolar transistors, its switching speed is fast, switching loss is small; input impedance is high, driving power is small; frequency characteristics are good; transconductance is highly linear. It is particularly worth pointing out that it has a negative temperature coefficient when the current is high, there is no secondary breakdown problem of bipolar power devices, and the safe working area is large. But for the VDMOSFET structure, due to the existence of its internal JFET region, the on-resistance of the VDMOS is relatively large. The structure of TRENCHMOSFET adopts U-shaped groove structure, and the conductive channel is a vertical channel, which eliminates the resistance of the JFET area, so its on-resistance is smaller.
在低压和超低压方向,漏源通态电阻(specific on-resistance)Rds(on)和单位面积栅极电荷Qg是两个重要参数。减小源漏通态电阻有利于降低通态损耗,减小栅极电荷则有利于降低开关损耗。但是,现在很难对两个参数同时进行大幅度的优化,这是因为以现有的工艺,优化其中的任何一个参数必将对另一个参数带来一定不利的影响。为了提高DMOS的性能,国内外提出了Trench底部厚SiO2结构(BOX)和分栅结构(Split-gate)等新型结构。一般情况下,BOX结构的“Miller”电荷比Split-gate的高,但它的栅极电荷比Split-gate的低。但是,由于Split-gate结构可利用其第一层多晶层(Shield)作为“体内场板”来降低漂移区的电场,所以Split-gate结构通常具有更低的导通电阻和更高的击穿电压,并可用于较高电压(20V-250V)的TRENCH MOS产品。In the direction of low voltage and ultra-low voltage, drain-source on-state resistance (specific on-resistance) Rds(on) and gate charge per unit area Qg are two important parameters. Reducing the on-state resistance of the source and drain is conducive to reducing the on-state loss, and reducing the gate charge is conducive to reducing the switching loss. However, it is difficult to optimize the two parameters at the same time at the same time, because with the existing technology, optimizing any one of the parameters will inevitably have a certain adverse effect on the other parameter. In order to improve the performance of DMOS, new structures such as trench bottom thick SiO2 structure (BOX) and split gate structure (Split-gate) have been proposed at home and abroad. In general, the "Miller" charge of the BOX structure is higher than that of the Split-gate, but its gate charge is lower than that of the Split-gate. However, since the Split-gate structure can use its first polycrystalline layer (Shield) as an "in-body field plate" to reduce the electric field in the drift region, the Split-gate structure usually has lower on-resistance and higher strike Breakthrough voltage, and can be used for TRENCH MOS products with higher voltage (20V-250V).
虽然国内外公司在优化导通电阻和栅电荷方面取得了较大的进展,但是近年来,激烈的市场竞争对器件的性能要求越来越高,所以如何采用先进的MOSFET结构设计同时降低器件Rds(on)及Qg仍然是各个厂家努力的方向。本发明提出的结构可以进一步改善器件的通态损耗和开关损耗。Although companies at home and abroad have made great progress in optimizing on-resistance and gate charge, in recent years, fierce market competition has placed higher and higher requirements on device performance, so how to adopt advanced MOSFET structure design while reducing device Rds (on) and Qg are still the direction of efforts of various manufacturers. The structure proposed by the invention can further improve the on-state loss and switching loss of the device.
发明内容Contents of the invention
本发明的目的是提供一种槽型电荷平衡的积累型DMOS,在槽型电荷平衡的DMOS中引入积累型区域,使得DMOS的阈值电压较低、导通电阻较小且栅漏电容较小。The object of the present invention is to provide a slot-type charge-balanced accumulation DMOS, and the accumulation-type region is introduced into the slot-type charge-balanced DMOS, so that the threshold voltage of the DMOS is lower, the on-resistance is smaller, and the gate-to-drain capacitance is smaller.
本发明所采用的技术方案:一种积累型DMOS,包括从下至上依次层叠设置的金属化漏极1、N+衬底2、N-漂移区3和金属化源极11;所述N-漂移区3上层具有N-型轻掺杂区8和P型掺杂区9,所述N-型轻掺杂区8位于P型掺杂区9之间;所述N-型轻掺杂区8正上方具有N+重掺杂区7,所述P型掺杂区9正上方具有P+重掺杂区10;所述N+重掺杂区7和P+重掺杂区10的上表面与金属化源极11接触;还包括第一沟槽和第二沟槽;所述第一沟槽沿N+重掺杂区7上表面中部垂直向下依次贯穿N+重掺杂区7和N-型轻掺杂区8后延伸入N-漂移区3中;所述第二沟槽沿P+重掺杂区10上表面垂直向下依次贯穿N+重掺杂区7和N-型轻掺杂区8后延伸入N-漂移区3中;所述第一沟槽和第二沟槽中填充有氧化层5,所述第一沟槽中具有栅电极4,所述第二沟槽中具有场板6,所述场板6的上表面与金属化源极11接触。The technical solution adopted in the present invention: an accumulation type DMOS, including a metallized drain 1, an N+ substrate 2, an N-drift region 3, and a metallized source 11 stacked sequentially from bottom to top; the N-drift The upper layer of the region 3 has an N-type lightly doped region 8 and a P-type doped region 9, and the N-type lightly doped region 8 is located between the P-type doped regions 9; the N-type lightly doped region 8 There is an N+ heavily doped region 7 directly above, and a P+ heavily doped region 10 directly above the P-type doped region 9; Pole 11 contacts; also includes a first trench and a second trench; the first trench runs through the N+ heavily doped region 7 and the N-type lightly doped region vertically downward along the middle of the upper surface of the N+ heavily doped region 7 The region 8 then extends into the N-drift region 3; the second trench runs through the N+ heavily doped region 7 and the N-type lightly doped region 8 vertically downward along the upper surface of the P+ heavily doped region 10, and then extends into In the N-drift region 3; the first trench and the second trench are filled with an oxide layer 5, the first trench has a gate electrode 4, and the second trench has a field plate 6, so The upper surface of the field plate 6 is in contact with the metallized source 11 .
进一步的,所述氧化层5为二氧化硅或者二氧化硅和氮化硅的复合材料。Further, the oxide layer 5 is silicon dioxide or a composite material of silicon dioxide and silicon nitride.
进一步的,所述栅电极4的材料为多晶硅。Further, the material of the gate electrode 4 is polysilicon.
进一步的,所述场板6的材料为多晶硅或者金属。Further, the material of the field plate 6 is polysilicon or metal.
本发明的有益效果为,本发明所提供的槽型电荷平衡的积累型DMOS,具有较大的正向电流、阈值电压较小、导通电阻降低、栅漏电流改善以及较小的栅漏电容等优良特性。The beneficial effect of the present invention is that the accumulation type DMOS with slot-type charge balance provided by the present invention has larger forward current, lower threshold voltage, reduced on-resistance, improved gate-leakage current and smaller gate-drain capacitance and other excellent characteristics.
附图说明Description of drawings
图1是本发明的积累型DMOS的剖面结构示意图;Fig. 1 is the sectional structure schematic diagram of accumulation type DMOS of the present invention;
图2是本发明的积累型DMOS在外加零电压时,耗尽线示意图;Fig. 2 is the accumulation type DMOS of the present invention when zero voltage is applied, the schematic diagram of the depletion line;
图3是本发明的积累型DMOS外加电压到达阈值电压时的电流路径示意图;3 is a schematic view of the current path when the accumulated DMOS applied voltage of the present invention reaches the threshold voltage;
图4图13是本发明的积累型DMOS的一种制造工艺流程的示意图;Fig. 4 Fig. 13 is the schematic diagram of a kind of manufacturing process flow of accumulation type DMOS of the present invention;
图14至图23是本发明的积累型DMOS的另一种制造工艺流程的示意图。14 to 23 are schematic diagrams of another manufacturing process of the accumulation-type DMOS of the present invention.
具体实施方式detailed description
下面结合附图,详细描述本发明的技术方案:Below in conjunction with accompanying drawing, describe technical scheme of the present invention in detail:
如图1所示,本发明的一种积累型DMOS,包括从下至上依次层叠设置的金属化漏极1、N+衬底2、N-漂移区3和金属化源极11;所述N-漂移区3上层具有N-型轻掺杂区8和P型掺杂区9,所述N-型轻掺杂区8位于P型掺杂区9之间;所述N-型轻掺杂区8正上方具有N+重掺杂区7,所述P型掺杂区9正上方具有P+重掺杂区10;所述N+重掺杂区7和P+重掺杂区10的上表面与金属化源极11接触;其特征在于,还包括第一沟槽和第二沟槽;所述第一沟槽沿N+重掺杂区7上表面中部垂直向下依次贯穿N+重掺杂区7和N-型轻掺杂区8后延伸入N-漂移区3中;所述第二沟槽沿P+重掺杂区10上表面垂直向下依次贯穿N+重掺杂区7和N-型轻掺杂区8后延伸入N-漂移区3中;所述第一沟槽和第二沟槽中填充有氧化层5,所述第一沟槽中具有栅电极4,所述第二沟槽中具有场板6,所述场板6的上表面与金属化源极11接触。As shown in Figure 1, an accumulation type DMOS of the present invention includes a metallized drain 1, an N+ substrate 2, an N-drift region 3, and a metallized source 11 stacked sequentially from bottom to top; the N- The upper layer of the drift region 3 has an N-type lightly doped region 8 and a P-type doped region 9, and the N-type lightly doped region 8 is located between the P-type doped regions 9; the N-type lightly doped region There is an N+ heavily doped region 7 directly above the 8, and a P+ heavily doped region 10 directly above the P-type doped region 9; the upper surfaces of the N+ heavily doped region 7 and the P+ heavily doped region 10 are connected The source electrode 11 is contacted; it is characterized in that it also includes a first groove and a second groove; the first groove runs through the N+ heavily doped region 7 and N The --type lightly doped region 8 then extends into the N-drift region 3; the second trench runs through the N+ heavily doped region 7 and the N-type lightly doped region vertically downward along the upper surface of the P+ heavily doped region 10 The region 8 then extends into the N-drift region 3; the first trench and the second trench are filled with an oxide layer 5, the first trench has a gate electrode 4, and the second trench has a The field plate 6 , the upper surface of the field plate 6 is in contact with the metallized source 11 .
本发明的工作原理为:Working principle of the present invention is:
(1)器件的正向导通(1) Forward conduction of the device
本发明所提供的槽型电荷平衡的积累型DMOS,其正向导通时的电极连接方式为:槽型栅电极4接正电位,金属化漏极1接正电位,金属化源极11接零电位。当槽型栅电极4为零电压或所加正电压非常小时,由于P型掺杂区9的掺杂浓度大于N-型轻掺杂区8的掺杂浓度,P型掺杂区9和N-型轻掺杂区8所构成的PN结的内建电势会使得P型掺杂区9和栅氧化层5之间的N-型轻掺杂区8耗尽,电子通道被阻断,如图2所示,此时积累型DMOS仍处于关闭状态。The accumulation type DMOS of slot-type charge balance provided by the present invention, the electrode connection mode during its forward conduction is: the slot-type gate electrode 4 is connected to a positive potential, the metallized drain electrode 1 is connected to a positive potential, and the metallized source electrode 11 is connected to zero potential. When the slot-type gate electrode 4 is zero voltage or the applied positive voltage is very small, since the doping concentration of the P-type doped region 9 is greater than the doping concentration of the N-type lightly doped region 8, the P-type doped region 9 and the N The built-in potential of the PN junction formed by the --type lightly doped region 8 will deplete the N-type lightly doped region 8 between the P-type doped region 9 and the gate oxide layer 5, and the electron channel is blocked, such as As shown in Figure 2, the accumulation DMOS is still off at this time.
随着槽型栅电极4所加正电压的增加,P型掺杂区9和N-型轻掺杂区8所构成的PN结的内建势垒区逐渐缩小。由于N-型轻掺杂区8的存在,器件更容易开启,从而降低了阈值电压。当槽型栅电极4所加正电压等于或大于开启电压之后,由于栅氧化层5侧面处的N-型轻掺杂区8内产生多子电子的积累层,这为多子电流的流动提供了一条低阻通路,导通电阻从而得到降低,如图3所示,此时积累型DMOS导通,多子电子在金属化漏极1正电位的作用下从N+重掺杂区7流向金属化漏极1。另外,由于槽型栅电极4底部的栅氧化层5采取厚氧工艺,所以栅漏电容Cgd得到较大的改善。As the positive voltage applied to the grooved gate electrode 4 increases, the built-in potential barrier region of the PN junction formed by the P-type doped region 9 and the N-type lightly doped region 8 gradually shrinks. Due to the existence of the N-type lightly doped region 8, the device is easier to turn on, thereby reducing the threshold voltage. After the positive voltage applied to the groove-shaped gate electrode 4 is equal to or greater than the turn-on voltage, a multi-sub-electron accumulation layer is generated in the N-type lightly doped region 8 at the side of the gate oxide layer 5, which provides a multi-sub-current flow. A low-resistance path is established, and the on-resistance is reduced. As shown in Figure 3, the accumulation DMOS is turned on at this time, and the multi-sub-electrons flow from the N+ heavily doped region 7 to the metal under the action of the positive potential of the metallized drain 1. de-drain 1. In addition, since the gate oxide layer 5 at the bottom of the grooved gate electrode 4 adopts a thick oxygen process, the gate-to-drain capacitance Cgd is greatly improved.
(2)器件的反向阻断(2) Reverse blocking of the device
本发明所提供的槽型电荷平衡的积累型DMOS,其反向阻断时的电极连接方式为:槽型栅电极4和金属化源极11短接且接零电位,金属化漏极1接正电位。The accumulation type DMOS of groove type electric charge balance that the present invention provides, the electrode connection mode when its reverse blocking is: groove type gate electrode 4 and metallized source electrode 11 are shorted and connected to zero potential, and metallized drain electrode 1 is connected to positive potential.
由于零偏压时P型掺杂区9和栅氧化层5之间的N-型轻掺杂区8已经被完全耗尽,多子电子的导电通路被夹断。增大反向电压时,由于体内场板6的存在,体内场板6和N-漂移区3构成横向电场,体内场板6和栅氧化层5之间的N-漂移区3首先耗尽,承受反向电压。继续增大反向电压时,耗尽层边界将向靠近金属化漏极1一侧的N-漂移区3扩展以承受反向电压。与普通的槽型DMOS相比,在N-漂移区3掺杂浓度相同的情况下,由于体内场板6的存在,N-漂移区3内可以实现电荷平衡,形成横向电场,在击穿电压相同时,槽型电荷平衡的积累型DMOS的导通电阻更小,且栅漏电流更小。Since the N-type lightly doped region 8 between the P-type doped region 9 and the gate oxide layer 5 has been completely depleted at zero bias, the conduction path of many electrons is pinched off. When the reverse voltage is increased, due to the existence of the internal field plate 6, the internal field plate 6 and the N-drift region 3 form a transverse electric field, and the N-drift region 3 between the internal field plate 6 and the gate oxide layer 5 is depleted first, withstand reverse voltage. When the reverse voltage continues to increase, the boundary of the depletion layer will expand to the N-drift region 3 on the side close to the metallized drain 1 to withstand the reverse voltage. Compared with ordinary trench DMOS, in the case of the same doping concentration in the N-drift region 3, due to the existence of the internal field plate 6, the charge balance in the N-drift region 3 can be achieved, forming a lateral electric field, and the breakdown voltage At the same time, the on-resistance of the accumulation DMOS with slot-type charge balance is smaller, and the gate leakage current is smaller.
本发明的积累型DMOS的一种制造工艺流程如下:A kind of manufacturing process flow of accumulation type DMOS of the present invention is as follows:
1、单晶硅准备及外延生长。如图4,采用N型重掺杂单晶硅衬底2,晶向为<100>。采用气相外延VPE等方法生长一定厚度和掺杂浓度的N-漂移区3。1. Single crystal silicon preparation and epitaxial growth. As shown in FIG. 4 , an N-type heavily doped single crystal silicon substrate 2 is used, and the crystal orientation is <100>. The N-drift region 3 with a certain thickness and doping concentration is grown by methods such as vapor phase epitaxy (VPE).
2、离子注入。如图5,利用光刻板进行P型柱区硼注入,形成P型掺杂区9,进行N型柱区磷注入,此处磷的注入剂量应较低,形成N型轻掺杂区8。2. Ion implantation. As shown in FIG. 5 , boron implantation is performed in the P-type column region using a photolithography plate to form a P-type doped region 9 , and phosphorus implantation is performed in the N-type column region. The phosphorus implantation dose here should be relatively low to form an N-type lightly doped region 8 .
3、刻槽。如图6,淀积硬掩膜(如氮化硅),利用光刻板刻蚀硬掩膜,进行深槽刻蚀,刻蚀出槽栅区和体内场板区,具体刻蚀工艺可以使用反应离子刻蚀或等离子刻蚀。3. Groove. As shown in Figure 6, deposit a hard mask (such as silicon nitride), use a photolithography plate to etch the hard mask, perform deep groove etching, and etch out the groove gate region and the internal field plate region. The specific etching process can use reaction Ion etching or plasma etching.
4、二氧化硅的填充。如图7,用二氧化硅填充槽栅区和体内场板区。4. Silica filling. As shown in Figure 7, the trench gate region and the body field plate region are filled with silicon dioxide.
5、体内场板中二氧化硅的刻蚀。如图8,利用光刻板先对体内场板区中的二氧化硅进行刻蚀。5. Etching of silicon dioxide in the field plate in the body. As shown in FIG. 8 , the silicon dioxide in the field plate region of the body is firstly etched using a photolithography plate.
6、二氧化硅的刻蚀。如图9,移去光刻板,对槽栅区和体内场板区中的二氧化硅同时进行刻蚀,去掉硬掩膜,此时槽栅区中仍留有较厚的二氧化硅5。6. Etching of silicon dioxide. As shown in Figure 9, remove the photoresist plate, etch the silicon dioxide in the trench gate area and the field plate area in the body at the same time, and remove the hard mask. At this time, there is still thicker silicon dioxide 5 in the trench gate area.
7、氧化层热生长。如图10,对槽栅区和体内场板区侧壁进行氧化层热生长,其中槽栅区形成侧壁栅氧化层5。7. Thermal growth of oxide layer. As shown in FIG. 10 , oxide layer thermal growth is performed on the sidewalls of the trench gate region and the internal field plate region, wherein the sidewall gate oxide layer 5 is formed in the trench gate region.
8、多晶硅的淀积与刻蚀。如图11,淀积多晶硅,多晶硅的厚度要保证能够填满槽型区域。利用光刻板对槽栅区的多晶硅刻蚀,并槽栅区上方淀积二氧化硅,并刻蚀表面二氧化硅。8. Deposition and etching of polysilicon. As shown in Figure 11, polysilicon is deposited, and the thickness of the polysilicon must be guaranteed to fill the groove area. Etching the polysilicon in the groove gate region by using a photolithography plate, depositing silicon dioxide on the groove gate region, and etching the silicon dioxide on the surface.
9、离子注入。如图12,P型重掺杂区硼注入,形成P+重掺杂区10,N型重掺杂区砷注入,形成N+重掺杂区7。9. Ion implantation. As shown in FIG. 12 , boron is implanted in the P-type heavily doped region to form the P+ heavily doped region 10 , and arsenic is implanted in the N-type heavily doped region to form the N+ heavily doped region 7 .
10、金属化。如图13,正面金属化,金属刻蚀,背面金属化,钝化等等。10. Metallization. As shown in Figure 13, front metallization, metal etching, back metallization, passivation and so on.
本发明的积累型DMOS的另一种制造工艺流程如下:Another manufacturing process flow of accumulation type DMOS of the present invention is as follows:
1、单晶硅准备及外延生长。如图14,采用N型重掺杂单晶硅衬底2,晶向为<100>。采用气相外延VPE等方法生长一定厚度和掺杂浓度的N-漂移区3。1. Single crystal silicon preparation and epitaxial growth. As shown in FIG. 14 , an N-type heavily doped single crystal silicon substrate 2 is used, and the crystal orientation is <100>. The N-drift region 3 with a certain thickness and doping concentration is grown by methods such as vapor phase epitaxy (VPE).
2、刻槽。如图15,淀积硬掩膜(如氮化硅),利用光刻板刻蚀硬掩膜,进行深槽刻蚀,刻蚀出槽栅区和体内场板区,具体刻蚀工艺可以使用反应离子刻蚀或等离子刻蚀。2. Groove. As shown in Figure 15, deposit a hard mask (such as silicon nitride), use a photolithography plate to etch the hard mask, perform deep groove etching, and etch out the groove gate region and the internal field plate region. The specific etching process can use the reaction Ion etching or plasma etching.
3、二氧化硅的填充。如图16用二氧化硅填充槽栅区和体内场板区。3. Silica filling. As shown in Figure 16, silicon dioxide is used to fill the trench gate region and the body field plate region.
4、体内场板中二氧化硅的刻蚀。如图17,利用光刻板先对体内场板区中的二氧化硅进行刻蚀。4. Etching of silicon dioxide in the field plate in the body. As shown in FIG. 17 , the silicon dioxide in the field plate region of the body is firstly etched using a photolithography plate.
5、二氧化硅的刻蚀。如图,18,移去光刻板,对槽栅区和体内场板区中的二氧化硅同时进行刻蚀,去掉硬掩膜,此时槽栅区中仍留有较厚的二氧化硅5。5. Etching of silicon dioxide. As shown in Figure 18, remove the photoresist plate, etch the silicon dioxide in the trench gate area and the field plate area in the body at the same time, and remove the hard mask. At this time, there is still thicker silicon dioxide in the trench gate area 5 .
6、氧化层热生长。如图19,对槽栅区和体内场板区侧壁进行氧化层热生长,其中槽栅区形成侧壁栅氧化层5。6. Thermal growth of oxide layer. As shown in FIG. 19 , thermal growth of the oxide layer is performed on the sidewalls of the trench gate region and the internal field plate region, wherein the sidewall gate oxide layer 5 is formed in the trench gate region.
7、多晶硅的淀积与刻蚀。如图20,淀积多晶硅,多晶硅的厚度要保证能够填满槽型区域。利用光刻板对槽栅区的多晶硅刻蚀,并槽栅区上方淀积二氧化硅,并刻蚀表面二氧化硅。7. Deposition and etching of polysilicon. As shown in Figure 20, polysilicon is deposited, and the thickness of the polysilicon must be guaranteed to fill the groove area. Etching the polysilicon in the groove gate region by using a photolithography plate, depositing silicon dioxide on the groove gate region, and etching the silicon dioxide on the surface.
8、扩散掺杂。如图21,利用光刻板进行P型柱区扩散掺杂,形成P型掺杂区9,进行N型柱区扩散掺杂,此处磷的掺杂剂量应较低,形成N型轻掺杂区8。8. Diffusion doping. As shown in Figure 21, the P-type column region is diffused and doped using a photolithography plate to form a P-type doped region 9, and the N-type column region is diffused and doped. The doping dose of phosphorus here should be low to form an N-type lightly doped District 8.
9、离子注入。如图22,P型重掺杂区硼注入,形成P+重掺杂区10,N型重掺杂区砷注入,形成N+重掺杂区7。9. Ion implantation. As shown in FIG. 22 , the P-type heavily doped region is implanted with boron to form the P+ heavily doped region 10 , and the N-type heavily doped region is implanted with arsenic to form the N+ heavily doped region 7 .
10、金属化。如图23,正面金属化,金属刻蚀,背面金属化,钝化等等。10. Metallization. As shown in Figure 23, front metallization, metal etching, back metallization, passivation and so on.
制作器件时,还可用碳化硅、砷化镓或锗硅等半导体材料替代体硅。When making devices, semiconductor materials such as silicon carbide, gallium arsenide, or silicon germanium can also be used to replace bulk silicon.
采用本发明的一种槽型电荷平衡的积累型DMOS,具有较大的正向电流、阈值电压较小、导通电阻降低、栅漏电流改善以及较小的栅漏电容等优良特性。The accumulative DMOS with slot-type charge balance of the present invention has excellent characteristics such as large forward current, low threshold voltage, reduced on-resistance, improved gate leakage current, and small gate-to-drain capacitance.
Claims (4)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201610532247.7A CN106158973A (en) | 2016-07-06 | 2016-07-06 | A kind of accumulation type DMOS |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201610532247.7A CN106158973A (en) | 2016-07-06 | 2016-07-06 | A kind of accumulation type DMOS |
Publications (1)
Publication Number | Publication Date |
---|---|
CN106158973A true CN106158973A (en) | 2016-11-23 |
Family
ID=58062056
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201610532247.7A Pending CN106158973A (en) | 2016-07-06 | 2016-07-06 | A kind of accumulation type DMOS |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN106158973A (en) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108538912A (en) * | 2018-05-07 | 2018-09-14 | 株洲中车时代电气股份有限公司 | Groove step grid igbt chip |
CN109119476A (en) * | 2018-08-23 | 2019-01-01 | 电子科技大学 | Separate gate VDMOS device and its manufacturing method with internal field plate |
CN110262771A (en) * | 2019-05-09 | 2019-09-20 | 中国科学院微电子研究所 | A kind of fundamental arithmetic circuit and its expanded circuit based on MOS transistor |
CN112071750A (en) * | 2020-09-11 | 2020-12-11 | 中国电子科技集团公司第五十八研究所 | Manufacturing method for reducing trench DMOS gate capacitance |
CN113990932A (en) * | 2021-10-28 | 2022-01-28 | 电子科技大学 | Semiconductor longitudinal device and preparation method |
CN114242779A (en) * | 2022-02-24 | 2022-03-25 | 成都功成半导体有限公司 | A Silicon Carbide Accumulated State MOSFET with Trench |
WO2023109080A1 (en) * | 2021-12-15 | 2023-06-22 | 苏州东微半导体股份有限公司 | Igbt device |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101536164A (en) * | 2006-09-27 | 2009-09-16 | 巨能半导体股份有限公司 | Power MOSFET with recessed field plate |
CN105047721A (en) * | 2015-08-26 | 2015-11-11 | 国网智能电网研究院 | Silicon carbide trench gate power metal-oxide-semiconductor field effect transistors (MOSFETs) device and manufacturing method thereof |
-
2016
- 2016-07-06 CN CN201610532247.7A patent/CN106158973A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101536164A (en) * | 2006-09-27 | 2009-09-16 | 巨能半导体股份有限公司 | Power MOSFET with recessed field plate |
CN105047721A (en) * | 2015-08-26 | 2015-11-11 | 国网智能电网研究院 | Silicon carbide trench gate power metal-oxide-semiconductor field effect transistors (MOSFETs) device and manufacturing method thereof |
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108538912A (en) * | 2018-05-07 | 2018-09-14 | 株洲中车时代电气股份有限公司 | Groove step grid igbt chip |
CN108538912B (en) * | 2018-05-07 | 2021-02-12 | 株洲中车时代半导体有限公司 | Trench step gate IGBT chip |
CN109119476A (en) * | 2018-08-23 | 2019-01-01 | 电子科技大学 | Separate gate VDMOS device and its manufacturing method with internal field plate |
CN110262771A (en) * | 2019-05-09 | 2019-09-20 | 中国科学院微电子研究所 | A kind of fundamental arithmetic circuit and its expanded circuit based on MOS transistor |
CN110262771B (en) * | 2019-05-09 | 2021-07-13 | 中国科学院微电子研究所 | A basic operation circuit based on MOS transistor and its extension circuit |
CN112071750A (en) * | 2020-09-11 | 2020-12-11 | 中国电子科技集团公司第五十八研究所 | Manufacturing method for reducing trench DMOS gate capacitance |
CN112071750B (en) * | 2020-09-11 | 2022-08-02 | 中国电子科技集团公司第五十八研究所 | Manufacturing method for reducing trench DMOS gate capacitance |
CN113990932A (en) * | 2021-10-28 | 2022-01-28 | 电子科技大学 | Semiconductor longitudinal device and preparation method |
WO2023109080A1 (en) * | 2021-12-15 | 2023-06-22 | 苏州东微半导体股份有限公司 | Igbt device |
CN114242779A (en) * | 2022-02-24 | 2022-03-25 | 成都功成半导体有限公司 | A Silicon Carbide Accumulated State MOSFET with Trench |
CN114242779B (en) * | 2022-02-24 | 2022-05-10 | 成都功成半导体有限公司 | Silicon carbide accumulation state MOSFET with groove |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN110148629B (en) | A trench type silicon carbide MOSFET device and preparation method thereof | |
CN104992976B (en) | A kind of VDMOS device and its manufacture method | |
CN106158973A (en) | A kind of accumulation type DMOS | |
CN109920839B (en) | P+ shielding layer potential adjustable silicon carbide MOSFET device and preparation method | |
CN101930999B (en) | Impuritytransistor component having an amorphous channel control layer | |
CN102751195A (en) | Lateral transistor and manufacturing method thereof | |
CN102097480B (en) | N-type super-junction transverse double-diffusion metal oxide semiconductor tube | |
CN106098777A (en) | A kind of splitting bar accumulation type DMOS device | |
CN107644913B (en) | Vertical double-diffusion metal oxide semiconductor field effect transistor with high-K charge compensation | |
CN106298939A (en) | A kind of accumulation type DMOS with complex media Rotating fields | |
CN113224148B (en) | SGT device with silicon nitride barrier layer and preparation method | |
US20230395651A1 (en) | Semiconductor device for reducing switching loss and manufacturing method thereof | |
CN105932051A (en) | Grooved gate MOSFET (Metal Oxide Semiconductor Field-Effect Transistor) device | |
CN111384153A (en) | A kind of SGT device with grounded P-type region and preparation method thereof | |
CN107437566B (en) | Semiconductor longitudinal double-diffusion metal oxide semiconductor field effect transistor with composite dielectric layer wide band gap and manufacturing method thereof | |
CN113838914A (en) | RET IGBT device structure and fabrication method with split gate structure | |
CN107170801B (en) | A kind of shield grid VDMOS device improving avalanche capability | |
CN113594255A (en) | Groove type MOSFET device and preparation method thereof | |
CN109037071A (en) | A kind of preparation method of shield grid power device | |
CN106129116B (en) | A Folded Transverse Double Diffusion Metal Oxide Semiconductor Field Effect Transistor with Variable K Dielectric | |
CN103515443B (en) | A kind of super junction power device and manufacture method thereof | |
CN106057906B (en) | A kind of accumulation type DMOS with p type buried layer | |
CN105957894A (en) | DMOS with composite dielectric layer structure | |
CN107180874A (en) | A kind of deep trouth superjunction DMOS devices of accumulation type | |
CN102097481B (en) | P-type super-junction transverse double-diffusion metal oxide semiconductor tube |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
WD01 | Invention patent application deemed withdrawn after publication | ||
WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20161123 |