CN118508961A - A time-domain assisted analog-to-digital converter resistant to aperture errors - Google Patents

Abstract

The present invention discloses a time-domain auxiliary analog-to-digital converter resistant to aperture error, which relates to the technical field of analog-to-digital converters, and includes a ring-shaped time-to-digital converter, a cross-voltage detector, two logic synthesis modules, and a switch capacitor array; the switch capacitor arrays are all connected to the ring-shaped time-to-digital converter, the cross-voltage detector, and the logic synthesis module, and the output end of the cross-voltage detector is connected to the input end of the two logic synthesis modules; the logic synthesis module is used to continuously adjust the switch state of the switch capacitor array to change the input of the cross-voltage detector, and the logic synthesis module continuously records the state of the ring-shaped time-to-digital converter, and converts the obtained output of the ring-shaped time-to-digital converter into a digital code. The present invention greatly reduces the hardware cost of the time-domain auxiliary analog-to-digital converter, and solves the aperture error problem of resolution misalignment.

Description

A time-domain assisted analog-to-digital converter resistant to aperture errors

Technical Field

The present invention relates to the technical field of analog-to-digital converters, and in particular to a time-domain auxiliary analog-to-digital converter capable of resisting aperture errors.

Background Art

Compared with other types of analog-to-digital converters, the successive approximate register analog-to-digital converter (SAR ADC) has the characteristics of low power consumption, simple structure, and high adaptability to CMOS process progress, so it has attracted widespread attention. However, with the iteration of communication technology, the data throughput rate requirements continue to increase, and the speed defect of SAR ADC has gradually emerged. If the traditional SAR ADC is not improved in terms of architecture, its comparator module and capacitor array CDAC module will consume more and more area and energy, which weakens the original advantages of SAR ADC. In recent years, there have been many technical means to improve the performance of SAR ADC at high resolution and high speed, among which time domain auxiliary technology has been adopted by many researchers.

The principle of time-domain assisted technology is to transfer the last few comparisons of the traditional SAR ADC to the time domain instead of continuing in the voltage domain. Compared with the traditional SAR ADC that performs all quantization processes in the voltage domain, the time-domain assisted technology can greatly relieve the pressure on the comparator in the SAR ADC, and the quantization in the time domain can be realized by digital circuits, which is in line with the development of CMOS technology. In the existing time-domain assisted SAR ADC technical solutions, the time domain conversion part mostly adopts the form of voltage-time converter (VTC) combined with time-to-digital converter (VTC). Among them, the time-to-digital converter mostly adopts a single-line or two-dimensional vernier structure. The required hardware increases exponentially with the resolution, and there is a serious problem of time-domain-voltage domain resolution alignment, that is, the aperture error problem.

Summary of the invention

The present invention provides an aperture error-resistant time-domain assisted analog-to-digital converter, which aims to solve the voltage domain-time domain alignment problem (aperture error problem) of the time-domain assisted SAR ADC in the prior art and reduce the hardware cost.

To achieve the above object, the present invention provides the following technical solutions:

A time-domain auxiliary analog-to-digital converter resistant to aperture errors, comprising a ring time-to-digital converter, a cross-voltage detector, two logic synthesis modules and a switched capacitor array;

The switch capacitor arrays are connected to the ring time-to-digital converter, the cross-voltage detector, and the logic synthesis module, and the output end of the cross-voltage detector is connected to the input ends of the two logic synthesis modules;

The logic synthesis module is used to continuously adjust the switch state of the switch capacitor array to change the input of the cross-voltage detector. The logic synthesis module continuously records the state of the ring time-to-digital converter and converts the obtained output of the ring time-to-digital converter into a digital code.

Preferably, the annular time-to-digital converter is a delay chain composed of multiple delay units with the same structure connected end to end to form a circle, each of the delay units delays an input pulse for a fixed time without changing the waveform and phase, and is used multiple times in the quantization process.

Preferably, the delay unit is a drive enhancement structure composed of two stages of inverters connected in series, and a delay capacitor is provided between the two stages of inverters. The value of the delay capacitor determines the actual delay time of the delay unit.

Preferably, the cross-voltage detector is composed of two differential active load amplifier stages with identical and symmetrical structures, each differential active load amplifier stage is connected to an enable signal and a bias source, and the enable signals connecting the two differential active load amplifier stages are mutually inverted.

Preferably, the logic synthesis module includes a decoder and a plurality of DFF triggers connected in series, and the output signal of the DFF trigger is input into the decoder as a part of the digital code and controls the level connection of the lower plate of the switch capacitor array.

Preferably, the switch capacitor array is composed of a capacitor array P and a capacitor array N with the same structure, the capacitor upper plate of the switch capacitor array is connected to the input terminal of the cross-voltage detector, and the capacitor lower plate is connected to the reference voltage.

Compared with the prior art, the present invention has the following beneficial effects:

The present invention greatly reduces the hardware cost of the time-domain auxiliary analog-to-digital converter and solves the aperture error problem of resolution misalignment.

BRIEF DESCRIPTION OF THE DRAWINGS

Fig. 1 is a schematic diagram of the overall structure of the present invention;

FIG2 is a simplified framework diagram and timing diagram of a ring-shaped time-to-digital converter according to an embodiment of the present invention;

FIG3 is a topological diagram of a delay unit according to an embodiment of the present invention;

FIG4 is a schematic diagram of the working process of the ring-shaped time-to-digital converter according to an embodiment of the present invention;

FIG5 is a topological diagram of a cross-voltage detector according to an embodiment of the present invention;

6 is a schematic diagram of the effect of the cut-off frequency of the cross-voltage detector on the nonlinearity simulation according to an embodiment of the present invention;

7 is a schematic diagram of the structure of the key circuit of the logic synthesis module according to an embodiment of the present invention;

FIG. 8 is a topological diagram of a switched capacitor array according to an embodiment of the present invention.

DETAILED DESCRIPTION

The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments; based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

As shown in FIG1 , a time-domain assisted analog-to-digital converter resistant to aperture error includes a ring time-to-digital converter, a cross-voltage detector, two logic synthesis modules, and a switched capacitor array;

The complete quantization process of the present invention is divided into a sampling phase and a conversion phase;

During the sampling phase, the input signal is connected to the switched capacitor array through switches.

In the conversion phase, the switch at the input signal is disconnected, and the voltage on the upper plate of the switch capacitor array is the input signal voltage value at the moment of disconnection. Then the ring time-to-digital converter starts to work, and the switch state of the switch capacitor array is continuously adjusted through the logic synthesis module to change the input of the cross-voltage detector. The logic synthesis module will continuously record the state of the ring time-to-digital converter (record the pulse appears on the output node of the delay unit) and use it as the output of the quantization process. The output of each delay unit in the ring delay chain is low at the beginning. When the timing starts, a fixed pulse will be input to the first delay unit, and then propagate along the 16 delay units in sequence. This fixed pulse will appear at the output nodes of the 16 delay units in sequence. When the entire quantization process is completed, the logic synthesis module will convert the obtained output of the ring time-to-digital converter into a digital code, and reset the entire circuit to wait for the next quantization.

The ring time-to-digital converter is a delay chain consisting of 16 delay units D1-D16 connected end to end in a circle. Each delay unit delays an input pulse for a fixed time without changing the waveform and phase. The space between two delay units is defined as a node, and the entire delay chain has a total of 16 nodes p1-p16.

When the start signal is input to D1, the signal needs to be transmitted 4 times around the delay chain. The output waveform of each delay unit is combined to form the waveform shown in the middle part of Figure 2. If the rising edge of each pulse is used as a time scale, then 16 delay units can obtain T1 to T64 time scales, which is a 6-bit resolution in binary. Each delay unit is used multiple times in the quantization process, instead of being used only once as in the prior art solution. Compared with the prior art, the present invention greatly reduces the number of delay units, which means that the mismatch problem between delay units caused by process deviations is well optimized, and the hardware cost is greatly reduced.

As shown in Figure 3, each of the delay units has the same structure, and is composed of two stages of inverters connected in series to form a drive enhancement structure, which increases the driving capability while ensuring that the phase of the signal remains unchanged, and a delay capacitor is provided between the two stages of inverters connected in series. The first stage inverter is connected to the input signal, and the second stage inverter outputs the signal and serves as the input of the next delay unit. The value of the delay capacitor will determine the actual delay time. The larger the delay capacitor value, the longer the delay time. When the input signal changes, the delay capacitor and the first stage inverter form an RC charge and discharge structure as the main delay control.

As shown in FIG8 , the switch capacitor array is composed of a fully differential capacitor array P and a capacitor array N with the same structure. The capacitor array P includes capacitors Cp1, Cp2, Cp3, and Cp4 connected in parallel; the capacitor array N includes capacitors Cn1, Cn2, Cn3, and Cn4 connected in parallel.

The end of the switch capacitor array connected to the voltage detector is the upper plate of the capacitor, and the lower plate of the capacitor is connected to the reference voltage A or the reference voltage B, and the reference voltage A and the reference voltage B are VDD or GND.

During the switching phase, the upper plate of the capacitor in the switched capacitor array is in a high impedance state, so the charge is conserved, and the level change of the lower plate will cause the level change of the upper plate. These level changes are controlled by the delay chain of the ring time-to-digital converter through the logic synthesis module. The reference voltage connection and switching of capacitor array P and capacitor array N are exactly opposite.

At the beginning of the sampling phase and conversion phase of the ADC, the lower plates of the capacitor array P are all connected to the reference voltage A, and the lower plates of the capacitor array N are all connected to the reference voltage B. After the signal is transmitted along the delay chain of the annular time-to-digital converter, the lower plate of the capacitor Cp1 is changed to the reference voltage B, and the lower plate of the capacitor Cn1 is changed to the reference voltage A, and the cycle continues until the cross-voltage detector is triggered and the level change of the switch capacitor array is terminated. The switch capacitor array in this embodiment represents a resolution of 2 bits, and the timing diagram is 64 time scales, which can be obtained by multiplying the number of capacitors in the single-sided capacitor array (capacitor array P or capacitor array N) by the number of delay units in the delay chain. In this embodiment, the number of single-sided capacitors is 4×16 (the number of delay units), so in actual engineering, the resolution can be increased by adding the corresponding number of capacitors in the switch capacitor array and the logic control module.

As shown in Figure 7, the logic synthesis module is mainly used to record the signal transmission of the delay chain and convert it into a digital code output to control the lower plate potential of the switch capacitor array. It mainly includes 4 DFF triggers connected in series, a decoder and a switch buffer. The 4 DFF triggers are connected to the lower plate of the switch capacitor array through the switch buffer, and its output signal is converted into a digital code through the decoder.

In the figure, 4 DFF triggers are used to record the number of turns of the delay chain. Each time the last delay unit D16 of the delay chain outputs a rising edge, it means that the signal has passed one turn along the delay chain. The output Q of the DFF trigger will copy the input D and hold it, that is, the output Q maintains the same level as the input D until the next time the delay unit D16 connected to the clock signal CLK outputs another high level. The output signals Q1~Q4 of the 4 DFF triggers will be sent to the decoder as part of the digital code. At the same time, the output signals Q1~Q4 will also control the level connection of the lower plate of the switch capacitor array. The lower right corner of Figure 7 shows the logical connection of a capacitor. Q1_B is the inversion of the output signal Q1. They will be used as selection signals to control the lower plate of the capacitor to be connected to the reference voltage A or B, thereby changing the level of the upper plate of the switch capacitor array. The function of the switch buffer is to be controlled by Q1_B or Q1 to select whether to access the reference voltage and increase the driving capability of the capacitor. The decoder also receives the output signal of each delay unit in the delay chain, ie, the rising edge of the nodes P1 to P16, which will be used as the quantized digital code of the last 4 bits.

As shown in Fig. 5, the cross-voltage detector is mainly composed of two differential active load amplifier stages, which are helpful for gain improvement and save voltage margin at low power supply voltage. The first differential active load amplifier stage is connected with enable signal 1 and bias signal 1, and connected with input + and input -, and the second differential active load amplifier stage is connected with enable signal 2 and bias signal 2 and output node.

The first stage differential active load amplifier stage is an NMOS input pair of transistors M5 and M6, and the load is an active current mirror transistor M2 and M3. Transistor M1 and transistor M4 are switch control tubes, which are connected in parallel with transistor M2 and transistor M3 respectively. Transistor M7 is a current source control tube of the first stage differential active load amplifier stage, which will determine whether the current of the tail current source transistor M8 can provide a DC current for the first stage differential active load amplifier stage. The drain of the first stage differential active load amplifier stage input pair is the output of the first stage differential active load amplifier stage, and also serves as the input of the second stage differential active load amplifier stage.

The structure of the second-stage differential active load amplifier stage is completely symmetrical with that of the first-stage differential active load amplifier stage and has the same function. The types of transistors are just opposite, so the enable signal 1 and the enable signal 2 are just opposite, ensuring that the two-stage differential active load amplifier stages work in the same state at the same time.

The enable signal 1 and the enable signal 2 are inversely phased with each other, and their function is to turn on the transistors M1, M4, M13, and M16 when the cross-voltage detector does not need to work, so that the circuit of the cross-voltage detector cannot work, the output node is locked to prevent misjudgment, and other nodes of the circuit are locked to a high level or a low level to prevent charge leakage; when the cross-voltage detector needs to work, the transistor where the enable signal is located is turned off to allow the circuit to work normally.

In the actual circuit, bias signal 1 and bias signal 2 are bias sources in the form of current mirrors, which can provide bias current for the cross-voltage detector. When the circuit works normally, the differential signal of input + and input - will be amplified by transistors M5 and M6, and the amplified differential signal will be input to transistors M11 and M12 in the second-stage differential active load amplifier stage. The amplified result of the second-stage differential active load amplifier stage will be provided to the logic synthesis module.

The low-pass filtering characteristics of the cross-voltage detector will greatly affect the quantization accuracy of the last delay of the ring time-to-digital converter. If the low-pass filtering effect is not good enough, the last falling edge of the stepped voltage waveform in Figure 4 will not be smooth enough, causing the final 4-bit additional quantization value to be offset. This is a dynamic error, which is related to the input frequency and cannot be eliminated by first-order compensation. Therefore, the 3dB cutoff frequency of the cross-voltage detector is designed to be 1/50 of the switching frequency of the switched capacitor array. Figure 6 shows the simulation results of the cutoff frequency and nonlinearity of the cross-voltage detector. If the cutoff frequency of the cross-voltage detector is too high or too low, it will have an adverse effect on the linearity.

As shown in FIG4 , the input level of the cross-voltage detector is the voltage of the upper plate of the switched capacitor array (only the single-ended one is shown here for the convenience of demonstration). The lower plates of all capacitors in the switched capacitor array are initially connected to the reference voltage A. When the ring time-to-digital converter starts working, every time the signal is transmitted along the ring delay chain, a capacitor lower plate will be changed from reference voltage A to reference voltage B, causing the upper plate of the switched capacitor array to drop a certain voltage value. Since each capacitance value of the switched capacitor array is the same, the voltage value dropped each time is also the same, thus forming a uniform equal step-like drop, which ensures that the gain from the voltage domain to the time domain is fixed, and largely solves the problem of the inability to align the time domain-voltage domain resolution in the prior art solution (i.e., the problem of clock aperture error). When the voltage on the upper plate of the switched capacitor array is lower than the threshold of the cross-voltage detector, it means that the ring delay chain corresponding to this voltage drop is the last circle (the last step of the voltage waveform in FIG4 ).

During the whole process, the logic synthesis module will always record the number of turns N of the delay chain of the ring time-to-digital converter and the number m of delay units that the signal passes through in the last turn, so the total quantization digital code value is 16×N+m, and the total quantization range code value is 0~63, and the final quantization value is Where V _total is the actual voltage value represented by the total quantization range. The switching action of the switch capacitor array is controlled by the ring time-to-digital converter through the logic synthesis module. In addition, the signal position in the last circle of the delay chain will be accompanied by an additional 4-bit quantization value. This additional quantization bit does not require additional capacitance because it is based on detecting the specific delay unit to which the pulse signal is transmitted in the last circle of the delay chain. At the same time, this reduces the area and power consumption of the switch capacitor array. In the present embodiment, a circle of delay chain has a total of 16 delay units, which can represent ²⁴ quantization intervals, so 4 additional quantization bits are attached.

Claims (6)

1. The time domain auxiliary analog-to-digital converter is characterized by comprising a ring-shaped time-to-digital converter, a voltage-across detector, 2 logic synthesis modules and a switched capacitor array;

The switch capacitor array is connected with the annular time-to-digital converter, the voltage-across detector and the logic synthesis modules, and the output end of the voltage-across detector is connected with the input ends of the 2 logic synthesis modules;

the logic synthesis module is used for continuously adjusting the switch state of the switch capacitor array so as to change the input of the voltage-across detector, continuously recording the state of the annular time-to-digital converter and converting the obtained output of the annular time-to-digital converter into a digital code.

2. The aperture error resistant time domain auxiliary analog-to-digital converter of claim 1, wherein said annular time-to-digital converter is a delay chain formed by a plurality of delay units of identical structure connected end-to-end in a loop, each of said delay units delaying an input pulse for a fixed time without changing waveform and phase, and being utilized multiple times during quantization.

3. The aperture error resistant time domain auxiliary analog-to-digital converter of claim 1, wherein the delay unit is a drive enhancement structure formed by two stages of inverters connected in series, and a delay capacitor is arranged between the two stages of inverters.

4. The aperture error resistant time domain auxiliary analog-to-digital converter of claim 1, wherein the cross voltage detector is composed of two differential active load amplifying stages which are identical in structure and symmetrical, each differential active load amplifying stage is connected with an enabling signal and a bias source, and the enabling signals connected with the two differential active load amplifying stages are mutually opposite.

5. The aperture error resistant time domain auxiliary analog-to-digital converter of claim 1, wherein said logic synthesis module comprises a decoder and a plurality of DFF flip-flops in series, the output signal of said DFF flip-flop being input to the decoder as part of a digital code and controlling the level connection of the bottom plate of the switched capacitor array.

6. The time domain auxiliary analog-to-digital converter of claim 2, wherein the switched capacitor array is composed of a capacitor array P and a capacitor array N with the same structure, a capacitor upper plate of the switched capacitor array is connected with an input end of the trans-voltage detector, and a capacitor lower plate is connected with a reference voltage.