CN110474623A - A kind of imbalance self-correcting dynamic comparer for gradual approaching A/D converter - Google Patents

Abstract

The invention discloses an offset self-correcting dynamic comparator for a successive approximation analog-to-digital converter, which enables the dynamic comparator to perform offset correction by improving the dynamic comparator in the traditional successive approximation analog-to-digital converter , the switching of NMOS and PMOS is controlled by the clock signal generated by the output of the comparator, and self-correction is performed according to the principle of charge redistribution, which avoids the static power consumption caused by the introduction of the amplifier to reduce the offset, thereby reducing the power of the comparator consumption. The invention effectively utilizes the principle of charge redistribution, can adjust the capacitance of the correction capacitor and the charge and discharge capacitor to effectively improve the correction accuracy, and compares the correction process of the dynamic comparator with that in the successive approximation analog-to-digital converter system The process is separated to avoid the influence of the system on the offset correction process, which can reduce the offset voltage of the dynamic comparator and improve the accuracy of the dynamic comparator.

Description

An offset self-correcting dynamic comparator for successive approximation analog-to-digital converters

technical field

The invention belongs to the technical field of analog-to-digital conversion, and in particular relates to an offset self-correcting dynamic comparator for successive approximation analog-to-digital converters.

Background technique

In nature, most of the signals generated are macroscopically analog quantities, such as temperature, pressure, sound or touch signals, etc. These signals must eventually be processed in the digital field in many ways, so each system needs an analog Composed of digital converter ADC and digital signal processor DSP. The development of ultra-large-scale integrated circuits has set off a climax in the use of digital processing technology, prompting people to pay attention to the role of interface components between analog and digital systems. Analog-to-digital converters have become a bridge connecting analog signals and digital signals; Today, the analog-to-digital converter is an important part of measuring equipment, various conversion and display information systems, so the analog-to-digital converter is an important module in a system, and its performance directly determines the performance of the electronic information processing system.

There are many types of ADCs, including parallel, successive approximation, integral, pipeline and Σ-Δ ADCs, etc. The speed, accuracy and power consumption of different types of ADCs will be different, so the ADC selected for different systems will also Different; while the successive approximation ADC is mostly used in some low power consumption, medium and high precision systems, as shown in Figure 1, it mainly includes four modules: sample and hold module, comparator module, capacitor array module and successive approximation register module etc.; the working principle of the successive approximation ADC is shown in Figure 1: first, the input analog signal is sent to the comparator after passing through the sample and hold module, and compared with the reference voltage generated by the DAC array, and the successive approximation register is based on the output result of the comparator. Control the capacitor switching of the capacitor array, change the reference level to perform the next comparison, and the final output digital result is the output of the ADC.

In recent years, with the rapid development of integrated circuit technology, the successive approximation ADC has been continuously promoted to the direction of low voltage, low power consumption, high speed, and high precision. As a key module of the successive approximation ADC, the speed and accuracy of the comparator affect The performance of the entire ADC is affected, and the dynamic comparator is often used because it can achieve high speed and does not consume the static power consumption of the system. In order to further improve the performance of the dynamic comparator, it is often required to maintain high-precision performance at high speed, where the offset voltage is directly related to the accuracy of the comparator; the method of reducing the offset in the prior art is to add an amplifier stage before the comparator structure, but adding an amplification stage increases the power consumption of the system and also affects the speed of the comparator.

Contents of the invention

In view of the above, the present invention provides a kind of offset self-calibration dynamic comparator for successive approximation analog-to-digital converters, which can make offset self-correction according to the output result of the comparator each time; the correction clock is determined by the output signal of the dynamic comparator Generate, separate the correction process of the dynamic comparator from the comparison process in the successive approximation analog-to-digital converter system, avoid the influence of the system on the offset correction process, and improve the correction accuracy; use the principle of charge redistribution for correction without consuming static power consumption, reducing system power consumption.

An offset self-correcting dynamic comparator for successive approximation analog-to-digital converters, including a dynamic comparison circuit, an offset correction circuit, and a clock control circuit; wherein:

The clock control circuit is used to generate the following three groups of clock signals:

The clock signal CAL is used to control the offset correction circuit;

The clock signal CALB is used to precharge the correction capacitor in the offset correction circuit so that its voltage reaches the common-mode level;

The clock signal CLK is used for the reset of the dynamic comparison circuit and the control of the comparison stage;

The dynamic comparison circuit is used to compare the two differential input signals inn and inp, and successively generate two differential comparison signals outn and outp under the control of the clock signal CLK;

The offset correction circuit enters the offset correction mode under the control of the clock signals CAL and CALB, charges and discharges the corresponding correction capacitor according to the differential comparison signal, and changes the capacitor voltage by changing the charge size, so as to perform a dynamic comparison circuit offset correction.

Further, the dynamic comparison circuit is composed of a pre-amplification circuit and a positive feedback latch structure and includes thirteen MOS transistors M1-M13, wherein: the source of the MOS transistor M1 is grounded, and the gate of the MOS transistor M1 is connected to the clock signal CLK , the drain of the MOS transistor M1 is connected to the source of the MOS transistor M2 and the source of the MOS transistor M3, the gate of the MOS transistor M2 and the gate of the MOS transistor M3 are respectively connected to the differential input signals inn and inp, and the drain of the MOS transistor M2 The pole is connected to the drain of MOS transistor M4, the gate of MOS transistor M6 and the gate of MOS transistor M12, the drain of MOS transistor M3 is connected to the drain of MOS transistor M5, the gate of MOS transistor M7 and the gate of MOS transistor M13 The gate of the MOS transistor M4 is connected to the gate of the MOS transistor M5 and connected to the clock signal CLK, the source of the MOS transistor M4 is connected to the source of the MOS transistor M5 and connected to the working voltage VDD, the source of the MOS transistor M12 is connected to the The source of the MOS transistor M10 is connected and grounded, the source of the MOS transistor M13 is connected to the source of the MOS transistor M11 and grounded, the drain of the MOS transistor M12 is connected to the drain of the MOS transistor M10, the drain of the MOS transistor M8, and the MOS transistor The gate of M9 is connected to the gate of MOS transistor M11 and outputs a differential comparison signal outn, the drain of MOS transistor M13 is connected to the drain of MOS transistor M11, the drain of MOS transistor M9, the gate of MOS transistor M8 and the gate of MOS transistor M10 The gate of the MOS transistor M8 is connected to the gate and outputs the differential comparison signal outp. The source of the MOS transistor M8 is connected to the drain of the MOS transistor M6. The source of the MOS transistor M9 is connected to the drain of the MOS transistor M7. The source of the MOS transistor M6 is connected to the drain of the MOS transistor M6. The source of M7 is connected and connected to the working voltage VDD.

Further, MOS tubes M1~M5 form a pre-amplification circuit, and MOS tubes M6~M13 form a positive feedback latch structure; wherein, MOS tubes M1~M3 and MOS tubes M10~M13 use NMOS tubes, MOS tubes M4~M5 and MOS tubes M6-M9 adopt PMOS tubes.

Further, the offset correction circuit is composed of two offset correction modules with exactly the same structure, the offset correction module is composed of a pre-charging circuit and a capacitor charging and discharging circuit and includes two inverters INV1 and INV2, a NAND gate, an AND gate, two ordinary capacitors C1 and C2, a correction capacitor, a controllable switch and five MOS transistors M16, M18-M21; where: the first input terminal of the NAND gate is connected to the differential comparison signal outp, and The second input terminal of the NOT gate is connected to the first input terminal of the AND gate and connected to the clock signal CAL, the second input terminal of the AND gate is connected to the differential comparison signal outn, the output terminal of the NAND gate is connected to the gate of the MOS transistor M19 and the inverter The input terminal of the phaser INV1 is connected, the output terminal of the AND gate is connected with the gate of the MOS transistor M20 and the input terminal of the inverter INV2, the output terminal of the inverter INV1 is connected with the gate of the MOS transistor M18, and the inverter INV2 The output terminal of the MOS transistor M21 is connected to the gate, the source of the MOS transistor M18 is connected to the working voltage VDD, the drain of the MOS transistor M18 is connected to one end of the capacitor C1 and the source of the MOS transistor M19, and the other end of the capacitor C1 is grounded. The drain of the MOS transistor M21 is connected to one end of the capacitor C2 and the source of the MOS transistor M20, the other end of the capacitor C2 is connected to the source of the MOS transistor M21 and grounded, and the drain of the MOS transistor M19 is connected to the drain of the MOS transistor M20, One end of the controllable switch, the gate of the MOS transistor M16 and one end of the correction capacitor are connected, the other end of the controllable switch is connected to the common mode level, the control pole of the controllable switch is connected to the clock signal CALB, the other end of the correction capacitor is grounded, and the MOS The drain and source of the tube M16 are respectively used as two output ports O1 and O2 of the offset correction module; the output ports O1 and O2 of one of the offset correction modules are respectively connected to the drain and source of the MOS transistor M2 in the dynamic comparison circuit, The output ports O1 and O2 of another offset correction module are respectively connected to the drain and source of the MOS transistor M3 in the dynamic comparison circuit.

Further, the controllable switch, the correction capacitor and the MOS transistor M16 constitute the pre-charging circuit, and the MOS transistors M18-M21, the inverters INV1 and INV2, the NAND gate, the AND gate, and the ordinary capacitors C1 and C2 constitute the capacitor charging and discharging circuit ; Among them, the MOS tubes M16, M20 and M21 are NMOS tubes, and the MOS tubes M18 and M19 are PMOS tubes.

Further, the clock control circuit includes an offset circuit correction signal generation module, a CLK clock signal generation module and a CALB clock signal generation module, wherein:

The offset circuit correction signal generation module includes an AND gate U1 and a delayer T1, the two input terminals of the AND gate are respectively connected to the inverting signals out+ and out- corresponding to the differential comparison signals outn and outp, and the output terminals of the AND gate Connected to the input terminal of the delay device, the output terminal of the delay device generates a correction signal clk_calib;

The CLK clock signal generation module includes a three-input AND gate U2, a NOR gate, an OR gate, a delayer T2 and an inverter INV3, and the two input terminals of the NOR gate are respectively connected to the current and previous The output value of a comparator, the output value of the comparator is the output Q value after the inversion signal out+ and out- are input to the RS flip-flop, and the output terminal of the OR gate is connected to the input terminal of the inverter INV3, and the inverter The output terminal of INV3 generates the clock signal OFF, and the three input terminals of the AND gate U2 are respectively connected to the correction signal clk_calib, the clock signal OFF and the clock signal CAL, and the output terminal of the AND gate U2 is connected to the first input terminal of the OR gate, and the OR gate The second input terminal is connected to the clock signal clk of the external given comparator, and the output terminal of the OR gate is connected to the input terminal of the delayer T2, and the output terminal of the delayer T2 generates the clock signal CLK;

The CALB clock signal generation module includes a two-stage frequency division clock circuit, the first stage frequency division clock circuit is formed by cascading a plurality of frequency division units, each frequency division unit includes a D flip-flop and an inverter, D The input terminal of the flip-flop is connected to the output terminal of the inverter, the output terminal of the D flip-flop is connected to the input terminal of the inverter and used as the output terminal of the frequency division unit, and the clock terminal of the D flip-flop is used as the input terminal of the frequency division unit , the output terminal of the previous frequency division unit is connected to the input terminal of the latter frequency division unit, and the input terminal of the first frequency division unit is connected to the correction signal clk_calib; the second stage frequency division clock circuit includes multiple cascaded D flip-flops And an inverter INV4, the output terminal of the previous D flip-flop is connected to the input terminal of the next D flip-flop, the input terminal of the first D flip-flop is connected to high level, and the output terminal of the last D flip-flop is connected to the inverted The input terminals of the phaser INV4 are connected, the output terminal of the inverter INV4 generates the clock signal CALB, and the clock terminals of each D flip-flop are connected together and connected to the output terminal of the last frequency division unit in the first stage frequency division clock circuit.

Further, the clock signal CAL is given externally and generated by a clock control circuit, and when it is at a high level, it controls the offset correction circuit to perform correction, and the comparator enters an offset correction mode.

The present invention improves the dynamic comparator in the traditional successive approximation analog-to-digital converter, so that the dynamic comparator can perform offset correction, and controls the switching of NMOS and PMOS through the clock signal generated by the output terminal of the comparator, and according to the current The principle of load distribution is used for self-calibration, which avoids the introduction of amplifiers to reduce static power consumption caused by offsets, thereby reducing the comparator power consumption.

The invention effectively utilizes the principle of charge redistribution, can adjust the capacitance of the correction capacitor and the charge and discharge capacitor to effectively improve the correction accuracy, and compares the correction process of the dynamic comparator with that in the successive approximation analog-to-digital converter system The process is separated to avoid system influence on the offset correction process. The invention can reduce system power consumption, reduce the offset voltage of the dynamic comparator and improve the precision of the dynamic comparator when used in the successive approximation analog-digital converter, and is suitable for the design of the successive approximation analog-digital converter with high speed and high precision.

Description of drawings

FIG. 1 is a schematic structural diagram of a successive approximation analog-to-digital converter system.

FIG. 2 is a structural schematic diagram of the offset self-correcting dynamic comparator of the present invention.

FIG. 3( a ) is a schematic structural diagram of an offset correction circuit in the present invention.

Fig. 3(b) is a schematic diagram of the change waveform of the output value of the offset self-correction dynamic comparator and the plate voltage on the correction capacitor.

FIG. 4 is a schematic structural diagram of a clock control circuit in the present invention.

FIG. 5 is a schematic diagram of the timing of each clock signal in the present invention.

Detailed ways

In order to describe the present invention more specifically, the technical solutions of the present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments.

As shown in Figure 2, the offset self-correcting dynamic comparator used for the successive approximation analog-to-digital converter of the present invention includes: a dynamic comparison circuit, an offset correction circuit, and a clock control circuit; wherein the dynamic comparator circuit is composed of a pre-amplification circuit and a positive feedback Latch structure, the pre-amplification circuit is composed of three NMOS transistors M1~M3 and two PMOS transistors M4~M5, the positive feedback latch structure is composed of four NMOS transistors M10~M13 and four PMOS transistors M6~M9, the input The drain ends of the NMOS transistors M2-M3 are connected to the gate ends of the NMOS transistors M12-M13 and the PMOS transistors M6-M7. The dynamic comparison circuit is used to compare the differential input signals, obtain two differential comparison signals according to the clock signal CLK, and generate comparison signals successively. When CAL is high, the circuit enters offset correction mode; when CAL is low, the circuit enters comparator mode. There are two phases when the dynamic comparator works: reset and comparison phase, when CLK is low level, the dynamic comparator enters the reset phase, when CLK is high level, the dynamic comparator enters the comparison phase; the offset correction circuit enters through the clock control circuit In the offset correction mode, the corresponding correction capacitor is charged and discharged according to the result of the comparison signal, and the voltage is changed by changing the charge size, and n times of comparisons are performed successively until the comparison signal changes. The clock control circuit is used for mode switching of the dynamic comparator, offset correction mode and comparison mode. Including three clock control signals: CAL clock signal, used to control the offset correction circuit; CALB clock signal, used to precharge the correction capacitor of the offset circuit, and charge the correction capacitor to the common mode level; CLK clock signal, used It is controlled during the reset and comparison stages of the comparator circuit.

The offset correction circuit of the present invention is shown in Figure 3(a), which is composed of a pre-charging circuit and a capacitor charging and discharging circuit; wherein the pre-charging circuit is composed of a switch, a correction capacitor Ccal, and two NMOS transistors M16-M17, and the switch Controlled by the CALB clock, the gate terminal voltage X and Y points of the two NMOS transistors M16~M17 are precharged to the common mode level, and the corresponding charge is stored on the correction capacitor Ccal; the capacitor charging and discharging circuit is composed of two PMOS transistors M18 ~M19, two NMOS transistors M20~M21 and logic gates, in which the comparator differential comparison signal outp and the CAL clock signal are connected to the gate terminal of the PMOS transistor M19 after passing through the NAND gate, and at the same time connected to the gate terminal of the PMOS transistor M18 after passing through the NOT gate The gate terminals are connected, and the PMOS transistor M18 realizes charging the upper plate of the capacitor C1 to VDD. The other terminal outn of the comparator differential comparison signal is connected to the gate terminal of the NMOS transistor M20 after passing through the NAND gate, and connected to the gate terminal of the NMOS transistor M21 after passing through the NOT gate. The NMOS transistor M20 realizes the upper pole of the capacitor C1 Board charges to GND. The correction capacitor is charged and discharged by switching off the PMOS transistor M19 and the NMOS transistor M20. When the circuit starts to work, when the comparator enters the reset phase, the outputs of outp and outn are low, causing the PMOS transistor M19 and NMOS transistor M20 to be turned off, and the PMOS transistor M18 and NMOS transistor M21 to be turned on, so that the C1 and C2 capacitors are charged to VDD and VDD respectively. GND stores the corresponding charges on the upper plates of C1 and C2. When the comparator enters the comparison stage, if the comparator has an offset voltage, outp and outn are reversed, making the PMOS transistor M19 or NMOS transistor M20 open, and correspondingly C1 and Ccal , C2 and Ccal charges are redistributed for charge and discharge process, resulting in the change of gate terminal voltage X and Y point voltage of NMOS transistors M16~M17, thus affecting the drain terminal voltage of dynamic comparator input pair transistors NMOS transistors M2~M3, with the dynamic The reset and comparison stages of the comparator are switched continuously, and the capacitor C1 or C2 is continuously charged and discharged until the calibration is completed. As shown in Figure 3(b), in the offset correction, the voltage on the upper plate of the correction capacitor Ccal is charged to the common-mode level at the time t1, and then the NMOS transistors M16, One side of the correction capacitor connected to the gate of M17 is charged, and the other side is discharged until the output result of the self-calibration dynamic comparator starts to flip 1/0 at time t2. At this time, the correction is over, and the voltage value of the plate on the correction capacitor Ccal is at Fluctuates around a fixed offset voltage.

The clock control circuit of the present invention is shown in FIG. 4 , and the clock control circuit includes three clock circuits, a CAL clock signal, a CALB clock signal and a CLK clock signal.

The CAL clock signal is composed of an external clock signal. When CAL is at a high level, the NMOS transistors M2~M3 at the input end of the dynamic comparator are connected to the common mode level, and the self-calibration comparator enters the offset correction mode; when CAL is at a low level , the self-calibrating comparator enters normal compare mode.

The CALB clock signal is used to precharge the correction capacitor of the offset circuit in the offset correction mode, and charge the correction capacitor to the common mode level. It is composed of two-stage frequency division clock; the first stage frequency division clock is composed of D flip-flop and The inverter INV is formed, and the differential output signals outp and outn of the self-correcting dynamic comparator pass through the inverter to obtain the differential signals out+ and out-, and after delaying by the AND gate, the input signal clk_calib of the first-stage frequency division clock is obtained. The clk_calib signal is connected to the clock terminal of the first D flip-flop, and the clock terminals of the remaining D flip-flops are connected to the output of the previous D flip-flop, and the output of the first stage is obtained after n D flip-flops and inverters Signal; the output signal of the first stage is connected to the clock terminals of all D flip-flops of the second-stage frequency division clock, and the output end of the last D flip-flop passes through the inverter INV to obtain the pre-charge clock CALB of the offset correction circuit.

The CLK clock signal is used to control the comparator circuit reset and comparison phase. When the self-calibration circuit is working, the clock signal is generated by the internal signal, and the differential signals out+, out- form the correction time of the offset correction circuit clk_calib after passing through the AND gate and delay, the output value Q of the self-calibration comparator and the previous output After the value Q* is NORed, the correction end signal OFF is obtained. The clk_calib signal, the OFF signal and the CAL clock signal are connected to one end of the OR gate after the AND gate, and the other end is connected to the comparator signal clk in the successive approximation analog-to-digital converter. , get the CLK clock signal. In the process of offset correction, the offset correction circuit is used for correction until the output value Q of the dynamic comparator is reversed. At this time, the correction has been completed, and the correction error is the correction voltage value of a single correction clock. The CLK clock signal separates the correction process of the dynamic comparator from the comparison process in the successive approximation analog-to-digital converter system, avoiding the influence of the system on the offset correction process.

The working sequence of the offset self-correcting dynamic comparator is shown in Figure 5. When the sequential analog-to-digital converter system is working, the offset self-correcting dynamic comparator is corrected first to avoid being affected by the system during the correction process of the dynamic comparator. Correction accuracy. When CAL is high, the self-correcting dynamic comparator enters offset correction mode. After entering the offset correction mode, precharge the correction capacitor Ccal first. When CALB is high, charge the upper plate voltage of the correction capacitor Ccal to the common mode level VCM. When CALB is low, as shown in Figure 5 The pre-charging ends at t1. The offset correction clock generated by the internal signal of the self-calibration dynamic comparator is clk_calib. When clk_calib is at a high level, the self-calibration circuit performs offset correction. The correction accuracy is related to the value of the capacitor. The larger the difference between C1, C2 and Ccal, the higher the correction accuracy. high. When clk_calib is at low level, the self-calibration circuit charges capacitors C1 and C2 to VDD and GND respectively, and performs charge redistribution when the next clk_calib clock is at high level, and performs corrections in turn. At time t2, the output signal Q of the dynamic comparator is reversed, the OFF signal jumps from high level to low level, the correction is over, and the offset correction circuit stops working. Wait until time t3, the clk clock in the successive approximation analog-to-digital converter arrives, and the self-correcting dynamic comparator starts to work in the successive-approximation analog-to-digital converter system.

The above description of the embodiments is for those of ordinary skill in the art to understand and apply the present invention. It is obvious that those skilled in the art can easily make various modifications to the above-mentioned embodiments, and apply the general principles described here to other embodiments without creative efforts. Therefore, the present invention is not limited to the above embodiments, and improvements and modifications made by those skilled in the art according to the disclosure of the present invention should fall within the protection scope of the present invention.

Claims (7)

1. A kind of offset self-correcting dynamic comparator for successive approximation analog-to-digital converter, it is characterized in that, comprises dynamic comparison circuit, offset correction circuit and clock control circuit; Wherein: The clock control circuit is used to generate the following three groups of clock signals: The clock signal CAL is used to control the offset correction circuit; The clock signal CALB is used to precharge the correction capacitor in the offset correction circuit so that its voltage reaches the common-mode level; The clock signal CLK is used for the reset of the dynamic comparison circuit and the control of the comparison stage; The dynamic comparison circuit is used to compare the two differential input signals inn and inp, and successively generate two differential comparison signals outn and outp under the control of the clock signal CLK; The offset correction circuit enters the offset correction mode under the control of the clock signals CAL and CALB, charges and discharges the corresponding correction capacitor according to the differential comparison signal, and changes the capacitor voltage by changing the charge size, so as to perform a dynamic comparison circuit offset correction. 2. The offset self-correcting dynamic comparator according to claim 1, characterized in that: the dynamic comparator circuit is composed of a pre-amplification circuit and a positive feedback latch structure and includes thirteen MOS transistors M1-M13, wherein: MOS The source of the tube M1 is grounded, the gate of the MOS tube M1 is connected to the clock signal CLK, the drain of the MOS tube M1 is connected to the source of the MOS tube M2 and the source of the MOS tube M3, the gate of the MOS tube M2 is connected to the source of the MOS tube M3 The gates of the gates are respectively connected to the differential input signals inn and inp, the drain of the MOS transistor M2 is connected to the drain of the MOS transistor M4, the gate of the MOS transistor M6 and the gate of the MOS transistor M12, and the drain of the MOS transistor M3 is connected to the gate of the MOS transistor M4. The drain of M5 is connected to the gate of MOS transistor M7 and the gate of MOS transistor M13, the gate of MOS transistor M4 is connected to the gate of MOS transistor M5 and connected to the clock signal CLK, the source of MOS transistor M4 is connected to the gate of MOS transistor M5 The source of the MOS transistor M12 is connected to the source of the MOS transistor M10 and grounded, the source of the MOS transistor M13 is connected to the source of the MOS transistor M11 and grounded, and the drain of the MOS transistor M12 It is connected to the drain of the MOS transistor M10, the drain of the MOS transistor M8, the gate of the MOS transistor M9, and the gate of the MOS transistor M11 to output a differential comparison signal outn, and the drain of the MOS transistor M13 is connected to the drain of the MOS transistor M11, The drain of the MOS transistor M9, the gate of the MOS transistor M8, and the gate of the MOS transistor M10 are connected to output a differential comparison signal outp, the source of the MOS transistor M8 is connected to the drain of the MOS transistor M6, and the source of the MOS transistor M9 is connected to the drain of the MOS transistor M9. The drain of the MOS transistor M7 is connected, the source of the MOS transistor M6 is connected to the source of the MOS transistor M7 and connected to the working voltage VDD. 3. The offset self-correcting dynamic comparator according to claim 2, characterized in that: MOS transistors M1-M5 form a pre-amplification circuit, and MOS transistors M6-M13 form a positive feedback latch structure; wherein, MOS transistors M1-M5 form a positive feedback latch structure; M3 and MOS transistors M10-M13 are NMOS transistors, and MOS transistors M4-M5 and MOS transistors M6-M9 are PMOS transistors. 4. The offset self-correcting dynamic comparator according to claim 2, characterized in that: the offset correction circuit is composed of two offset correction modules with the same structure, and the offset correction module is composed of a pre-charging circuit and a capacitor charging and discharging The circuit consists of two inverters INV1 and INV2, a NAND gate, an AND gate, two common capacitors C1 and C2, a correction capacitor, a controllable switch and five MOS transistors M16, M18~M21; Among them: the first input terminal of the NAND gate is connected to the differential comparison signal outp, the second input terminal of the NAND gate is connected to the first input terminal of the AND gate and connected to the clock signal CAL, and the second input terminal of the AND gate is connected to the differential comparison signal outn, the output terminal of the NAND gate is connected to the gate of the MOS transistor M19 and the input terminal of the inverter INV1, the output terminal of the AND gate is connected to the gate of the MOS transistor M20 and the input terminal of the inverter INV2, and the inverter The output terminal of INV1 is connected to the gate of MOS transistor M18, the output terminal of inverter INV2 is connected to the gate of MOS transistor M21, the source of MOS transistor M18 is connected to the working voltage VDD, the drain of MOS transistor M18 is connected to the capacitor C1 One end is connected to the source of the MOS transistor M19, the other end of the capacitor C1 is grounded, the drain of the MOS transistor M21 is connected to one end of the capacitor C2 and the source of the MOS transistor M20, and the other end of the capacitor C2 is connected to the source of the MOS transistor M21 and grounded, the drain of the MOS transistor M19 is connected to the drain of the MOS transistor M20, one end of the controllable switch, the gate of the MOS transistor M16 and one end of the correction capacitor, and the other end of the controllable switch is connected to the common mode level, and the controllable The control electrode of the switch is connected to the clock signal CALB, the other end of the correction capacitor is grounded, and the drain and source of the MOS transistor M16 are respectively used as two output ports O1 and O2 of the offset correction module; one of the output ports O1 and O2 of the offset correction module They are respectively connected to the drain and source of the MOS transistor M2 in the dynamic comparison circuit, and the output ports O1 and O2 of the other offset correction module are respectively connected to the drain and source of the MOS transistor M3 in the dynamic comparison circuit. 5. The offset self-correcting dynamic comparator according to claim 4, characterized in that: the controllable switch, the correction capacitor and the MOS transistor M16 form a pre-charging circuit, and the MOS transistors M18-M21, inverters INV1 and INV2, and A NOT gate, an AND gate, and ordinary capacitors C1 and C2 form a capacitor charging and discharging circuit; among them, the MOS transistors M16, M20 and M21 are NMOS transistors, and the MOS transistors M18 and M19 are PMOS transistors. 6. The offset self-correcting dynamic comparator according to claim 1, wherein the clock control circuit includes an offset circuit correction signal generation module, a CLK clock signal generation module and a CALB clock signal generation module, wherein: The offset circuit correction signal generation module includes an AND gate U1 and a delayer T1, the two input terminals of the AND gate are respectively connected to the inverting signals out+ and out- corresponding to the differential comparison signals outn and outp, and the output terminals of the AND gate Connected to the input terminal of the delay device, the output terminal of the delay device generates a correction signal clk_calib; The CLK clock signal generation module includes a three-input AND gate U2, a NOR gate, an OR gate, a delayer T2 and an inverter INV3, and the two input terminals of the NOR gate are respectively connected to the current and previous The output value of a comparator, the output value of the comparator is the output Q value after the inversion signal out+ and out- are input to the RS flip-flop, and the output terminal of the OR gate is connected to the input terminal of the inverter INV3, and the inverter The output terminal of INV3 generates the clock signal OFF, and the three input terminals of the AND gate U2 are respectively connected to the correction signal clk_calib, the clock signal OFF and the clock signal CAL, and the output terminal of the AND gate U2 is connected to the first input terminal of the OR gate, and the OR gate The second input terminal is connected to the clock signal clk of the external given comparator, and the output terminal of the OR gate is connected to the input terminal of the delayer T2, and the output terminal of the delayer T2 generates the clock signal CLK; The CALB clock signal generation module includes a two-stage frequency division clock circuit, the first stage frequency division clock circuit is formed by cascading a plurality of frequency division units, each frequency division unit includes a D flip-flop and an inverter, D The input terminal of the flip-flop is connected to the output terminal of the inverter, the output terminal of the D flip-flop is connected to the input terminal of the inverter and used as the output terminal of the frequency division unit, and the clock terminal of the D flip-flop is used as the input terminal of the frequency division unit , the output terminal of the previous frequency division unit is connected to the input terminal of the latter frequency division unit, and the input terminal of the first frequency division unit is connected to the correction signal clk_calib; the second stage frequency division clock circuit includes multiple cascaded D flip-flops And an inverter INV4, the output terminal of the previous D flip-flop is connected to the input terminal of the next D flip-flop, the input terminal of the first D flip-flop is connected to high level, and the output terminal of the last D flip-flop is connected to the inverted The input terminals of the phaser INV4 are connected, the output terminal of the inverter INV4 generates the clock signal CALB, and the clock terminals of each D flip-flop are connected together and connected to the output terminal of the last frequency division unit in the first stage frequency division clock circuit. 7. The offset self-correcting dynamic comparator according to claim 1, characterized in that: the clock signal CAL is given externally and generated by a clock control circuit, and when it is at a high level, it controls the offset correction circuit to perform correction, and the comparator enters Offset correction mode.