CN113852373A - Assembly line domino structure successive approximation type analog-to-digital converter - Google Patents

Abstract

The invention provides a pipeline domino structure successive approximation type analog-to-digital converter, comprising: n+1 stage sub-ADC, multiple residual amplifiers and preset adjustment modules; the input end of the first stage sub-ADC is connected with the signal input end, It is used to obtain the input signal after sampling; the output end of the sub-ADC includes a first output end, and the first output end is connected with the preset adjustment module, and is used for inputting the 5-bit quantization code generated by each sub-ADC to the preset adjustment module, In order to make the preset adjustment module perform splicing and redundancy bit correction on the quantization code to obtain an analog-to-digital conversion result; the first to n stages of sub-ADCs also include a second output terminal, which is used for the residual signal generated by the sub-ADC to be processed by the residual difference. The signal amplified by the amplifier is used as the input signal and input to the next stage sub-ADC. The invention improves the conversion speed and precision of the SAR ADC, can correct the offset voltage in real time during the working process of the comparator, and prevent the performance of the sub-ADC from being affected by the offset accumulation.

Description

A pipelined domino successive approximation analog-to-digital converter

technical field

The invention belongs to the technical field of integrated circuits, and in particular relates to a successive approximation analog-to-digital converter with a pipeline domino structure.

Background technique

With the rapid development of integrated circuits, the performance requirements of ADC (Analog to Digital Converter) in portable electronic applications such as wireless communication, image and video are also constantly improving, with high resolution, high conversion rate, low distortion and Designing for low power consumption has become a major challenge in analog-to-digital converter design.

At present, the analog-to-digital converter mostly adopts a pipeline structure, and the conversion mode of the analog-to-digital converter in the conversion speed, accuracy and power consumption is realized by cascading multiple sub-ADCs and working in a pipeline. A SAR ADC (Successive Approximation Register, successive approximation analog-to-digital converter) is a commonly used analog-to-digital converter. In order to realize a high-speed SAR ADC, time-domain interleaving and pipeline structure are generally used in related technologies. However, the mismatch between multiple channels of the time-domain interleaved SAR ADC will seriously affect the performance of the ADC. The pipelined SAR ADC replaces the fully parallel ADC in the pipeline with the SAR ADC, which is limited by the speed of the traditional asynchronous logic SAR ADC. This method has high requirements on the bandwidth of the residual difference amplifier, and at the same time requires the establishment of the amplified residual difference signal in a short time, thus greatly increasing the power consumption of the residual difference amplifier.

SUMMARY OF THE INVENTION

In order to solve the above problems existing in the prior art, the present invention provides a successive approximation analog-to-digital converter with a pipeline domino structure. The technical problem to be solved by the present invention is realized by the following technical solutions:

The present invention provides a pipeline domino structure successive approximation type analog-to-digital converter, comprising: n+1 stage sub-ADCs, multiple residual amplifiers and preset adjustment modules; wherein,

The sub-ADC includes an input end and an output end, and the input end of the first-stage sub-ADC is connected to the signal input end for obtaining an input signal after sampling; the output end of the sub-ADC includes a first output end, the first An output terminal is connected to the preset adjustment module, and is used for inputting the 5-bit quantization code generated by the sub-ADCs to the preset adjustment module, so that the preset adjustment module can process the 5-bit quantization code generated by each sub-ADC. Perform splicing and redundant bit correction to obtain analog-to-digital conversion results;

The first to n-stage sub-ADCs further include a second output terminal, and the second output terminal is connected to the next-stage sub-ADC through the residual amplifier, and is used to pass the residual signal generated by the sub-ADC through the residual ADC. The signal amplified by the difference amplifier is used as the input signal and input to the next stage sub-ADC.

In an embodiment of the present invention, it further includes a first reference voltage signal terminal, a second reference voltage signal terminal, and a third reference voltage signal terminal, and the signal input terminal includes a first signal input terminal and a second signal input terminal;

The sub-ADC includes: a first module, a second module, a calibration circuit and an output module, the first module includes comparators: A1-A5, a first type of capacitor, a second type of capacitor, a first type of switch, a second type of capacitor Class switches and preset logic circuits corresponding to A1 to A5 respectively, the first class switches include a plurality of first switch groups, the second class switches include a plurality of second switch groups, each of the first switches The group includes three first switches, and each of the second switch groups includes three second switches; wherein,

The first input end of each comparator is connected to the first signal input end, the second input end is connected to the second signal input end, and the output end is connected to its corresponding preset logic circuit; the first type capacitor The first terminals are connected to the first signal input terminal, and the second terminals are respectively connected to the first reference voltage signal terminal and the second reference voltage signal terminal through the three first switches in the first switch group. or the third reference voltage signal terminal;

The first terminals of the second type of capacitors are all connected to the second signal input terminal, and the second terminals are respectively connected to the first reference voltage signal terminal through three second switches in the second switch group. The second reference voltage signal terminal or the third reference voltage signal terminal.

In an embodiment of the present invention, in the first to n stages of sub-ADCs, the first type of capacitors include: Cs1 to Cs5, and the second type of capacitors include: Cs6 to Cs10, Cs1, Cs2, Cs3, Cs4 and The ratio of capacitance values of Cs5 is 16:8:4:2:1, and the ratio of capacitance values of Cs6, Cs7, Cs8, Cs9 and Cs10 is 16:8:4:2:1.

In an embodiment of the present invention, the first stage sub-ADC further includes a second module, the second module includes a third type of capacitor, a fourth type of capacitor, a third type of switch and a fourth type of switch, the The third type of switches includes a plurality of third switch groups, the fourth type of switches includes a plurality of fourth switch groups, each of the third switch groups includes three third switches, and each of the fourth switch groups includes three fourth switches; of which,

The first terminals of the third type of capacitors are all connected to the first signal input terminal, and the second terminals are respectively connected to the first reference voltage signal terminal through three third switches in the third switch group. the second reference voltage signal terminal or the third reference voltage signal terminal;

The first terminals of the fourth type of capacitors are all connected to the second signal input terminal, and the second terminals are respectively connected to the first reference voltage signal terminal through three fourth switches in the fourth switch group. The second reference voltage signal terminal or the third reference voltage signal terminal.

In an embodiment of the present invention, in the first stage sub-ADC, the third type of capacitors include: Cs11 to Cs15, and the second type of capacitors include: Cs16 to Cs20, Cs11, Cs12, Cs13, Cs14 and Cs15 The ratio of the capacitance values of Cs16, Cs17, Cs18, Cs19 and Cs20 is 16:8:4:2:1.

In an embodiment of the present invention, the sub-ADC further includes a calibration circuit and an output module, wherein the calibration circuit is used for calibrating the offset voltages of A1-A5, and the output module is used for storing the data generated by the sub-ADC 5-bit quantization code.

In an embodiment of the present invention, it further includes a power signal terminal; the comparator includes a first sub-module and a second sub-module, and the first sub-module includes first transistors: M1 to M7 and an inverter: B1 , B2, the second sub-module includes second transistors: M8-M14 and inverters: B1-B4; wherein,

The source of M1 is connected to the power signal terminal, the drain is connected to the source of M2, the gate is connected to the gate of M4, the gate of M2 is connected to the second signal input terminal, and the drain is connected to the drain of M4 The source of M4 is grounded, the drain of M1 and the source of M2 include a first node, the gate of M3 is connected to the second reference voltage signal terminal, the source is connected to the first node, The drain is connected to the second node, a third node is included between the drain of M4 and the drain of M2, the source of M4 is grounded, the gate of M5 is connected to the clock signal, the drain is connected to the second node, and the source is grounded , the gate of M6 is connected to the first reset signal, the drain is connected to the second node, and the source is grounded; the gate of M7 is connected to the second reset signal, the drain is connected to the second node, and the source is grounded; the input of B1 The terminal is connected to the drain of M4, and the output terminal of B1 is connected to the input terminal of B2;

The source of M8 is connected to the power signal terminal, the drain is connected to the source of M9, the gate is connected to the gate of M11, the gate of M9 is connected to the second signal input terminal, and the drain is connected to the drain of M11 The source of M11 is grounded, the drain of M8 and the source of M9 include a fourth node, the gate of M10 is connected to the second reference voltage signal terminal, the source is connected to the fourth node, The drain is connected to the fifth node, a sixth node is included between the drain of M11 and the drain of M9, the source of M11 is grounded, the gate of M12 is connected to the clock signal, the drain is connected to the fifth node, and the source is grounded , the gate of M13 is connected to the first reset signal, the drain is connected to the fifth node, and the source is grounded; the gate of M14 is connected to the second reset signal, the drain is connected to the fifth node, and the source is grounded; the input of B3 The terminal is connected to the drain of M11, and the output terminal of B3 is connected to the input terminal of B4;

The third node is connected to the gate of M8, and the sixth node is connected to the gate of M1.

In one embodiment of the present invention, M1, M2, M3, M8, M9 and M10 are P-type field effect transistors, and M4, M5, M6, M7, M11, M12, M13 and M14 are N-type super-effect transistors.

In an embodiment of the present invention, the calibration circuit includes third transistors: M15˜M25, a preset current source, AND gates: C1 and C2, and an inverter B5; wherein,

The gate of M15 is connected to the gate of M16, the source of M15 and the source of M16 are both connected to the power signal terminal, the drain of M15 is connected to the source of M17, the gate of M17 is grounded, and the drain is connected to M19 The drain of M19 is connected to the drain of M21, the source of M21 is grounded, the drain of M16 is connected to the source of M18, the gate of M18 is connected to the first switch signal, the drain of M18 is connected to M20 The drain of M18 and the drain of M20 include a seventh node, the seventh node is connected to the first reference voltage, the gate of M20 is connected to the second switch signal, and the source is connected to M22 The drain of M22 is connected to the ground, the gate of M22 is connected to the preset current source, the eighth node is included between the preset current source and the gate of M22, the gate of M23 and the gate of M21 are both connected to the eighth node, the drain of M23 is connected to the preset current source, and the source is grounded;

The first input terminal of the comparator is connected to the second input terminal through a first switch, the third input terminal is connected to the first reference voltage, the first output terminal is connected to the first input terminal of C1, and the second input terminal is connected to the first reference voltage. The output terminal is connected to the first input terminal of C2, the second input terminal of C1 and the second input terminal of C2 are both connected to the enable signal, the gate of M24 is connected to the power signal terminal, the source of M24 is connected to the source of M25. The source is connected to the ninth node, the ninth node is connected to the second switch signal, the drain of M24 and the drain of M25 are connected to the tenth node, the tenth node is connected to the output end of C1, and the M25 The gate of C2 is grounded, and the output of C2 is connected to the input of inverter B5.

Compared with the related art, the beneficial effects of the present invention are:

The invention provides a pipeline domino structure successive approximation type analog-to-digital converter, comprising: n+1 stage sub-ADC, multiple residual amplifiers and preset adjustment modules; wherein, the sub-ADC includes an input end and an output end, and the first stage The input end of the sub-ADC is connected to the signal input end for obtaining the input signal after sampling; the output end of the sub-ADC includes a first output end, and the first output end is connected to the preset adjustment module, and is used to convert the 5 The bit quantization code is input to the preset adjustment module, so that the adjustment module performs splicing and redundancy bit correction on the 5-bit quantization code generated by each sub-ADC to obtain an analog-to-digital conversion result; the first to n stages of sub-ADCs also include Two output terminals, the second output terminal is connected to the sub-ADC of the next stage through the residual difference amplifier, and is used to use the signal amplified by the residual difference signal generated by the sub-ADC by the residual difference amplifier as an input signal, and input it to the sub-ADC of the next stage . The invention adopts a multi-stage sub-ADC structure, which improves the conversion speed and accuracy of the SAR ADC. Since each sub-ADC includes a calibration circuit, the offset voltage can be corrected in real time during the working process of the comparator to prevent the comparator from being caused by the accumulation of offsets. The performance of the sub ADC is degraded.

The present invention will be further described in detail below with reference to the accompanying drawings and embodiments.

Description of drawings

1 is a schematic structural diagram of a successive approximation analog-to-digital converter of a pipeline domino structure provided by an embodiment of the present invention;

2 is a schematic structural diagram of a first-stage sub-ADC provided by an embodiment of the present invention;

FIG. 3 is a schematic structural diagram of the second to n-stage sub-ADCs provided by an embodiment of the present invention;

FIG. 4 is a schematic structural diagram of the n+1th stage sub-ADC provided by an embodiment of the present invention;

5 is a schematic structural diagram of a comparator provided by an embodiment of the present invention;

6 is a schematic structural diagram of a latch in a comparator provided by an embodiment of the present invention;

7 is a schematic structural diagram of a calibration circuit provided by an embodiment of the present invention;

8 is a working sequence diagram of a first-stage sub-ADC provided by an embodiment of the present invention;

9 is a working sequence diagram of a second-stage sub-ADC provided by an embodiment of the present invention;

FIG. 10 is a working timing diagram of a third-stage sub-ADC provided by an embodiment of the present invention.

Detailed ways

The present invention will be described in further detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

FIG. 1 is a schematic structural diagram of a successive approximation analog-to-digital converter of a pipeline domino structure provided by an embodiment of the present invention. Referring to FIG. 1, the present invention provides a pipelined domino structure successive approximation analog-to-digital converter 100, including: n+1 stage sub-ADCs 10, a plurality of residual amplifiers 20 and a preset adjustment module 30; wherein,

The sub-ADC10 includes an input end and an output end, and the input end of the first stage sub-ADC10 is connected to the signal input end for obtaining the input signal after sampling; the output end of the sub-ADC10 includes a first output end, and the first output end is connected to the preset The adjustment module 30 is connected for inputting the 5-bit quantization code generated by the sub-ADC 10 to the preset adjustment module 30, so that the preset adjustment module 30 performs splicing and redundancy bit correction on the 5-bit quantization code generated by each sub-ADC 10 to obtain A/D conversion result;

The first to n-stage sub-ADCs 10 further include a second output terminal, and the second output terminal is connected to the next-stage sub-ADC 10 via the residual amplifier 20 , and is used to amplify the residual signal generated by the sub-ADC 10 and amplified by the residual amplifier 20 . As an input signal, it is input to the next stage sub-ADC10.

2 is a schematic structural diagram of a first-stage sub-ADC provided by an embodiment of the present invention, FIG. 3 is a schematic structural diagram of a second-n-stage sub-ADC provided by an embodiment of the present invention, and FIG. 4 is provided by an embodiment of the present invention. A schematic diagram of the structure of the n+1th stage sub-ADC. Please refer to FIGS. 2-4. Optionally, the successive approximation analog-to-digital converter 100 with the pipeline domino structure further includes a first reference voltage signal terminal VREF, a second reference voltage signal terminal VCM, and a third reference voltage signal terminal GND. The signal The input terminal includes a first signal input terminal V _IN and a second signal input terminal V _IP ;

The sub-ADC 10 includes: a first module 101, a second module 102, a calibration circuit 103 and an output module 104. The first module 101 includes comparators: A1-A5, first-type capacitors, second-type capacitors, first-type switches, The switches of the second type and the preset logic circuits corresponding to A1 to A5 respectively, the switches of the first type include a plurality of first switch groups SW1, the switches of the second type include a plurality of second switch groups SW2, and each first switch group SW1 includes a plurality of first switch groups SW1. three first switches, and each second switch group SW2 includes three second switches; wherein,

The first input end of each comparator is connected to the first signal input end V _IN , the second input end is connected to the second signal input end V _IP , and the output end is connected to its corresponding preset logic circuit; One end is connected to the first signal input end V _IN , and the second end is respectively connected to the first reference voltage signal end VREF, the second reference voltage signal end VCM or the third through the three first switches in the first switch group SW1. Reference voltage signal terminal GND;

The first terminals of the second type capacitors are all connected to the second signal input terminal V _IP , and the second terminals are respectively connected to the first reference voltage signal terminal VREF and the second reference voltage through the three second switches in the second switch group SW2. The signal terminal VCM or the third reference voltage signal terminal GND.

It should be noted that, in this embodiment, the structures of the sub-ADCs 10 in the second to n stages of the sub-ADCs 10 are the same, and the structure of the first stage of the sub-ADCs 10 is different from that of the second to n stages of sub-ADCs 10 . Specifically, the first stage In addition to the first module 101 , the sub ADC 10 also includes a second module 102 .

Optionally, as shown in FIG. 2 , the first stage sub-ADC 10 further includes a second module 102, and the second module 102 includes a third type of capacitor, a fourth type of capacitor, a third type of switch, a fourth type of switch, and a third type of switch. The switches include a plurality of third switch groups SW3, the fourth type of switches includes a plurality of fourth switch groups SW4, each third switch group SW3 includes three third switches, and each fourth switch group SW4 includes three fourth switches ;in,

The first terminals of the third type capacitors are all connected to the first signal input terminal V _IN , and the second terminals are respectively connected to the first reference voltage signal terminal VREF and the second reference voltage through the three third switches in the third switch group SW3. The signal terminal VCM or the third reference voltage signal terminal GND;

The first terminals of the fourth type capacitors are all connected to the second signal input terminal V _IP , and the second terminals are respectively connected to the first reference voltage signal terminal VREF and the second reference voltage through three fourth switches in the fourth switch group SW4. The signal terminal VCM or the third reference voltage signal terminal GND.

Optionally, as shown in FIGS. 2-4 , the sub-ADC 10 further includes a calibration circuit 103 and an output module 104, wherein the calibration circuit 103 is used to calibrate the offset voltages of A1 to A5, and the output module 104 is used to store the 5 Bit quantization code.

FIG. 5 is a schematic structural diagram of a comparator provided by an embodiment of the present invention. As shown in FIG. 5 , the successive approximation analog-to-digital converter 100 with the pipeline domino structure further includes a power supply signal terminal VDD; the comparator includes a first sub-module 201 and a second sub-module 202, and the first sub-module 201 includes a first transistor: M1-M7 and inverters: B1, B2, the second sub-module 202 includes second transistors: M8-M14 and inverters: B1-B4; wherein,

The source of M1 is connected to the power signal terminal VDD, the drain is connected to the source of M2, the gate is connected to the gate of M4, the gate of M2 is connected to the second signal input terminal VIP, and the _drain is connected to the drain of M4 connected, the source of M4 is grounded, the first node N1 is included between the drain of M1 and the source of M2, the gate of M3 is connected to the second reference voltage signal terminal VCM, the source is connected to the first node N1, the drain Connected to the second node N2, a third node N3 is included between the drain of M4 and the drain of M2, the source of M4 is grounded, the gate of M5 is connected to the clock signal, the drain is connected to the second node N2, and the source Grounding, the gate of M6 is connected to the first reset signal, the drain is connected to the second node N2, and the source is grounded, the gate of M7 is connected to the second reset signal, the drain is connected to the second node N2, and the source is grounded; The input terminal of B1 is connected to the drain of M4, and the output terminal of B1 is connected to the input terminal of B2;

The source of M8 is connected to the power signal terminal VDD, the drain is connected to the source of M9, the gate is connected to the gate of M11, the gate of M9 is connected to the second signal input terminal VIP, and the drain is connected to the drain of _M11 connected, the source of M11 is grounded, the drain of M8 and the source of M9 include a fourth node, the gate of M10 is connected to the second reference voltage signal terminal VCM, the source is connected to the fourth node N4, the drain is connected to The fifth node N5 is connected, a sixth node N6 is included between the drain of M11 and the drain of M9, the source of M11 is grounded, the gate of M12 is connected to the clock signal, the drain is connected to the fifth node N5, and the source is grounded , the gate of M13 is connected to the first reset signal, the drain is connected to the fifth node N5, the source is grounded, the gate of M14 is connected to the second reset signal, the drain is connected to the fifth node N5, and the source is grounded; B3 The input terminal of M11 is connected to the drain, and the output terminal of B3 is connected to the input terminal of B4;

The third node N3 is connected to the gate of M8, and the sixth node N6 is connected to the gate of M1.

Optionally, M1, M2, M3, M8, M9 and M10 are P-type field effect transistors, and M4, M5, M6, M7, M11, M12, M13 and M14 are N-type super-effect transistors.

In addition, it should be noted that in this embodiment, the comparators A1 to A5 further include latches as shown in FIG. 6 , which are used to store the quantization codes generated after the quantization is completed.

FIG. 7 is a schematic structural diagram of a calibration circuit provided by an embodiment of the present invention. As shown in FIG. 7 , in the successive approximation analog-to-digital converter 100 with the pipeline domino structure, the calibration circuit 103 includes third transistors: M15-M25, a preset current source IC, AND gates: C1 and C2, and an inverter B5; in,

The gate of M15 is connected to the gate of M16, the source of M15 and the source of M16 are both connected to the power supply signal terminal VDD, the drain of M15 is connected to the source of M17, the gate of M17 is grounded, the drain is connected to the source of M19 The drain is connected, the source of M19 is connected to the drain of M21, the source of M21 is grounded, the drain of M16 is connected to the source of M18, the gate of M18 is connected to the first switch signal SPS, the drain of M18 is connected to M20 The drain of M18 and the drain of M20 include a seventh node N7, the seventh node N7 is connected to the first reference voltage Vc, the gate of M20 is connected to the second switch signal SNS, the source is connected to M22 The drain of M22 is connected to the ground, the gate of M22 is connected to the preset current source IC, the eighth node N8 is included between the preset current source IC and the gate of M22, and the gate of M23 and the gate of M21 are connected to The eighth node N8 is connected, the drain of M23 is connected to the preset current source IC, and the source is grounded;

The first input end and the second input end of the comparator are connected through the first switch, the third input end is connected with the first reference voltage Vc, the first output end is connected with the first input end of C1, and the second output end is connected with the first input end of C2. The first input terminal is connected, the second input terminal of C1 and the second input terminal of C2 are both connected to the enable signal EN, the gate of M24 is connected to the power signal terminal VDD, the source of M24 and the source of M25 are connected to the first input terminal. The ninth node N9, the ninth node N9 is connected to the second switch signal SNS, the drain of M24 and the drain of M25 are connected to the tenth node N10, the tenth node N10 is connected to the output end of C1, the gate of M25 is grounded, C2 The output terminal of the inverter B5 is connected to the input terminal.

Optionally, in the first to n stages of sub-ADCs, the first type of capacitors include: Cs1 to Cs5, the second type of capacitors include: Cs6 to Cs10, and the ratio of the capacitance values of Cs1, Cs2, Cs3, Cs4 and Cs5 is 16: 8:4:2:1, the ratio of capacitance values of Cs6, Cs7, Cs8, Cs9 and Cs10 is 16:8:4:2:1.

Exemplarily, the pipelined domino structure successive approximation analog-to-digital converter in this embodiment may include three stages of 5-bit sub-ADCs. Please continue to refer to Figure 2. For the first-stage 5-bit sub-ADC, CLKS1 is the first-stage sampling clock signal, and the sampling frequency can be 1GHz, that is, the period is 1ns. In the 1ns period, 250ps is used for sampling, and 750ps is used for sampling Conversion, residual amplification and offset calibration. Optionally, the first reference voltage signal terminal VREF=0.9mV, the second reference voltage signal terminal VCM=450mV, and the input signal of Vpp=1.8V can be quantized. The first module 101 and the second module 102 sample the first signal input terminal V _IN and the second signal input terminal V _IP at the same time, and the comparator compares the voltage of the first type capacitor and the second type capacitor in the first module 101 , and feed back the comparison result to the preset logic circuits of the first module 101 and the second module 102 .

It should be noted that, among the first type capacitors, the second type capacitors, the third type capacitors and the fourth type capacitors, the capacitors are arranged according to the weights of 16:8:4:2:1, and the third type of capacitors in the second module 102 The unit capacitances of the capacitors and the fourth type of capacitors are larger than the unit capacitances of the first type of capacitors and the second type of capacitors in the first module 101 . This design method can enable the small capacitors in the first module 101 to achieve a faster quantization code conversion process. , and the large capacitor in the second module 102 can ensure the accuracy of the residual level output after the quantization is completed, and at the same time meet the requirements of KT/C noise. During the conversion period, the residual amplifier 20 operates in a stable state in which the inputs are all common-mode signals. After the conversion is completed, the capacitor array of the second module 102 (ie the third type of capacitor and the fourth type of capacitor) is connected to the input of the residual amplifier 20 At the end, a multiplying digital-to-analog converter MDAC circuit is formed.

FIG. 8 is a working timing diagram of a first-stage sub-ADC provided by an embodiment of the present invention. In the following, please refer to Figure 2 and Figure 8, still take the pipeline domino structure successive approximation analog-to-digital converter including 3-stage 5-bit SAR sub-ADC as an example, and combine the timing diagram to introduce the working principle of the first-stage sub-ADC.

The first-stage clock signal CLKS1 is sampled at high level and kept at low level. CLKS1 generates the clock signal CLKC5 of A1 after a delay, and the first comparison is triggered when CLKC5 changes from high to low.

The comparison result of the highest-order comparator A1 generates CLKC4 through the preset logic circuit, and then the same process generates the clock signals CLKC3, CLKC2, and CLKC1 of the comparators A2, A3, A4, and A5 in turn, and the output of the last comparator A5 passes through the preset logic. The circuit generates a control signal CLKC0. The five comparators continuously perform a binary search algorithm on the upper plate levels of the first type capacitors and the second type capacitors in the first module 101 at a faster rate, and the comparison results of A1 to A5 are also It is fed back to the preset logic circuit of the second module 102, and the second module 102 follows the first module 101 to generate the same successive approximation process, but the time for the third type capacitor and the fourth type capacitor to flip to a stable level is longer. The process is also the process of making a difference between the analog input signal in the MDAC and the DAC in the pipeline. The control signal CLKC0 is inverted to generate the latch control signal CLK_LOCK1, and the comparison result is stored in the latch structure, and no change occurs in this cycle, and the conversion cycle ends.

When the calibration reset signal RESET_1 arrives at a high level, the switch SV1 is turned on, and the first type capacitor and the second type capacitor in the first module 101 are short-circuited together to generate the same level of the positive and negative input terminals of the comparator for the calibration process.

In the previous conversion process, the positive and negative input terminals of the residual difference amplifier 20 are connected to the common mode level, so as to ensure that the residual difference amplifier 20 quickly enters a stable DC bias state during the residual difference amplification process. The common mode level control signal CLK_VCM1 changes from high level to low level, indicating the start of the residual amplifier stage.

The multiplying digital-to-analog converter control signal CLK_MDAC1 arrives at almost the same time as the high level of CLKS1 of the second stage, and the capacitor array in the second module 102 (ie the third type of capacitors and the fourth type of capacitors) is connected to the residual amplifier 20. The input end forms the multiplying digital-to-analog converter MDAC module in the pipeline ADC. The first type capacitor and the second type capacitor of the second stage 5bit SAR ADC10 are connected to the output terminal of the residual difference amplifier 20 to become the load of the operational amplifier. The operational amplifier approximately amplifies the difference signal between the analog input on the capacitor plate and the DAC by a factor of 16 through negative feedback and outputs it to the capacitor array of the second-stage first-type capacitor and the second-type capacitor. After the establishment of the residual amplified signal is completed, in order to ensure that the residual amplified signal sampled by the second stage is not disturbed, the second stage CLKS2 triggers the switch to turn off before CLK_MDAC1. In order to ensure that the input signal affects the DC bias state of the op amp, CLK_MDAC1 must be turned off before the rising edge of the second stage CLKS2.

In the process of the second module 102 participating in the amplification, the upper plates of the first type capacitor and the second type capacitor in the first module 101 are short-circuited to the same level, and then the comparator calibration reset signal RESET_c1 becomes low level, triggering the generation of The calibration enable signal EN1, during the short pulse time when EN1 is high, the two AND gates in the calibration logic no longer shield the CN1-5/CP1-5 signal, and adjust the VC voltage to compensate for the offset voltage. (The pulse width of EN1 determines the charging and discharging time)

Under the action of the output control clock signal CLK_D1, the quantization codes D15-11 are output.

When the high level of CLKS1 arrives, the EN1 signal is quickly triggered to become low level, and the output signal of the comparator is shielded. The high level of CLKS1 quickly resets all the comparators, connects the lower plates of the capacitor arrays of the first module 101 and the second module 102 to the VCM, and starts a new round of sampling cycle.

Further, when the pipelined domino structure successive approximation analog-to-digital converter includes 3-stage 5-bit sub-ADCs, please continue to refer to Figure 3. For the second-stage sub-ADC, CLKS2 is the first-stage sampling clock signal, and the frequency can be 1GHz, that is, The period is 1ns, and again, in one period, 250ps is used for sampling and 750ps for conversion, residual amplification and offset calibration. VREF=0.9mV, VCM=450mV, Vpp=1.8V input signal can be quantized, CLKS2 high level samples the residual difference amplification signal VOUTP2/VOUTN2 of the first stage. The capacitance design of the second-level 5bit SAR should consider the load capacity of the residual amplifier 20, the conversion speed and the accuracy of generating the residual. In the first type capacitor and the second type capacitor, the ratio of each capacitor is 16:8:4:2:1.

FIG. 9 is a working timing diagram of a second-stage sub-ADC provided by an embodiment of the present invention. Please refer to Figure 3 and Figure 9 to further introduce the working process of the second-level 5bit SAR sub-ADC:

CLKS2 is sampled at high level and kept at low level. CLKS2 is also the first comparison when the highest-order comparator clock CLKC5 changes from high to low.

The comparison result of the highest-order comparator A1 generates CLKC4 through a preset logic circuit, and then the same process generates the clock signals CLKC3, CLKC2, and CLKC1 of the comparators A2, A3, A4, and A5 in sequence. The output of the last comparator A5 generates a control signal CLKC0 through a preset logic circuit. The comparators A1 to A5 output 5-bit quantization codes in turn. The quantization codes are controlled by the logic circuit to switch the lower plate of the capacitor to produce a successive approximation process. This process is also the difference between the analog input signal in the multiplying digital-to-analog converter MDAC in the pipeline and the DAC. process. The inversion of CLKC0 generates the second-level latch control signal CLK_LOCK2, and the comparison result is stored in the latch structure, and no change occurs in this cycle, and the conversion cycle ends.

In the previous conversion process, the positive and negative input terminals of the op amp were connected to the common mode level. Ensure that the op amp quickly enters a stable DC bias state during the residual amplification process. The common mode control signal CLK_VCM1 changes from high level to low level, marking the beginning of the residual amplification stage

The multiplication digital-to-analog converter control signal CLK_MDAC2 and the high level of the third-stage clock signal CLKS3 arrive almost at the same time, and the second-stage capacitor array is connected to the input end of the op amp to form the MDAC module in the pipeline ADC. The capacitor array of the second stage 5bitSAR ADC is connected to the output end of the operational amplifier and becomes the load of the operational amplifier. The operational amplifier approximately amplifies the difference signal between the analog input on the capacitor plate and the DAC through negative feedback by approximately 16 times and outputs it to the capacitor array of the third stage. After the establishment of the residual amplification signal is completed, in order to ensure that the residual amplification signal sampled in the third stage is not disturbed, CLKS3 triggers the switch to turn off before CLK_MDAC2. The residual amplification cycle ends.

After the falling edge of the third-stage clock signal CLKS3, the switch SV2 is turned on, the differential input terminals of the second-stage capacitor plates are shorted together, and the circuit enters a calibration cycle.

When the capacitor plate voltage is the same, the comparator calibration reset signal RESET_c2 triggers the rapid reset of five comparators in the second stage. After the reset is completed, the comparison result under the action of the offset voltage is output.

During the high level window of the calibration enable signal EN2, the output of the comparator controls the charging or discharging of the current source, thereby compensating for the offset voltage.

The quantization code D10-6 is output under the action of the output control clock signal CLK_D2.

CLKS3 is the third-level sampling clock signal with a frequency of 1GHz and a period of 1ns, of which about 250ps are used for sampling, and the remaining 750ps are used for conversion, residual amplification, and offset calibration. VREF=0.9mV, VCM=450mV, Vpp=1.8V input signal can be quantized, CLKS3 high-level samples the residual amplification signal VOUTP2/VOUTN2 of the second stage. Since the third-stage 5-bit SAR sub-ADC does not need to transfer residuals, the ratio of the capacitance values of the first and second types of capacitors is 8, 4, 2, and 1.

FIG. 10 is a working timing diagram of a third-stage sub-ADC provided by an embodiment of the present invention. Please refer to Figure 4 and Figure 10. After the sampling of CLKS3 is completed, CLKC4, CLKC3, CLK2, and CLK1 generate and output their respective comparison results.

The low level of the third-level latch control signal CLK_LOCK3 arrives, the comparison result is latched, and the conversion cycle ends.

The high level of the third-stage comparator calibration reset signal RESET_c3 triggers the comparator reset. The conduction of the switch SV3 triggers a short circuit on the upper plate of the differential capacitor. RESET_c3 is a low level output offset comparison result.

In the high-level pulse window of the third-level calibration enable signal EN3, the comparison result controls the charging and discharging of the capacitor on the comparator to complete the calibration.

The quantization code D5-1 is output under the action of the output control clock signal CLK_D3.

As can be seen from the above-mentioned embodiments, the beneficial effects of the present invention are:

The invention provides a pipeline domino structure successive approximation type analog-to-digital converter, comprising: n+1 stage sub-ADC, multiple residual amplifiers and preset adjustment modules; wherein, the sub-ADC includes an input end and an output end, and the first stage The input end of the sub-ADC is connected to the signal input end for obtaining the input signal after sampling; the output end of the sub-ADC includes a first output end, and the first output end is connected to the preset adjustment module, and is used to convert the 5 The bit quantization code is input to the preset adjustment module, so that the adjustment module performs splicing and redundancy bit correction on the 5-bit quantization code generated by each sub-ADC to obtain an analog-to-digital conversion result; the first to n stages of sub-ADCs also include Two output terminals, the second output terminal is connected to the sub-ADC of the next stage through the residual difference amplifier, and is used to use the signal amplified by the residual difference signal generated by the sub-ADC by the residual difference amplifier as an input signal, and input it to the sub-ADC of the next stage . The invention adopts a multi-stage sub-ADC structure, which improves the conversion speed and accuracy of the SAR ADC. Since each sub-ADC includes a calibration circuit, the offset voltage can be corrected in real time during the working process of the comparator to prevent the comparator from being caused by the accumulation of offsets. The performance of the sub ADC is degraded.

In the description of the present invention, the terms "first" and "second" are only used for the purpose of description, and cannot be understood as indicating or implying relative importance or implying the number of indicated technical features. Thus, a feature defined as "first" or "second" may expressly or implicitly include one or more of that feature. In the description of the present invention, "plurality" means two or more, unless otherwise expressly and specifically defined.

In the present invention, unless otherwise expressly specified and limited, a first feature "on" or "under" a second feature may include the first and second features in direct contact, or may include the first and second features Not directly but through additional features between them. Also, the first feature being "above", "over" and "above" the second feature includes the first feature being directly above and obliquely above the second feature, or simply means that the first feature is level higher than the second feature. The first feature is "below", "below" and "below" the second feature includes the first feature being directly below and diagonally below the second feature, or simply means that the first feature has a lower level than the second feature.

In the description of this specification, description with reference to the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples", etc., mean specific features described in connection with the embodiment or example , structure, material or feature is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, those skilled in the art may combine and combine the different embodiments or examples described in this specification.

Although the application is described herein in conjunction with the various embodiments, those skilled in the art will understand and understand from a review of the drawings, the disclosure, and the appended claims in practicing the claimed application. Other variations of the disclosed embodiments are implemented. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that these measures cannot be combined to advantage.

The above content is a further detailed description of the present invention in combination with specific preferred embodiments, and it cannot be considered that the specific implementation of the present invention is limited to these descriptions. For those of ordinary skill in the technical field of the present invention, without departing from the concept of the present invention, some simple deductions or substitutions can be made, which should be regarded as belonging to the protection scope of the present invention.

Claims (9)

1. a pipeline domino structure successive approximation type analog-to-digital converter, is characterized in that, comprises: n+1 stage sub-ADC, multiple residual amplifiers and preset adjustment module; Wherein, The sub-ADC includes an input end and an output end, and the input end of the first-stage sub-ADC is connected to the signal input end for obtaining an input signal after sampling; the output end of the sub-ADC includes a first output end, the first An output terminal is connected to the preset adjustment module, and is used for inputting the 5-bit quantization code generated by the sub-ADCs to the preset adjustment module, so that the preset adjustment module can process the 5-bit quantization code generated by each sub-ADC. Perform splicing and redundant bit correction to obtain analog-to-digital conversion results; The first to n-stage sub-ADCs further include a second output terminal, and the second output terminal is connected to the next-stage sub-ADC through the residual amplifier, and is used to pass the residual signal generated by the sub-ADC through the residual ADC. The signal amplified by the difference amplifier is used as the input signal and input to the next stage sub-ADC. 2. The pipeline domino structure successive approximation analog-to-digital converter according to claim 1, characterized in that, further comprising a first reference voltage signal terminal, a second reference voltage signal terminal and a third reference voltage signal terminal, the signal The input terminal includes a first signal input terminal and a second signal input terminal; The sub-ADC includes: a first module, a second module, a calibration circuit and an output module, the first module includes comparators: A1-A5, a first type of capacitor, a second type of capacitor, a first type of switch, a second type of capacitor Class switches and preset logic circuits corresponding to A1 to A5 respectively, the first class switches include a plurality of first switch groups, the second class switches include a plurality of second switch groups, each of the first switches The group includes three first switches, and each of the second switch groups includes three second switches; wherein, The first input end of each comparator is connected to the first signal input end, the second input end is connected to the second signal input end, and the output end is connected to its corresponding preset logic circuit; the first type capacitor The first terminals are connected to the first signal input terminal, and the second terminals are respectively connected to the first reference voltage signal terminal and the second reference voltage signal terminal through the three first switches in the first switch group. or the third reference voltage signal terminal; The first terminals of the second type of capacitors are all connected to the second signal input terminal, and the second terminals are respectively connected to the first reference voltage signal terminal through three second switches in the second switch group. The second reference voltage signal terminal or the third reference voltage signal terminal. 3 . The pipelined domino structure successive approximation analog-to-digital converter according to claim 2 , wherein, in the first to n stages of sub-ADCs, the first type of capacitors include: Cs1 to Cs5 , and the second type of capacitors include: Capacitors include: Cs6~Cs10, the ratio of capacitance values of Cs1, Cs2, Cs3, Cs4 and Cs5 is 16:8:4:2:1, and the ratio of capacitance values of Cs6, Cs7, Cs8, Cs9 and Cs10 is 16:8 :4:2:1. 4 . The pipeline domino structure successive approximation analog-to-digital converter according to claim 2 , wherein the first stage sub-ADC further comprises a second module, and the second module comprises a third type capacitor, a fourth Capacitor-like, a third-type switch, and a fourth-type switch, the third-type switch including a plurality of third switch groups, the fourth-type switch including a plurality of fourth switch groups, each of the third switch groups including three third switches, each of the fourth switch groups including three fourth switches; wherein, The first terminals of the third type of capacitors are all connected to the first signal input terminal, and the second terminals are respectively connected to the first reference voltage signal terminal through three third switches in the third switch group. the second reference voltage signal terminal or the third reference voltage signal terminal; The first terminals of the fourth type of capacitors are all connected to the second signal input terminal, and the second terminals are respectively connected to the first reference voltage signal terminal through three fourth switches in the fourth switch group. The second reference voltage signal terminal or the third reference voltage signal terminal. 5 . The pipelined domino structure successive approximation analog-to-digital converter according to claim 4 , wherein, in the first stage sub-ADC, the third type of capacitors include: Cs11 to Cs15 , the second type of capacitors Including: Cs16～Cs20, the ratio of capacitance values of Cs11, Cs12, Cs13, Cs14 and Cs15 is 16:8:4:2:1, and the ratio of capacitance values of Cs16, Cs17, Cs18, Cs19 and Cs20 is 16:8: 4:2:1. 6. The pipeline domino structure successive approximation analog-to-digital converter according to claim 4, wherein the sub-ADC further comprises a calibration circuit and an output module, wherein the calibration circuit is used to calibrate the offsets of A1-A5 voltage, the output module is used to store the 5-bit quantization code generated by the sub-ADC. 7. The pipeline domino structure successive approximation analog-to-digital converter according to claim 1, further comprising a power supply signal terminal; the comparator comprises a first sub-module and a second sub-module, the first sub-module The module includes first transistors: M1-M7 and inverters: B1, B2, and the second sub-module includes second transistors: M8-M14 and inverters: B1-B4; wherein, The source of M1 is connected to the power signal terminal, the drain is connected to the source of M2, the gate is connected to the gate of M4, the gate of M2 is connected to the second signal input terminal, and the drain is connected to the drain of M4 The source of M4 is grounded, the drain of M1 and the source of M2 include a first node, the gate of M3 is connected to the second reference voltage signal terminal, the source is connected to the first node, The drain is connected to the second node, a third node is included between the drain of M4 and the drain of M2, the source of M4 is grounded, the gate of M5 is connected to the clock signal, the drain is connected to the second node, and the source is grounded , the gate of M6 is connected to the first reset signal, the drain is connected to the second node, and the source is grounded; the gate of M7 is connected to the second reset signal, the drain is connected to the second node, and the source is grounded; the input of B1 The terminal is connected to the drain of M4, and the output terminal of B1 is connected to the input terminal of B2; The source of M8 is connected to the power signal terminal, the drain is connected to the source of M9, the gate is connected to the gate of M11, the gate of M9 is connected to the second signal input terminal, and the drain is connected to the drain of M11 The source of M11 is grounded, the drain of M8 and the source of M9 include a fourth node, the gate of M10 is connected to the second reference voltage signal terminal, the source is connected to the fourth node, The drain is connected to the fifth node, a sixth node is included between the drain of M11 and the drain of M9, the source of M11 is grounded, the gate of M12 is connected to the clock signal, the drain is connected to the fifth node, and the source is grounded , the gate of M13 is connected to the first reset signal, the drain is connected to the fifth node, and the source is grounded; the gate of M14 is connected to the second reset signal, the drain is connected to the fifth node, and the source is grounded; the input of B3 The terminal is connected to the drain of M11, and the output terminal of B3 is connected to the input terminal of B4; The third node is connected to the gate of M8, and the sixth node is connected to the gate of M1. 8. pipeline domino structure successive approximation type analog-to-digital converter according to claim 7, is characterized in that, M1, M2, M3, M8, M9 and M10 are P-type field effect transistors, M4, M5, M6, M7, M11, M12, M13 and M14 are N-type super effect transistors. 9. The pipeline domino structure successive approximation analog-to-digital converter according to claim 8, wherein the calibration circuit comprises a third transistor: M15˜M25, a preset current source, an AND gate: C1 and C2, and Inverter B5; where, The gate of M15 is connected to the gate of M16, the source of M15 and the source of M16 are both connected to the power signal terminal, the drain of M15 is connected to the source of M17, the gate of M17 is grounded, and the drain is connected to M19 The drain of M19 is connected to the drain of M21, the source of M21 is grounded, the drain of M16 is connected to the source of M18, the gate of M18 is connected to the first switch signal, the drain of M18 is connected to M20 The drain of M18 and the drain of M20 include a seventh node, the seventh node is connected to the first reference voltage, the gate of M20 is connected to the second switch signal, and the source is connected to M22 The drain of M22 is connected to the ground, the gate of M22 is connected to the preset current source, the eighth node is included between the preset current source and the gate of M22, the gate of M23 and the gate of M21 are both connected to the eighth node, the drain of M23 is connected to the preset current source, and the source is grounded; The first input terminal of the comparator is connected to the second input terminal through a first switch, the third input terminal is connected to the first reference voltage, the first output terminal is connected to the first input terminal of C1, and the second input terminal is connected to the first reference voltage. The output terminal is connected to the first input terminal of C2, the second input terminal of C1 and the second input terminal of C2 are both connected to the enable signal, the gate of M24 is connected to the power signal terminal, the source of M24 is connected to the source of M25. The source is connected to the ninth node, the ninth node is connected to the second switch signal, the drain of M24 and the drain of M25 are connected to the tenth node, the tenth node is connected to the output end of C1, and the M25 The gate of C2 is grounded, and the output of C2 is connected to the input of inverter B5.

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