CN114978165A - Time-interleaved pipelined successive approximation analog-to-digital converter - Google Patents

Abstract

A time-interleaved pipelined successive approximation analog-to-digital converter comprising: the invention has sampling frequency and wide signal bandwidth above GHz, can carry on the high-speed conversion to the signal in the radio frequency system, utilize on-chip analog and digital calibration technology to solve the mismatch problem among the channels of the time interweaving analog-to-digital converter at the same time, in addition, the invention adopts the sub analog-to-digital converter of the successive approximation mixed type architecture (PSAR) of the assembly line, realize the low-power consumption design.

Description

Time Interleaving Pipeline Successive Approximation Analog-to-Digital Converter

technical field

The invention relates to a technology in the field of wireless communication, in particular to a time-interleaving pipeline successive approximation analog-to-digital converter.

Background technique

The time-interleaving analog-to-digital converter works alternately through N channels of single-core analog-to-digital converters, which can achieve a sampling rate that is difficult to achieve with a single-core analog-to-digital converter, so it is often used in high-speed occasions. The pipeline successive approximation analog-to-digital converter combines the high-speed characteristics of the pipeline ADC with the low power consumption of the successive approximation ADC, and is very suitable for the design of high-precision analog-to-digital converters in high-speed and low-power consumption. However, the channel-to-channel mismatch of the time-interleaved analog-to-digital converter, including: channel-to-channel offset mismatch, gain mismatch, and mismatch caused by different sampling time deviations, will greatly affect the performance of the time-interleaved analog-to-digital converter. Impact. At the same time, the inter-stage gain mismatch of the pipeline successive approximation hybrid analog-to-digital converter and the offset of the module circuit will also deteriorate the overall ADC performance. In addition, the inter-stage residual amplifier is also its design difficulty.

SUMMARY OF THE INVENTION

Aiming at the defects of large overall power consumption and area consumption of the input buffer of the existing high-speed time-interleaving analog-to-digital converter, the present invention proposes a time-interleaving pipeline successive approximation analog-to-digital converter, which has a sampling frequency above GHz and a wide signal The bandwidth can be used for high-speed conversion of the signals in the radio frequency system, and at the same time, the on-chip analog and digital calibration technology can be used to solve the channel-to-channel mismatch problem of the time-interleaved analog-to-digital converter. In addition, the invention adopts the pipeline successive approximation hybrid architecture (PSAR) A sub-analog-to-digital converter for low-power designs.

The present invention is achieved through the following technical solutions:

The invention relates to a time-interleaving pipeline successive approximation analog-to-digital converter, comprising: a pipeline successive approximation analog-to-digital converter unit, an input buffer unit integrated on a chip, a clock generation module unit and a digital reconstruction filter unit, wherein: an input buffer The processor unit receives the input signal of the time-interleaved pipeline successive approximation analog-to-digital converter, and provides 50 ohm impedance matching for the input; the pipeline successive approximation analog-to-digital converter unit performs analog-to-digital conversion processing according to the analog output information of the input buffer to obtain an analog The digital code value corresponding to the input signal; the clock generation module unit performs frequency division and phase processing according to the clock input signal, provides a sampling clock for the pipeline successive approximation analog-to-digital converter unit, and controls the time interleaving pipeline successively approximating the overall working sequence of the analog-to-digital converter The digital reconstruction filter unit performs interleaving and reconstruction according to the data output by the pipeline successive approximation analog-to-digital converter unit, and obtains the digital output code value of the time-interleaving pipeline successive approximation analog-to-digital converter.

The pipeline successive approximation analog-to-digital converter unit has a four-channel structure, and each channel includes: a three-stage sub-successive approximation register-type analog-to-digital converter (SAR ADC), two interstage residual amplifiers, and a bootstrap switch , a single-core digital calibration module and a digital error correction logic DEC, in which: the bootstrap switch works at the frequency of Fs/4 to sample the input, the first-stage SAR ADC quantizes the input and obtains the residual, and the residual amplifier Amplify the residual voltage to the next-stage SAR ADC; the resolutions of the three-stage SAR ADC are 5bit, 5bit and 6bit respectively, and the gain of the residual amplifier between the two stages is 8x; the single-core digital calibration module completes the comparator of the three-stage SAR ADC Offset calibration, residual amplifier offset calibration, and gain calibration of interstage residual amplifiers; DEC performs logical operations on the output of the three-stage sub-SAR ADC to obtain output data.

The interstage residual amplifier includes: a main circuit, a common mode detection circuit and a gain compensation circuit, wherein: the dynamic amplifier works in three phases, resets, amplifies and maintains to realize residual voltage amplification. The common mode detection circuit controls the output common mode and controls the amplification process of the residual amplifier, and the gain compensation circuit adjusts the amplification factor of the residual amplifier according to different working environments and PVT.

The input buffer includes: a source follower (Source Follower) architecture buffer and an on-chip negative pressure generator, wherein: the buffer provides the driving capability for the input of the analog-to-digital converter and provides 50 Ω for the previous stage. Ohmic impedance matching, the on-chip negative voltage generator provides negative voltage power supply for the input buffer to improve the linearity of the input buffer.

technical effect

The invention adopts a four-channel time interleaving pipeline successive approximation analog-to-digital converter overall architecture design method and an inter-channel mismatch calibration scheme, a pipeline successive approximation analog-to-digital converter unit and its calibration scheme, and a dynamic amplifier-based interstage residual amplifier. Gain compensation technology can achieve 12bit resolution and signal bandwidth close to GHz, and has the characteristics of low power consumption. The channel-to-channel mismatch caused by time interleaving and the non-idealities of the sub-sequential-approximation register-based analog-to-digital converter ADC itself are corrected by a digital calibration system.

Description of drawings

1 is a schematic structural diagram of a four-channel time-interleaving pipeline successive approximation analog-to-digital converter;

2 is a schematic diagram of a four-channel time interleaving pipeline successive approximation analog-to-digital converter inter-channel timing error calibration module;

Fig. 3 is the working sequence diagram of the successive approximation analog-to-digital converter of the four-channel time interleaving pipeline;

4 is a schematic structural diagram of a pipeline successive approximation analog-to-digital converter unit;

Fig. 5 is the working sequence diagram of the three-stage successive approximation register type analog-to-digital converter;

6 is a circuit diagram of a residual amplifier based on a dynamic amplifier;

Figure 7 is a circuit diagram of an on-chip integrated input buffer.

Detailed ways

As shown in FIG. 1 , the present embodiment relates to a four-channel time-interleaving pipeline successive approximation analog-to-digital converter, including: a clock generation module, a controllable delay chain, input buffers connected in sequence, and a pipeline successive approximation analog-to-digital conversion A clock generator unit, a digital reconstruction filter and a calibration module, wherein: the clock generation module and the controllable delay chain are used to form an inter-channel timing error calibration module, and the input buffer receives the signal voltage V _in and the automatic output of the four-way sub-analog-to-digital converter. A switch is connected, the clock generation module is connected to the pipeline successive approximation analog-to-digital converter unit, and the main frequency clock CLK _S of the time-interleaving successive approximation analog-to-digital converter is received, and the frequency of the main frequency clock is the sampling frequency of the time-interleaving analog-to-digital converter, The clock generation module outputs four down-converted clocks, namely CLK ₀ , CLK ₁ , CLK ₂ and CLK ₃ , their frequencies are 1/4 of the sampling frequency of the time-interleaving successive approximation analog-to-digital converter, and their phases differ by 90 °. Control the three-stage sub-sequential approximation register-type analog-to-digital converter and the bootstrap switch in the four channels in the pipeline successive approximation analog-to-digital converter unit respectively, thereby realizing four-channel time interleaving, and the three-stage sub-sequential approximation in the four channels The register-type analog-to-digital converter ADC0~3 works alternately at a speed of 1/4 of the sampling frequency of the analog-to-digital converter with a time-interleaving pipeline and outputs 12-bit data D ₀ <11:0>, D ₁ <11:0>, D ₂ <11:0>, D ₃ <11:0>, after reconstruction by the digital reconstruction filter, the uncalibrated data D _ch <11:0> is output to the calibration module, and the calibration module outputs the calibrated output Dout<11: 0>.

As shown in FIG. 2 , the inter-channel timing error calibration module includes: a clock generation module, a frequency divider and a parallel four-way controllable delay chain, wherein: the clock generation module receives the time-interleaved successive approximation analog-to-digital converter. The main frequency clock CLK _S is divided by 4 by the frequency divider after passing through the on-chip clock buffer to generate four-phase clocks such as CLK ₀ , CLK ₁ , CLK ₂ , and CLK ₃ . The four-phase clocks respectively control the three-stage sub-sequential approximation register analog-to-digital converter ADC0-3 in the four channels to sample.

Due to the deviation of parasitics, wiring and manufacturing process, the phase between the four-phase clocks will be deviated, and the accurate 1/4 phase interval cannot be achieved, resulting in the generation of timing errors.

In this embodiment, the phase interval between the four-phase times is adjusted through a controllable delay chain, and each controllable delay chain is regulated by an 8-bit digital input code value, which are Dtune0<7:0> and Dtune1<7:0> respectively. , Dtune2<7:0> and Dtune3<7:0>, so as to realize the calibration of timing errors, eliminate the harmonics caused by timing errors, and improve the linearity and spurious-free dynamic range of successive approximation analog-to-digital converters in time-interleaving pipelines .

As shown in Figure 3, it is the timing diagram of the successive approximation analog-to-digital converter of the four-channel time interleaving pipeline. CLK _S , CLK ₀ , CLK ₁ , CLK ₂ , CLK ₃ are the input signal of the clock generation module shown in FIG. 1 and the control signal of the three-stage sub-successive approximation register type analog-to-digital converter ADC in the four channels, D ₀ <11:0>, D ₁ <11:0>, D ₂ <11:0>, D ₃ <11:0> are the three-stage successive approximation register analog-to-digital converter ADC output data in four channels. [n-1], [n], [n+1]...represent the digital output code value of the input signal at the n-1, n, n+1...th sampling time. Referring to the timing diagram, CLK _S , CLK ₀ , CLK ₁ , CLK ₂ , and CLK ₃ are separated by 1/4 phase. When the CLK ₀ signal is high, the bootstrap switch of channel 0 is closed, ADC0 starts sampling, and after one sampling After the time, the sampling is over, the bootstrap switch is turned off, the first three-stage sub-sequential approximation register-type analog-to-digital converter ADC0 starts to convert, and the conversion is completed after one conversion time, and the output result D ₀ <11:0> is obtained. n cycle data. Then the second to fourth third-stage sub-sequential approximation register-type analog-to-digital converters ADC1 to 3 start sampling and conversion in sequence, and obtain D ₁ <11:0>, D ₂ <11:0>, D ₃ <11:0> The nth cycle data, and then enter the n+1th cycle, and repeat.

As shown in FIG. 4 , the three-stage sub-sequential approximation register-type analog-to-digital converter includes: three interstage residual amplifiers SAR1, SAR2 and SAR3, and two-stage residual amplifiers RA1 and RA2, wherein: the first interstage The residual amplifier SAR1 is connected to the first-stage residual amplifier RA1, the first-stage residual amplifier RA1 is connected to the second inter-stage residual amplifier SAR2, and the second inter-stage residual amplifier SAR2 is connected to the second-stage residual amplifier RA2, The second-stage residual amplifier RA2 is connected to the third inter-stage residual amplifier SAR3, and the first inter-stage residual amplifier receives the bootstrap sampling switch signals SW_p and SW_m (SamplingSwitch).

The three-stage sub-sequential-approximation register-type analog-to-digital converters are respectively a first-stage 5-bit, a second-stage 5-bit and a third-stage 6-bit SAR ADC.

In Fig. 4, φ _s is the sampling clock. CDAC_p and CDAC_m (Capacitor Digital-to-AnalogConverter) are the first-stage sampling capacitors. φ _c1 is the comparison clock of the first-level comparator, φ _c2 is the comparison clock of the second-level comparator, and φ _c3 is the comparison clock of the third-level comparator. D<15:0> is the raw output data of the 16-bit pipeline analog-to-digital converter without calibration and digital error logic, where D<15:11> is the output data of the first-stage SAR ADC, and D<10:6> is the first-stage SAR ADC output data. The output data of the second-stage SAR ADC, D<5:0> is the output data of the third-stage SAR ADC. Dout<11:0> is the actual output data after the original output data of each sub-SAR ADC has undergone offset, gain calibration and digital error correction logic DEC (Digital Error Correction).

Different from the existing pipeline successive approximation analog-to-digital converter, the device does not use a closed-loop amplifier as the inter-stage residual amplifier, but uses a dynamic amplifier as the structure of the inter-stage residual amplifier, thereby reducing power consumption and saving area. This embodiment reduces the gain variation of the dynamic amplifier under different PVT conditions through the analog gain compensation technology.

The CDAC used in this embodiment adds PN CAP and Cali DAC on the basis of the Main DAC, wherein: the Main DAC is the same as the traditional CDAC, adopts the upper plate sampling to improve the sampling speed, and adopts the split monotonic setting The method ensures that the common mode voltage of the upper plate of the CDAC remains unchanged during comparison and setting; PN Cap is used for pseudo-random PN (Pseudorandom) signal injection and gain calibration of interstage residual amplifiers. The Cali DAC is used to complete the offset calibration of the comparator and residual amplifier.

When the SAR ADC is in the sampling and ending stage, the PN Cap is in the Reset state, the lower plate of the PN Cap on CDAC_p is connected to the positive reference voltage VREFP, and the lower plate of the PN Cap on CDAC_m is connected to the negative reference voltage VREFM. When the SAR ADC ends the conversion stage and enters the residual amplification stage, the PN Cap will invert the lower plate voltage according to the input pseudo-differential random signal pn. If "pn=1", the PN Cap lower plate voltage on CDAC_p keeps the positive reference voltage unchanged, and the PN Cap lower plate voltage on CDAC_m is reversed from the negative reference voltage to the positive reference voltage; if "pn=0", the Then the PN Cap lower plate voltage under CDAC_p keeps the negative reference voltage unchanged, and the PN Cap upper plate voltage on CDAC_m is reversed from the positive reference voltage to the negative reference voltage. The injected pn signal is multiplied by the ADC output signal in the calibration module, accumulated and averaged to obtain the interstage residual amplifier gain. The Cali DAC is used to calibrate the offset of comparators and residual amplifiers. When the SAR ADC is in the sampling phase, the Cali DAC is in the reset phase, the lower plate of the Cali DAC in CDAC_p is connected to the positive reference voltage, and the lower plate of the Cali DAC in CDAC_m is connected to the negative reference voltage. When the SAR ADC is in the comparison stage, the Cali DAC is in the comparator offset calibration mode, and the lower plate of the Cali DAC is respectively connected to the positive reference voltage and the negative reference voltage according to the comparator offset calibration code to complete the comparator offset calibration. When the SARADC is in the residual amplifier stage, the lower plate of the Cali DAC is connected to the positive reference voltage and the negative reference voltage respectively according to the offset calibration code of the residual amplifier to complete the offset calibration of the residual amplifier.

As shown in Figure 5, φ _s controls the opening and closing of the bootstrap switch, which is the sampling clock, and its sampling frequency is 1/fsub. fsub is the sampling frequency of the three-stage pipeline successive ADC, and its value is 1/4Fs, and Fs is the overall sampling frequency of the time interleaving ADC. φ _c1 , φ _c2 , and φ _c3 are the comparison clocks of the comparators of the first-stage SAR ADC, the second-stage SAR ADC, and the third-stage SAR ADC, respectively. The interstage residual amplifier uses a dynamic amplifier based architecture and therefore requires a reset signal. φ _RA1 and φ _RST1 are the amplification phase and reset phase of the first-stage residual amplifier, respectively. φ _RA2 and φ _RST2 are the amplification phase and reset phase of the second-stage residual amplifier, respectively. D<15:0> is the original data output by the three-stage pipeline, among which: D<15:11> is the output data of the first stage, D<10:6> is the output data of the second stage, and D<5:0> is the output data of the second stage The third-level output data, on the timing diagram of D<15:0>, the gray shaded part is the unstable state, and the white is the stable state. Referring to the timing diagram, when the nth conversion cycle comes, φ _s is pulled high first, and enters the sampling stage of the three-stage pipeline successively approximating the ADC. After the sampling stage, φ _s is pulled low. The first-stage comparator starts to work and enters the conversion stage of the first-stage SAR ADC. The SAR logic is a 1b/1cycle architecture. After 5 comparisons, the comparison is completed, and D<15:11> changes from unstable to stable. state, the [n]th cycle conversion value of D<15:11> is obtained. At the same time, φ _RA1 is pulled high, the first-stage residual amplifier starts to work and enters the amplification stage, and the residual of the first-stage SAR ADC is The difference voltage is amplified to the second stage SAR ADC. The second-stage comparator starts to work and enters the conversion stage of the second-stage SAR ADC. After 5 comparisons, the comparison stage is completed, and D<10:6> changes from an unstable state to a stable state, obtaining D<10:6 > of the [n]th cycle transition value. At the same time, φ _RA2 is pulled high, the first-stage residual amplifier starts to work and enters the amplification stage, amplifying the residual voltage of the second-stage SAR ADC to the third-stage SAR ADC. The third-stage comparator starts to work and enters the conversion stage of the third-stage SARADC. After 6 comparisons, the comparison is completed, and D<5:0> changes from an unstable state to a stable state, and the value of D<5:0> is obtained. The [n]th cycle transition value. After timing alignment and digital calibration and DEC, the nth cycle output of Dout<11:0> is obtained. It is worth noting that the entire conversion process is pipelined, when the first stage completes the data conversion of the nth cycle and amplifies the residual voltage to the second stage and the second stage starts the data conversion of the nth cycle. , the first stage starts to receive the sampling signal of the n+1th cycle and starts to convert.

As shown in FIG. 6 , the interstage residual amplifier includes: a main body circuit, a common mode detection circuit and an analog gain compensation circuit, wherein: the common mode detection circuit outputs CMD signals to the main body circuit and the analog gain compensation circuit respectively. Among them, VIP and VIM are input differential signals, CLK_RA is residual amplifier amplification signal, CLK_RST is residual amplifier reset signal, VOP and VOM are residual amplifier differential output signals, and CMD is common mode detection output signal.

As shown in FIG. 6a , the main circuit includes: tail current control transistors M ₀ , M ₁ , input differential pair transistors M ₂ , M ₃ , connection transistors M ₄ , M ₅ for controlling the amplifier circuit and the output capacitor, and a reset pair Tubes M ₆ , M ₇ and the latter stage load capacitor _CL .

As shown in Fig. 6b, in the common mode detection circuit: C ₀ and C ₁ are used to detect the output common mode voltage of VOP and VOM, M ₈ -M ₁₈ detect the output common mode voltage and generate a CMD signal to control the residual amplifier When the output common-mode voltage reaches VCM, CMD is pulled down to the ground level, thereby turning off the residual amplifier and ending the amplification process. The reference voltage generator controls the starting voltage of the common mode detection circuit, and the output voltage of the reference voltage generator will change according to PVT (Process, Voltage, Temperature). The output voltage is raised, thereby increasing the amplification time of the residual amplifier and increasing the gain of the residual amplifier. Conversely, when PVT causes the gain of the residual amplifier to increase, the output voltage of the reference voltage generator decreases, thereby reducing the amplification time of the residual amplifier and reducing the gain of the residual amplifier, thereby keeping the gain of the residual amplifier stable. It is worth noting that the constituent circuit of the reference voltage generator is not unique, as long as it can generate an output voltage that is opposite to the variation trend of the residual amplifier body gain with PVT, it can be used as the implementation circuit of the reference voltage generator.

As shown in FIG. 7 , the input buffer according to the time interleaving pipeline successively approximates the input signal of the analog-to-digital converter, and after buffering, it is output to the four pipeline successive approximation analog-to-digital converters. The architecture includes: source-level followers M ₀ -M ₃ , coupled DC blocking circuits R ₀ -R ₃ , C ₀ -C ₃ and bootstrap switches S ₀ -S ₄ , wherein: source-level followers and coupling isolation circuits The straight circuit constitutes the main circuit, and the bootstrap switch is connected to the pipeline successively approximating the analog-to-digital converter unit.

The source-level followers M0 to M3 are relatively large in size, and provide sufficient driving capability for the output.

In the figure: VIN is the input buffer input voltage, VOUT is the input buffer output voltage, and V _b1 , V _b2 , V _b3 , and V _b4 are the four DC bias voltages of the input buffer. VDD (1.8V) is the positive supply voltage of the input buffer. VSS(-0.5V) is the negative power supply voltage of the input buffer, V _b1 , V _b2 , V _b3 , and V _b4 are generated by resistive voltage division. EN<3:0> is the enable signal of the four bias circuits. When When EN<3:0> is high, the four bias circuits output the bias voltage normally. When EN<3:0> is low, the four bias circuits are turned off, V _b1 , V _b2 , V _b3 , and V _b4 are set to VDD (1.8V), and the input buffers are turned off. V _b1 , V _b2 , V _b3 , V _b4 can be regulated by 8bit control word. Rtune0<7:0>, Rtune1<7:0>, Rtune2<7:0>, Rtune3<7:0> can respectively adjust the ratio of the resistances in the four bias circuits, thereby adjusting V _b1 , V _b2 , V _b3 , V _b4 voltage. The negative power supply voltage VSS (-0.5V) is powered by the on-chip Negative Charge Pump, which has higher integration, smaller power ripple and better performance than traditional off-chip power supply.

After specific practical experiments, under the 28nm process, the realized four-channel pipeline successive approximation analog-to-digital converter unit can reach a sampling frequency of 2GHz and a signal bandwidth of 800MHz, and the achieved signal-to-noise distortion ratio is 61.3dB. The spurious dynamic range is 73dB.

Compared with the prior art, the device realizes a high-speed and high-performance analog-to-digital converter with 2GHz sampling and 800MHz signal bandwidth, the signal-to-noise-distortion ratio reaches 61.3dB, and the spurious-free dynamic range is 73dB.

The above-mentioned specific implementation can be partially adjusted by those skilled in the art in different ways without departing from the principle and purpose of the present invention. The protection scope of the present invention is subject to the claims and is not limited by the above-mentioned specific implementation. Each implementation within the scope is bound by the present invention.

Claims (6)

1. A time-interleaved pipelined successive approximation analog-to-digital converter, comprising: the device comprises a pipeline successive approximation analog-to-digital converter unit, an on-chip integrated input buffer unit, a clock generation module unit and a digital reconstruction filter unit, wherein: the input buffer unit receives an input signal of the time-interleaved pipeline successive approximation analog-to-digital converter and provides 50-ohm impedance matching for input; the pipeline successive approximation analog-to-digital converter unit performs analog-to-digital conversion processing according to the analog output information of the input buffer to obtain a digital code value corresponding to the analog input signal; the clock generation module unit carries out frequency division and phase processing according to a clock input signal, provides a sampling clock for the pipeline successive approximation analog-to-digital converter unit and controls the overall working time sequence of the time-interleaved pipeline successive approximation analog-to-digital converter; and the digital reconstruction filter unit performs interleaving reconstruction according to the data output by the pipeline successive approximation analog-to-digital converter unit to obtain a digital output code value of the time interleaving pipeline successive approximation analog-to-digital converter.

2. The time-interleaved pipelined successive approximation analog-to-digital converter as claimed in claim 1, wherein said pipelined successive approximation analog-to-digital converter unit is of a four-channel structure, each channel comprising: three-stage sub successive approximation register analog-to-digital converter, two inter-stage residual amplifiers, a bootstrap switch, a single-core digital calibration module and a digital error correction logic DEC, wherein: the bootstrap switch works at the frequency of Fs/4 to sample the input, the first-stage SAR ADC quantizes the input and obtains a residual error, and the residual error amplifier amplifies the residual error voltage to the next-stage SAR ADC; the three-stage SAR ADC resolution ratio is 5bit, 5bit and 6bit respectively, and the gain of the two-stage interstage residual error amplifier is 8 x; the single-core digital calibration module completes the offset calibration of a comparator of the three-level SAR ADC, the offset calibration of a residual error amplifier and the gain calibration of an inter-stage residual error amplifier; and the DEC performs logic operation on the output of the three-level sub SAR ADC to obtain output data.

3. The time-interleaved pipelined successive approximation analog-to-digital converter of claim 1 wherein said inter-stage residual amplifier comprises: a body circuit, a common mode detection circuit and a gain compensation circuit, wherein: the dynamic amplifier works in three phases, and resets, amplifies and maintains to realize residual voltage amplification. The common mode detection circuit controls an output common mode and controls the amplification process of the residual error amplifier, and the gain compensation circuit adjusts the amplification factor of the residual error amplifier according to different working environments and PVT.

4. The time-interleaved pipelined successive approximation analog-to-digital converter of claim 1 wherein said input buffer comprises: a source follower architecture buffer and an on-chip negative voltage generator, wherein: the buffer provides driving capability for the input of the analog-to-digital converter and 50-ohm impedance matching for the previous stage, and the on-chip negative voltage generator provides negative voltage power supply for the input buffer, so that the linearity of the input buffer is improved.

5. The time-interleaved pipelined successive approximation analog-to-digital converter as claimed in claim 2, wherein said three-stage sub-successive approximation register-type analog-to-digital converter comprises: three inter-stage residual amplifiers SAR1, SAR2 and SAR3, two-stage residual amplifiers RA1 and RA2, wherein: the first-stage residual amplifier SAR1 is connected with a first-stage residual amplifier RA1, the first-stage residual amplifier RA1 is connected with a second-stage residual amplifier SAR2, the second-stage residual amplifier SAR2 is connected with a second-stage residual amplifier RA2, the second-stage residual amplifier RA2 is connected with a third-stage residual amplifier SAR3, and the first-stage residual amplifier receives bootstrap sampling switch signals SW _ p and SW _ m.

6. The time-interleaved pipelined successive approximation analog-to-digital converter of claim 2 or 5, wherein the three-stage sub-successive approximation register type analog-to-digital converters are a first-stage 5-bit, a second-stage 5-bit and a third-stage 6-bit SAR ADC, respectively.

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