CN113542642B - Analog-to-digital converter for locally generating reference voltage of sub-digital-to-analog converter - Google Patents

Abstract

The invention relates to the field of analog integrated circuit design, which changes the prior art that a voltage source directly provides reference voltage for a sub-digital-analog converter in an ADC structure into a mode of locally generating the reference voltage of the sub-digital-analog converter in each column of ADC, thereby avoiding crosstalk between columns of a reading circuit, reducing noise and improving precision. The invention relates to an analog-digital converter for locally generating sub-digital-analog converter reference voltage, wherein the input of each sub-digital-analog converter is connected with a digital code output by a corresponding sub-digital-analog converter, and the digital code determines the theoretical reference voltage output by the sub-digital-analog converter; the sampling capacitors and the operational amplifier form a multiplying-by-two amplifying circuit, one end of one group of sampling capacitors is connected with the input end of the operational amplifier, and the other end of the one group of sampling capacitors is connected with the actual reference voltage, namely the output of the sub-digital-to-analog converter. The invention is mainly applied to the design and manufacture occasions of the analog integrated circuit.

Description

Analog-to-digital converter that locally generates the reference voltage of the sub-digital-to-analog converter

technical field

The field of analog integrated circuit design, especially the design field of image sensor readout circuit. Specifically, it relates to a sub-digital-to-analog converter device in an analog-to-digital converter.

Background technique

The pixels of an image sensor can sense light signals and output analog electrical signals, but obtaining image information requires processing digital signals, so the Analog to Digital Converter (ADC) plays a vital role in image sensors. effect. Commonly used ADCs of image sensors are mainly divided into chip-level ADCs, column-level ADCs and pixel-level ADCs. Chip-level ADCs mean that all pixels share one ADC, which requires high working speed of ADCs and is generally used for readout of small-scale pixel arrays. Circuit; column-level ADC means that each column of pixels shares an ADC, which has relatively low speed requirements and relatively low design difficulty; pixel-level ADC refers to each pixel or several adjacent pixels integrate an ADC, pixel-level ADC The advantage is that the signal-to-noise ratio is high, and the disadvantage is that it will increase the area and power consumption of the chip, and reduce the fill factor of the pixel. There are four main types of column-level ADCs currently commonly used: single-slope ADC (Single-Slope ADC, SS-ADC), oversampling ADC (sigma-delta ADC), successive approximation ADC (Successive-Approximation ADC, SA ADC), cyclic ADC (Cyclic ADC). The working principles of the four ADCs are different, and each has its own advantages and disadvantages. Compared with other ADCs, the Cyclic ADC has the advantages of faster speed and stronger accuracy and scalability. The two-stage parallel Cyclic ADC further improves the data conversion speed. The first-stage Cyclic ADC performs high-significant-bit quantization, and the second-stage Cyclic ADC performs low-significant-bit quantization on the residual voltage of the first stage. The two-stage quantization is carried out at the same time, which improves the data conversion speed and conversion bits compared with the single-stage ADC.

A schematic diagram of the structure of the column-level Cyclic ADC is shown in FIG. 1 . Its working principle is: first, switch 1 is closed, switch 2 is open, the ADC enters the sampling state, the sample and hold circuit collects the analog voltage Vin that will be quantized, and then Vin is sent to the comparator and the precise multiplying circuit, if the comparator output High level means the most significant bit digital code is 1, if the comparator output is low level, the most significant bit digital code is 0, Vin is multiplied by two and the reference voltage is summed; then switch 1 is turned off, switch 2 is closed, and the sum is The residual voltage output by the circuit is collected by the sample and hold circuit, and is compared, multiplied by two and summed to complete the quantization of the second highest bit. Repeat the above operation on the residual voltage until the quantization of the lowest bit is completed. The column-level Cyclic ADC completes the double-amplification operation of the voltage through the switched capacitor circuit and the operational amplifier. When converting each bit of data, the reference voltage connected to the capacitor is determined according to the digital code of the previous conversion result. The schematic diagram of the connection between the multi-column Cyclic ADC and the reference voltage is shown in Figure 2. The reference voltage of the Cyclic ADC has two cases, namely the high reference voltage VR+ and the low reference voltage VR-. In the case of a large readout circuit array At the same time, the reference voltage is connected to the sampling and holding circuits of the ADCs of multiple columns, and the capacitors in the sampling and holding circuits of the ADCs of the multiple columns are charged and discharged at the same time, which will increase the noise, instability and crosstalk between the columns of the readout circuit. In order to solve the above problems, it is necessary to change the way in which the voltage source directly provides the reference voltage for the sub-digital-to-analog converters in the ADC structure in the prior art, and instead generate the reference voltage of the sub-digital-to-analog converters in each column of ADCs locally, so as to avoid reading It can reduce the crosstalk between the circuit columns, reduce the noise and improve the accuracy.

SUMMARY OF THE INVENTION

In order to overcome the deficiencies of the prior art, the present invention aims to change the way in which the voltage source directly provides the reference voltage for the sub-digital-to-analog converters in the ADC structure in the prior art, and to locally generate the sub-digital-to-analog converters of each row of ADCs. reference voltage, so as to avoid crosstalk between columns of readout circuits, reduce noise, and improve accuracy. To this end, the technical solution adopted by the present invention is to locally generate an analog-to-digital converter for the reference voltage of the sub-digital-to-analog converter, and the input of each sub-digital-to-analog converter is connected to a digital code output by a corresponding sub-analog-to-digital converter, and the digital The code determines the theoretical reference voltage output by the sub-digital-to-analog converter; the sampling capacitor and the op amp form a multiplication circuit. One end of a group of sampling capacitors is connected to the input end of the op-amp, and the other end is connected to the actual reference voltage, that is, the sub-digital-to-analog conversion. output of the device.

Capacitor 1+ and capacitor 1- are the sampling capacitors of the accurate multiplying circuit of Cyclic ADC. One end of capacitor 1+ is connected to the non-inverting input of the op amp, the other end is connected to the output 2 of the sub-digital-to-analog converter, and one end of the capacitor 1- Connect the inverting input of the op amp, and connect the other end to the output 1 of the sub-digital-to-analog converter.

The logic control circuit in the sub-analog-to-digital converter determines the magnitude of the reference voltage in the current analog-to-digital conversion cycle according to the digital code output by the sub-analog-to-digital converter, and the comparator in the sub-analog-to-digital converter determines the actual output value of the sub-analog to digital converter The relationship between the reference voltage and the theoretical reference voltage. If the voltage at the sampling end of the sampling capacitor is less than the reference voltage required for this conversion, the switch connecting the column current source and the sampling capacitor is closed, and the switch connecting the power supply ground and the sampling capacitor is disconnected. The current source charges the sampling capacitor; if the current voltage at the sampling end of the sampling capacitor is greater than the reference voltage required for this conversion, the switch connecting the power ground and the sampling capacitor is closed, the switch connecting the current source and the sampling capacitor is disconnected, and the sampling capacitor When discharging to the ground, the magnitude of the charging current and the discharging current are equal, that is, the charging and discharging speeds of the two sampling capacitors are the same, which ensures that the common mode voltage of the sampling capacitors remains stable.

The sub-digital-to-analog converter consists of a four-input comparator, logic control circuit, switches 1 to 4, power ground, current source 1, and current source 2. The input of the logic control circuit is connected to the output of the previous sub-analog-to-digital converter, and the logic The output of the control circuit is the theoretical reference voltage, which is connected to the input of the comparator; the current source 1 is connected to the output 1 of the sub-digital-analog converter through switch 1, and the power ground is also connected to the sub-digital-to-analog converter through switch 3 The output 1 of the current source 2 is connected to the output 2 of the sub-digital-analog converter through the switch 2, and the power ground is also connected to the output 2 of the sub-digital-analog converter through the switch 4; For the control of the output signal, a pair of input terminals of the four-input comparator are respectively connected to the output 1 and output 2 of the sub-digital-to-analog converter, that is, the actual digital-to-analog conversion result, and the other pair of input terminals of the four-input comparator are respectively connected to the logic control circuit Output theoretical reference voltage vref1 and reference voltage vref2.

The characteristics and beneficial effects of the present invention are:

The readout circuit described in the present invention improves the traditional Cyclic ADC, and uses a current source to charge and discharge the capacitor of the Cyclic ADC. The sub-digital-to-analog converters of each column of ADCs are independent of each other and have no interference, which can avoid the readout based on the column-parallel Cyclic ADC. When the circuit array is large, the consistency of the ADC column is reduced due to the insufficient driving capability of the reference voltage, so as to ensure that the result of the analog-to-digital conversion has a sufficiently high precision.

Description of drawings:

Figure 1 is a schematic diagram of the structure of a column-level Cyclic ADC.

FIG. 2 is a schematic diagram of the connection between the multi-column Cyclic ADC and the reference voltage.

FIG. 3 is a schematic structural diagram of the sub-digital-to-analog converter described in the present invention.

FIG. 4 is a schematic structural diagram of a Cyclic ADC employing the sub-digital-to-analog converter described in the present invention.

Detailed ways

The present invention proposes a Cyclic ADC sub-digital-to-analog converter structure that locally generates a reference voltage. The current source charges the sampling capacitors of the readout circuits in each column respectively, and stops charging when the actual reference voltage reaches the theoretical value, which can avoid The problem of poor consistency of the ADC columns caused by the insufficient driving ability of the voltage source to charge the sampling capacitors of multiple columns at the same time.

When the Cyclic ADC readout circuit array is large, the reference voltage needs to simultaneously charge and discharge the sampling capacitors of the ADC accurate multiplying circuits of each column in the process of each data conversion. In order to avoid the problem of large error in the analog-to-digital conversion result due to insufficient charge and discharge of the reference voltage to the capacitor, the existing technology uses a voltage source to generate The reference voltage method is changed to locally generated reference voltage by the current source. The schematic diagram of its working principle is shown in Figure 3, and the schematic diagram of the Cyclic ADC structure using the sub-digital-to-analog converter shown in Figure 3 is shown in Figure 4. Capacitor 1 The + and capacitor 1- are the sampling capacitors of the accurate multiplying circuit of the Cyclic ADC. One end of the capacitor 1+ is connected to the non-inverting input of the op amp, the other end is connected to the output 2 of the sub-digital-to-analog converter, and one end of the capacitor 1- is connected to the op amp. The inverting input terminal of the amplifier, and the other terminal is connected to the output 1 of the sub-digital-to-analog converter. The working process of the sub-digital-to-analog converter is as follows: the logic control circuit determines the reference voltage in the current analog-to-digital conversion cycle according to the digital code output by the sub-analog-to-digital converter; the comparator determines the actual reference voltage output by the sub-digital-to-analog converter and The size relationship of the theoretical reference voltage, the four input terminals of the four-input comparator are respectively connected to the voltages of the two sampling capacitor sampling terminals, that is, the actual reference voltage and the two theoretical reference voltages output by the logic control circuit. When the voltage difference between the two sampling capacitors reaches When the difference between the two theoretical reference voltages is reached, the output level of the comparator is inverted, and the inversion level controls all switches to turn off; if the voltage at the sampling end of the sampling capacitor is less than the reference voltage required for this conversion, the column current is connected The switch between the source and the sampling capacitor is closed, the switch connecting the power ground and the sampling capacitor is disconnected, and the sampling capacitor is charged by the current source; if the current voltage at the sampling end of the sampling capacitor is greater than the reference voltage required for this conversion, connect the power ground The switch of the sampling capacitor is closed, the switch connecting the current source and the sampling capacitor is disconnected, the sampling capacitor is discharged to the ground, and the charging current and the discharging current are equal in magnitude, that is, the charging and discharging speeds of the two sampling capacitors are the same, which ensures the actual reference voltage. The common mode value remains stable. This method of locally generating the reference voltage does not require the voltage source to participate in the dynamic process of charging and discharging the capacitor, and does not generate the coupling effect between the ADC columns.

The structure shown in FIG. 3 uses a four-input comparator, which has the advantage that only one comparator is required for each column readout circuit, and the layout area is small. Two two-input comparators can also be used to replace the four-input comparator, respectively The sampling terminals of the two sampling capacitors are compared to the ground voltage and the single-ended reference voltage. The power consumption of two two-input comparators is similar to that of a four-input comparator. The advantage of two-input comparators is that they do not require the same size. Charge and discharge current, the working principle is simple.

First, the devices or modules connected to the input and output terminals of the sub-digital-to-analog converters are described: the input of each sub-digital-to-analog converter is connected to a digital code output by the corresponding sub-analog-to-digital converter, and the digital code determines the sub-digital-to-analog converter. The theoretical reference voltage of the output; in the Cyclic ADC, the sampling capacitor and the op amp form a multiplier-two amplifier circuit. When the Cyclic ADC is working, one end of a set of sampling capacitors is connected to the input end of the op amp, and the other end is connected to the actual reference voltage, that is, the number of sub-units. output of the analog converter. Next, the internal structure and working principle of the sub-digital-to-analog converter will be explained: the sub-digital-to-analog converter is composed of a four-input comparator, a logic control circuit, switches 1 to 4, a power ground, a current source 1, and a current source 2. The logic control The input of the circuit is connected to the output of the sub-analog-to-digital converter of the previous stage, and the output of the logic control circuit is the theoretical reference voltage, which is connected to the input end of the comparator; the current source 1 is connected to the output of the sub-digital-to-analog converter through the switch 1 1. The power ground is also connected to the output 1 of the sub D/A converter through switch 3, the current source 2 is connected to the output 2 of the sub D/A converter through switch 2, and the power ground is also connected to the sub D/A converter through switch 4. Output 2; the on-off of switches 1 to 4 is controlled by the output signal of the four-input comparator. A pair of input terminals of the four-input comparator are respectively connected to the output 1 and output 2 of the sub-digital-to-analog converter, that is, the actual digital-to-analog conversion result, The other pair of input terminals of the four-input comparator are respectively connected to the theoretical reference voltage vref1 and the reference voltage vref2 output by the logic control circuit. The four-input comparator compares the theoretical value and the actual value of the reference voltage. When the actual reference voltage is less than the theoretical reference voltage When the switch connected to the current source is turned on, the sampling capacitor of the latter-stage multiplying amplifier circuit is charged. When the actual reference voltage is greater than the theoretical reference voltage, the switch connected to the power supply ground is turned on to discharge the sampling capacitor. The charging current and the discharging current are equal in size, that is, the charging and discharging speeds of the two sampling capacitors are the same, so that the common mode value of the actual reference voltage output by the sub-digital-to-analog converter can be kept stable.

The content represented in FIG. 1 is a schematic diagram of the overall structure of the Cyclic ADC, illustrating the main modules of the Cyclic ADC and the connection mode between the modules. The present invention proposes an innovative structure of the neutron digital-to-analog converter in FIG. 1 .

The content represented in Figure 2: The reference voltage VR+ and the reference voltage VR- are commonly connected to the multi-column Cyclic ADC during operation. Since the sampling capacitor of the Cyclic ADC is directly connected to the reference voltage, it is equivalent to the reference voltage to multiple parallel capacitors. Charging and discharging, the driving ability of the reference voltage is limited, which will lead to a decrease in the accuracy of the Cyclic ADC.

The content represented by FIG. 3: the specific structure of the sub-digital-to-analog converter proposed by the present invention in the dashed-line frame, and the input and output terminals of the sub-digital-to-analog converter outside the dashed-line frame.

The working principle of the present invention: the Cyclic ADC using the sub-digital-to-analog converter proposed by the present invention is shown in FIG. 4 , the capacitor 1+ and the capacitor 1- are the sampling capacitors of the accurate multiplying circuit of the Cyclic ADC, wherein one end of the capacitor 1+ Connect the non-inverting input of the op amp, the other end is connected to the output 2 of the sub-digital-to-analog converter, one end of the capacitor 1- is connected to the inverting input of the op-amp, and the other end is connected to the output 1 of the sub-digital-to-analog converter. The working process of the sub-digital-to-analog converter is: the logic control circuit determines the size of the reference voltage in the current analog-to-digital conversion cycle according to the digital code output by the sub-analog-to-digital converter, and the comparator determines the actual reference voltage output by the sub-digital-to-analog converter. It is related to the theoretical reference voltage. If the voltage at the sampling end of the sampling capacitor is less than the reference voltage required for this conversion, the switch connecting the column current source and the sampling capacitor is closed, the switch connecting the power ground and the sampling capacitor is disconnected, and the current source Charge the sampling capacitor; if the current voltage at the sampling end of the sampling capacitor is greater than the reference voltage required for this conversion, the switch connecting the power ground and the sampling capacitor is closed, the switch connecting the current source and the sampling capacitor is disconnected, and the sampling capacitor is connected to ground The magnitudes of discharge, charge current and discharge current are equal, that is, the charge and discharge speeds of the two sampling capacitors are the same, which ensures that the common mode voltage of the sampling capacitors remains stable. This method of locally generating the reference voltage does not require the voltage source to participate in the dynamic process of charging and discharging the capacitor, and does not generate the coupling effect between the ADC columns.

In order to more intuitively express the implementation conditions, advantages, etc. of the present invention, the embodiments of the present invention are described below with reference to examples. The readout circuit described in the present invention is applied to a TOF image sensor with a pixel array of 1920 columns and 1080 rows, the frame frequency is 300FPS (Frames per Second, the number of frames), the quantization bit is 10 bits, and the clock frequency is 250MHz ( Megahertz), Cyclic ADC using RSD (Redundant Signed Digit, redundant bit) encoding, the single-ended input voltage range of Cyclic ADC is 1.05V (volts) ~ 2.25V, the input voltage common mode value is 1.65V, the ADC quantization range For -1.2V～+1.2V, the reference voltages of Cyclic ADC are respectively high reference voltage VR+=2.25V, low reference voltage VR-=1.05V. The op amp in the Cyclic ADC adopts a folded cascode op amp structure, and the comparator in the sub-analog-to-digital converter adopts a dynamic latch comparator structure, and the threshold voltage of the comparator is +0.3V and -0.3V. The data conversion time of the readout circuit of each column is 3us (microseconds), and the conversion time of each bit of the Cyclic ADC is 300ns (nanoseconds). Then the difference between the input voltages is 0.7V. The structure of Cyclic ADC is shown in Figure 4. The voltages collected by capacitor 1+, capacitor 1-, capacitor 2+, and capacitor 2- are respectively 2V and 1.3V within 0-300ns. The 1.5-bit digital code is binary 10; within 300ns to 600ns, the Cyclic ADC enters the next quantization cycle. At this time, capacitor 2+ and capacitor 2- collect the output voltage of the op amp, and the two plates of capacitor 1+ and capacitor 1- Connect the op amp input terminal and the reference voltage respectively. According to the digital code obtained in the last quantization cycle, the reference voltages that need to be connected to capacitor 1+ and capacitor 1- are 2.25V and 1.05V, respectively. The logic circuit controls capacitor 1+ to connect to the column current source. For charging, capacitor 1- is connected to the power supply ground for discharging. The charging and discharging speed of capacitor 1+ and capacitor 1- are the same, and the common mode voltage is maintained at 1.65V. When the voltage of capacitor 1+ and capacitor 1- respectively reach 2.25V after charging and discharging and 1.05V, the output level of the four-input comparator is inverted, all switches connected to the column current source and ground are turned off, and the charging and discharging of the sampling capacitor is stopped. The output voltage of the op amp is multiplied by two and subtracted by 1.2V. is 0.2V, and the ground voltages of capacitor 2+ and capacitor 2- are 1.75V and 1.55V respectively; within the time period of 600ns to 900ns, the two groups of sampling capacitors, capacitor 1+, capacitor 1-, capacitor 2+, and capacitor 2- The positions are interchanged. At this time, capacitor 1+ and capacitor 1- collect the output voltage of the op amp. Capacitor 2+ and capacitor 2- are connected to the input terminal of the op amp and the reference voltage. Since -0.3V<0.2V<0.3V, capacitor 2 The reference voltages to be connected to + and capacitor 2- are both 1.65V. At this time, capacitor 2+ is connected to the power supply ground for discharging, and capacitor 2- is connected to the column current source for charging. The charge and discharge speeds of capacitor 1+ and capacitor 1- are the same. The mode voltage is maintained at 1.65V. When the voltage of capacitor 1+ and capacitor 1- reaches 1.65V after charging and discharging, the output level of the four-input comparator is reversed, and all switches connected to the column current source and ground are turned off, and the pairing is stopped. The sampling capacitor is charged and discharged, and the output voltage of the op amp is multiplied by two and subtracted from the 0V reference voltage to become 0.4V; after that, the op amp circuit repeats the process of multiplying, amplifying, and comparing the residual voltage output by the op amp until the 10-bit quantization is completed. until. During the conversion process, the sampling capacitor of the Cyclic ADC is charged by the column-level current source. The charging time of the column-level current source is controlled by the comparator according to the voltage across the capacitor and the reference voltage that should be connected for this conversion. The reference voltage of each column ADC Local generation, and the columns are independent of each other, which avoids the coupling and crosstalk problems caused by the reference voltage shared by all the rows and the insufficient reference voltage driving capability, and ensures the high precision of the readout circuit.

The above are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included in the protection of the present invention. within the range.

Claims (3)

1. An analog-to-digital converter for locally generating a reference voltage of a sub-digital-to-analog converter is characterized in that the analog-to-digital converter is realized by using a Cyclic ADC structure comprising the sub-digital-to-analog converter: the input of each sub-digital-to-analog converter is connected with a digital code output by a corresponding sub-digital-to-analog converter, and the digital code determines the theoretical reference voltage output by the sub-digital-to-analog converter; the sampling capacitors and the operational amplifier form a multiplying-by-two amplifying circuit, one end of one group of sampling capacitors is connected with the input end of the operational amplifier, and the other end of the one group of sampling capacitors is connected with the actual reference voltage, namely the output of the sub-digital-to-analog converter; the sub-digital-to-analog converter is composed of a four-input comparator, a logic control circuit, switches 1-4, a power ground, a current source 1 and a current source 2, wherein the input of the logic control circuit is connected with the output of the preceding stage sub-analog-to-digital converter, the output of the logic control circuit is a theoretical reference voltage, and the theoretical reference voltage is connected with the input end of the comparator; the current source 1 is connected to the output 1 of the sub-digital-to-analog converter through the switch 1, and the power ground is also connected to the output 1 of the sub-digital-to-analog converter through the switch 3, the current source 2 is connected to the output 2 of the sub-digital-to-analog converter through the switch 2, and the power ground is also connected to the output 2 of the sub-digital-to-analog converter through the switch 4; the on-off of the switches 1-4 is controlled by the output signal of the four-input comparator, one pair of input ends of the four-input comparator are respectively connected with the output 1 and the output 2 of the sub-digital-to-analog converter, namely the actual digital-to-analog conversion result, the other pair of input ends of the four-input comparator are respectively connected with the theoretical reference voltage vref1 and the reference voltage vref2 output by the logic control circuit, the four-input comparator compares the theoretical value and the actual value of the reference voltage, when the actual reference voltage is smaller than the theoretical reference voltage, the switch connected with the current source is conducted, the sampling capacitor of the second-stage multiplying amplifying circuit is charged, when the actual reference voltage is larger than the theoretical reference voltage, the switch connected with the power ground is conducted, the sampling capacitor is discharged, the magnitudes of the charging current and the discharging current are equal, namely, the charging and discharging speeds of the two sampling capacitors are the same.

2. The analog-to-digital converter for locally generating a reference voltage of a sub-digital-to-analog converter as claimed in claim 1, wherein the capacitor 1+ and the capacitor 1-are sampling capacitors of a precise multiplication-by-two circuit of a Cyclic ADC, wherein one end of the capacitor 1+ is connected to a non-inverting input terminal of the operational amplifier, the other end is connected to an output 2 of the sub-digital-to-analog converter, one end of the capacitor 1-is connected to an inverting input terminal of the operational amplifier, and the other end is connected to an output 1 of the sub-digital-to-analog converter.

3. The analog-to-digital converter for locally generating reference voltages of sub-digital-to-analog converters according to claim 1, wherein a logic control circuit in the sub-analog-to-digital converter determines the magnitude of the reference voltage in the current analog-to-digital conversion period according to the digital code output by the sub-analog-to-digital converter, a comparator in the sub-analog-to-digital converter determines the magnitude relation between the actual reference voltage and the theoretical reference voltage output by the sub-digital-to-analog converter, if the voltage at the sampling end of the sampling capacitor is less than the reference voltage required by the conversion, a switch connecting the column current source and the sampling capacitor is closed, a switch connecting the power ground and the sampling capacitor is opened, and the sampling capacitor is charged by the current source; if the current voltage of the sampling end of the sampling capacitor is larger than the reference voltage required by the conversion, the switch connecting the ground of the power supply and the sampling capacitor is closed, the switch connecting the current source and the sampling capacitor is disconnected, the sampling capacitor discharges to the ground, the charging current and the discharging current are equal, namely the charging and discharging speeds of the two sampling capacitors are the same, and the common-mode voltage of the sampling capacitors is guaranteed to be kept stable.

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