CN116314513A - Light-emitting diode epitaxial wafer and preparation method thereof - Google Patents

Abstract

The invention relates to the field of semiconductor technology, and specifically discloses a light-emitting diode epitaxial wafer and a preparation method thereof, including a substrate, on which a nucleation layer, an intrinsic GaN layer, an N-type semiconductor layer, and an electron guiding layer are sequentially arranged along the epitaxial direction. layer, a multi-quantum well layer, an electron blocking layer, and a P-type semiconductor layer; the electron guiding layer includes a first electron storage layer, a second electron intercepting layer, and a third electron expansion layer arranged in sequence along the epitaxial direction; the second The forbidden band width of the electron intercepting layer>the maximum forbidden band width of the third electron expansion layer>the forbidden band width of the first electron storage layer. The epitaxial wafer of the invention has uniform distribution of luminous wavelength and luminous brightness, and good antistatic ability.

Description

Light-emitting diode epitaxial wafer and preparation method thereof

technical field

The invention relates to the technical field of semiconductors, in particular to a light-emitting diode epitaxial wafer and a preparation method thereof.

Background technique

At present, GaN-based light-emitting diodes have been widely used in the fields of solid-state lighting and display, attracting more and more people's attention. GaN-based light-emitting diodes have been industrialized and used in backlights, lighting, and landscape lights.

A traditional GaN-based light-emitting diode epitaxial wafer includes: a substrate, and a nucleation layer, an intrinsic GaN layer, an N-type semiconductor layer, a multi-quantum well layer, an electron blocking layer, and a P-type semiconductor layer grown sequentially on the substrate. The disadvantage of this structure is that because the electron mobility is much larger than that of holes, the electron expansion ability is poor, resulting in the carriers not being able to spread well in the multi-quantum well region, resulting in poor uniformity of luminous wavelength and brightness. Moreover, the carrier expansion is not good, which will lead to the deterioration of the antistatic ability of the light emitting diode.

Contents of the invention

The purpose of the present invention is to provide a light-emitting diode epitaxial wafer with uniform distribution of luminous wavelength and luminous brightness and good antistatic ability and its preparation method in view of the existing technical status.

To achieve the above object, the present invention adopts the following technical solutions:

The invention provides a light-emitting diode epitaxial wafer, including a substrate, on which a nucleation layer, an intrinsic GaN layer, an N-type semiconductor layer, an electron guiding layer, a multi-quantum well layer, and an electron blocking layer are sequentially arranged along the epitaxial direction , P-type semiconductor layer;

The electron guide layer includes a first electron storage layer, a second electron interception layer and a third electron expansion layer sequentially arranged along the epitaxial direction;

The forbidden band width of the second electron intercepting layer>the maximum forbidden band width of the third electron expanding layer>the forbidden band width of the first electron storage layer.

In some embodiments, the first electron storage layer includes a first sublayer, a second sublayer, and a third sublayer stacked periodically, and the bandgap Eg ₃ of the third sublayer is greater than the second sublayer The band gap Eg ₂ of the second electron intercepting layer is greater than the band gap Eg ₁ of the first sublayer, and Eg ₃ /Eg ₁ >3, and the band gap of the second electron intercepting layer is >1.5×Eg ₃ .

In some embodiments, the first electron storage layer is In _x N _1-x /In _y Ga _1-y N/GaN layer, and the second electron interception layer is B _m Ga _1-m N/B _n N _1-n layer, the third electron expansion layer is an In _a Ga _1-a N/N type B _b Ga _1-b N layer.

In some embodiments, in the first electron storage layer, 0.6≥x≥0.4, 0.3≥y≥0.1.

In some embodiments, the first electron storage layer includes periodically stacked In _x N _1-x sub-layers, In _y Ga _1-y N sub-layers and GaN sub-layers, wherein a single In _x N _1-x The thickness of the sublayer is 1nm~5nm, the thickness of a single In _y Ga _1-y N sublayer is 1nm~5nm, the thickness of a single GaN sublayer is 6nm~10nm, and the number of periods of the first electron storage layer is 2 ~6, the growth temperature is 800℃~900℃.

In some embodiments, in the second electron intercepting layer, 0.3≥m≥0.1, 0.5≥n≥0.3.

In some embodiments, the second electron intercepting layer includes periodically stacked B _m Ga _1-m N sub-layers and B _n N _1-n sub-layers, wherein a single B _m Ga _1-m N sub-layer The thickness is 6nm-10nm, the thickness of a single B _n N _1-n sublayer is 2nm-5nm, the number of periods of the second electron intercepting layer is 2-6, and the growth temperature is 1000°C-1100°C.

In some embodiments, in the third electron expansion layer, 0.3≥a≥0.1, 0.3≥b≥0.1, and the doping concentration of Si is 1×10 ¹⁶ cm ⁻³ to 1×10 ¹⁷ cm ⁻³ .

In some embodiments, the third electron expansion layer includes periodically stacked In _a Ga _1-a N sublayers and N-type B _b Ga _1-b N sublayers, wherein a single In _a Ga _1-a N The thickness of the sublayer is 1nm~10nm, the thickness of a single N-type B _b Ga _1-b N sublayer is 10nm~20nm, and the growth temperature of the third electron expansion layer is 900°C~1000°C.

The present invention also provides a method for preparing a light-emitting diode epitaxial wafer, comprising:

provide the substrate;

sequentially depositing a nucleation layer, an intrinsic GaN layer, an N-type semiconductor layer, an electron guiding layer, a multiple quantum well layer, an electron blocking layer, and a P-type semiconductor layer on the substrate;

The electron guide layer includes a first electron storage layer, a second electron interception layer and a third electron expansion layer sequentially arranged along the epitaxial direction;

The forbidden band width of the second electron intercepting layer>the maximum forbidden band width of the third electron expanding layer>the forbidden band width of the first electron storage layer.

The beneficial effects of the present invention are:

In the present invention, an electron guiding layer is provided between the N-type semiconductor layer and the multi-quantum well layer, and in the electron guiding layer, firstly, a first electron storage layer is provided for storing electrons generated from the N-type semiconductor layer, and secondly , using the second electron interception layer whose bandgap width is higher than the first electron storage layer, forms an energy level barrier, intercepts electrons, and forces the electron movement speed to slow down. Since the mobility across the second electron interception layer itself is greatly reduced, electrons The expansion itself will be strengthened, and at the same time, through the third electron expansion layer whose bandgap width is higher than the first electron storage layer and lower than the second electron interception layer, electrons are further expanded, thereby passing through the first electron storage layer, the second The combined effect of the electron intercepting layer and the third electron expansion layer guides the electrons, reduces the electron mobility, increases the expansion ability of the electrons in the multi-quantum well region, and then effectively improves the antistatic ability, and the distribution of the luminous wavelength and luminous brightness is more accurate. Uniform, at the same time, higher luminous efficiency.

Description of drawings

FIG. 1 is a schematic structural view of a light-emitting diode epitaxial wafer of the present invention.

Fig. 2 is a schematic diagram of the structure of the electron guiding layer of the present invention.

FIG. 3 is a schematic structural diagram of the first electron storage layer of the present invention.

Fig. 4 is a schematic structural diagram of the second electron intercepting layer of the present invention.

FIG. 5 is a schematic structural diagram of the third electron expansion layer of the present invention.

Fig. 6 is a flow chart of a method for preparing a light-emitting diode epitaxial wafer of the present invention.

Detailed ways

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below.

Referring to Fig. 1, the present invention discloses a light-emitting diode epitaxial wafer, including a substrate 1, on which a nucleation layer 2, an intrinsic GaN layer 3, an N-type semiconductor layer 4, and an electron guiding layer are sequentially arranged along the epitaxial direction. 5. Multiple quantum well layer 6, electron blocking layer 7, P-type semiconductor layer 8;

The electron guide layer 5 includes a first electron storage layer 51, a second electron interception layer 52 and a third electron expansion layer 53 arranged in sequence along the epitaxial direction;

The forbidden band width of the second electron intercepting layer 52 >the maximum forbidden band width of the third electron expanding layer 53 >the forbidden band width of the first electron storage layer 51 .

In the present invention, an electron guiding layer 5 is set between the N-type semiconductor layer 4 and the multi-quantum well layer 6, and in the electron guiding layer 5, at first, a first electron storage layer 51 is set for storing electrons from the N-type semiconductor layer. 4. The generated electrons, secondly, use the second electron interception layer 52 whose band gap is higher than that of the first electron storage layer 51 to form an energy level barrier to intercept the electrons and force the electrons to move at a slower rate. The mobility of layer 52 itself is greatly reduced, and the expansion of electrons will be strengthened. At the same time, through the third electron expansion layer 53 whose maximum band gap is higher than the first electron storage layer 51 and lower than the second electron interception layer 52, further expansion The electrons are thus guided by the joint action of the first electron storage layer 51, the second electron interception layer 52, and the third electron expansion layer 53, so that the electron mobility is reduced, and the expansion ability of the electrons in the multi-quantum well region is increased. , and then effectively improve the antistatic ability, the distribution of luminous wavelength and luminous brightness is more uniform, and at the same time, the luminous efficiency is higher.

Wherein, the first electron storage layer 51 includes a first sub-layer, a second sub-layer and a third sub-layer stacked periodically, and the band gap Eg ₃ of the third sub-layer > the band gap Eg ₂ of the second sub-layer > The forbidden band of the first sublayer is Eg ₁ , and Eg ₃ /Eg ₁ >3, and the forbidden band of the second electron intercepting layer 52 is >1.5×Eg ₃ .

In the present invention, in the first electron storage layer 51, the first sublayer with a relatively lower forbidden band width and the third sublayer with a much higher forbidden band width than the first sublayer are provided, and the first sublayer and the second sublayer The second sublayer with a forbidden band width between the first sublayer and the third sublayer is arranged between the three sublayers, thereby forming an "energy band trap" in the first electron storage layer 51, and passing through the "energy band trap" Electrons generated from the N-type semiconductor layer 4 are stored.

At the same time, the band gap of the second electron intercepting layer 52 is much higher than that of the third sublayer, ensuring that the band gap of the second electron intercepting layer 52 is much higher than that of the first electron storage layer 51, thereby forming an energy level barrier, wherein, Eg ₃ /Eg ₁ (the ratio between the band gap Eg ₃ of the third sublayer and the band gap Eg ₁ of the first sublayer) cannot be too low, and too low Eg ₃ /Eg ₁ is not conducive to the formation of "band traps"", it is difficult to store electrons, and if Eg ₃ /Eg ₁ is too high, electrons are difficult to cross the third sublayer, and the ratio of the band gap width of the second electron intercepting layer 52 to the band gap width between the third sublayer should not be too low, otherwise It is not conducive to forming a sufficient gap between the first electron storage layer 51 and the second electron interception layer 52 , and the second electron interception layer 52 is difficult to form an energy level barrier.

Referring to Fig. 2, wherein, the first electron storage layer 51 is In _x N _1-x /In _y Ga _1-y N/GaN layer, and the second electron interception layer 52 is B _m Ga _1-m N/B _n N _1-n layer, the third electron expansion layer 53 is an In _a Ga _1-a N/N type B _b Ga _1-b N layer.

In the present invention, the first electron storage layer 51 is an In _x N _1-x /In _y Ga _1-y N/GaN layer, wherein the In _x N _1-x sublayer 511 is the first sublayer, and the In _y Ga _{1 -y} N sublayer 512 is the second sublayer, GaN sublayer 513 is the third sublayer, In _x N _1-x sublayer 511 has a band gap of about 0.7 eV, and GaN sub layer 513 has a band gap of about 3.4eV, thereby forming an “energy band trap” in the first electron storage layer 51 to store electrons generated from the N-type semiconductor layer 4 .

In addition, the In _x N _1-x sublayer 511 and the In _y Ga _1-y N sublayer 512 introduce In components to reduce the barrier height, thereby forming a potential barrier difference with the GaN sublayer 513. In addition, the In _x N _{1 -} After the x sublayer 511 and the In _y Ga _1-y N sublayer 512, the GaN sublayer 513 is introduced, and the In _x N _1-x sublayer 511 and the In _y Ga _1-y N sublayer 512 can also be repaired during the growth process Defects generated by low temperature and high doping In components.

Secondly, in the second electron intercepting layer 52, the band gap of the BN layer is about 6.4eV, which is much higher than the band gap of the first electron storage layer 51, and the energy level of this layer is much higher than that of the first electron storage layer The energy level of 51 forms an energy level barrier, which forcibly slows down the electron movement rate. At the same time, due to the small boron atom and the better lattice matching of B _m Ga _1-m N/B _n N _1-n atoms, Therefore, a high-quality crystal lattice can be formed in this layer, and defects generated by the low-temperature high-doped In component of the first electron storage layer 51 can be repaired.

The third electron expansion layer 53 is an In _a Ga _1-a N/N type B _b Ga _1-b N layer. On the one hand, because the maximum band gap of this layer is higher than that of the first electron storage layer 51 and lower than that of the first electron storage layer 51 The second electron interception layer 52, the energy level is between the first electron storage layer 51 and the second electron interception layer 52, the mobility across the second electron interception layer 52 itself is greatly reduced, and the expansion of electrons itself will be strengthened. Secondly, In The lattice mismatch between _a Ga _1-a N and N-type B _b Ga _1-b N materials is serious, and the repeated stacked heterostructure generates two-dimensional electron gas, which increases the expansion of carriers, and B _b Ga The incorporation of low N-type doping in _1-b N materials reduces the bulk resistance of the material and enables better electron spreading.

Thus, through the joint cooperation of the first electron storage layer 51, the second electron interception layer 52 and the third electron expansion layer 53, electrons are guided, thereby reducing electron mobility and increasing the balance of electron-hole pairs in the multi-quantum well region , increasing the expansion ability of electrons, thereby effectively improving the antistatic ability, the distribution of luminous wavelength and luminous brightness is more uniform, and the luminous efficiency is higher.

Wherein, in the first electron storage layer 51, 0.6≥x≥0.4, 0.3≥y≥0.1, for example, x is 0.4, 0.5 or 0.6, but not limited thereto, when x is too large, it may be caused by In group Too much content leads to poor lattice quality. When x is too small, that is, the In composition is too small, it is difficult to form a potential barrier difference with the GaN sublayer 513, and it is difficult to store enough electrons; for example, y is 0.1, 0.2 Or 0.3, but not limited thereto, when y is too large, defects may increase due to continuous high In composition, and the crystal quality may deteriorate; when y is too small, electrons cannot be stored effectively.

Referring to FIG. 3 , the first electron storage layer 51 includes periodically stacked In _x N _1-x sub-layers 511, In _y Ga _{1- y} N sub-layers 512 and GaN sub-layers 513, wherein a single In _x The thickness of the N _1-x sublayer 511 is 1nm~5nm, the thickness of a single In _y Ga _1-y N sublayer 512 is 1nm~5nm, the thickness of a single GaN sublayer 513 is 6nm~10nm, the first electron storage layer 51 The number of cycles is 2~6, and the growth temperature is 800°C~900°C. Preferably, the thickness of a single GaN sublayer 513 is 8nm~10nm, and the GaN sublayer 513 is thicker, which is more conducive to repairing In _x N _1-x Defects generated by sub-layer 511 and In _y Ga _1-y N sub-layer 512 caused by low temperature and high doping of In components, for example, the growth temperature is 800°C, 830°C, 860°C or 900°C, but not limited thereto, The growth temperature should not be too high, as the growth temperature that is too high will easily cause the diffusion of the In component, and the growth temperature should not be too low, as the growth temperature that is too low will affect the incorporation of the In component.

Wherein, in the second electron intercepting layer 52, 0.3≥m≥0.1, 0.5≥n≥0.3, for example, m is 0.1, 0.2 or 0.3, but not limited thereto, within this range, both B _m Ga _{The 1-m} N sublayer 521 and the B _n N _1-n sublayer 522 have good lattice matching, and ensure that no cracks are generated; for example, n is 0.3, 0.4 or 0.5, but not limited thereto, when When n>0.5, it is easy to produce cracks, resulting in a decrease in lattice quality, and when n<0.3, the electron interception effect is weakened.

4, wherein the second electron intercepting layer 52 includes periodically stacked B _m Ga _1-m N sub-layers 521 and B _n N _1-n sub-layers 522, wherein a single B _m Ga _1-m N The thickness of the sublayer 521 is 6nm~10nm, the thickness of a single B _n N _1-n sublayer 522 is 2nm~5nm, the number of cycles of the second electron intercepting layer 52 is 2~6, and the growth temperature is 1000°C~1100°C. °C, for example, the growth temperature is 1000 °C, 1030 °C, 1080 °C or 1100 °C, but not limited thereto, a higher growth temperature is conducive to improving the quality of the crystal lattice, better repairing the first electron storage layer 51 with low temperature and high In defects caused by components.

Wherein, in the third electron expansion layer 53, 0.3≥a≥0.1, 0.3≥b≥0.1, the doping concentration of Si is 1×10 ¹⁶ cm ^-3 ~1×10 ¹⁷ cm ^-3 , for example, a is 0.1, 0.2 or 0.3, but not limited thereto, when a is too large, the In composition is too much, and the quality of the crystal lattice is easily reduced; when a is too small, the In composition is too small, and it is difficult to form a potential with the second electron intercepting layer 52. barrier difference, b is 0.1, 0.2 or 0.3, but not limited thereto, when b is too large, cracks are likely to occur, resulting in a decrease in lattice quality; when b is too small, it is difficult to form a potential barrier difference with the first electron storage layer 51, The doping concentration of Si is 1×10 ¹⁶ cm ^-3 , 3×10 ¹⁶ cm ^-3 , 5×10 ¹⁶ cm ^-3 , 8×10 ¹⁶ cm ^-3 or 1×10 ¹⁷ cm ^-3 , but not limited thereto , through the incorporation of low N-type doped Si, the bulk resistance of the material is reduced, making the electron expansion better.

5, wherein the third electron expansion layer 53 includes periodically stacked In _a Ga _1-a N sub-layers 531 and N-type B _b Ga _1-b N sub-layers, wherein a single In _a Ga _1-a The thickness of _{the a} N sublayer 531 is 1nm~10nm, the thickness of a single N-type _{BbGa1 -bN} sublayer is 10nm~20nm, the growth temperature of the third electron expansion layer 53 is 900°C~1000°C, preferably, The thickness of a single N-type B _b Ga _1-b N sublayer is 15nm~20nm. By setting the thickness and growth temperature of each sublayer, it can not only ensure the incorporation of In components, but also ensure better lattice quality. , to block the defects at the bottom layer, and prevent the defects from extending to the multi-quantum well layer 6 to cause non-radiative recombination.

Among them, the thickness of the nucleation layer 2 is 20nm~100nm, the thickness of the intrinsic GaN layer 3 is 300nm~800nm, the thickness of the N-type semiconductor layer 4 is 1μm~3μm, and the thickness of the multiple quantum well layer 6 of a single period is 2nm~ 5nm, the thickness of the electron blocking layer 7 of a single period is 20nm~100nm, and the thickness of the P-type semiconductor layer 8 is 200nm~300nm.

Referring to Figure 6, the present invention also discloses a method for preparing a light-emitting diode epitaxial wafer, including:

S100. Providing a substrate 1;

S200. sequentially depositing a nucleation layer 2, an intrinsic GaN layer 3, an N-type semiconductor layer 4, an electron guiding layer 5, a multi-quantum well layer 6, an electron blocking layer 7, and a P-type semiconductor layer 8 on the substrate 1;

The electron guide layer 5 includes a first electron storage layer 51, a second electron interception layer 52 and a third electron expansion layer 53 arranged in sequence along the epitaxial direction;

The forbidden band width of the second electron intercepting layer 52 >the forbidden band width of the third electron expanding layer 53 >the forbidden band width of the first electron storage layer 51 .

Wherein, in step S100, the substrate 1 can be a Si substrate, a sapphire substrate, etc., but not limited thereto, and the specific steps are as follows:

The temperature of the reaction chamber is controlled to be 1000°C-1200°C, the pressure of the reaction chamber is controlled to be 200Torr-600Torr, and the substrate 1 is annealed at a high temperature for 5-8 minutes under _H2 atmosphere to clean the particles and oxides on the surface of the substrate 1.

Wherein, the specific steps of step S200 are as follows:

S210. Depositing a nucleation layer 2 on the substrate 1:

Wherein, the nucleation layer 2 can be an AlGaN layer or an AlN layer, and this layer is mainly used to provide crystal seeds, alleviate the lattice mismatch between the substrate 1 and the epitaxial layer, and improve the lattice quality of the epitaxial wafer.

Control the temperature of the reaction chamber at 500°C to 700°C, the pressure of the reaction chamber at 200Torr to 400Torr, _N2 and _H2 as the carrier gas, _NH3 as the N source, TMGa as the Ga source, and TMAl as the Al source, The thickness is 20nm~100nm.

S220. Depositing an intrinsic GaN layer 3 on the nucleation layer 2:

The temperature of the reaction chamber is controlled at 1100°C-1150°C, the pressure is 100Torr-500Torr, _N2 and _H2 are used as carrier gases, _NH3 is fed as N source, TMGa is fed as Ga source, and the thickness is 300nm~800nm.

S230. Depositing an N-type semiconductor layer 4 on the intrinsic GaN layer 3:

Control the temperature of the reaction chamber at 1100°C to 1150°C, the pressure at 100Torr to 500Torr, _N2 and _H2 as the carrier gas, _NH3 as the N source, TMGa as the Ga source, and _SiH4 as the N type Dopant, the thickness is 1μm~3μm.

S240. Depositing the electron guiding layer 5 on the N-type semiconductor layer 4, the specific steps are as follows:

S241. Depositing the first electron storage layer 51 on the N-type semiconductor layer 4:

1) depositing In _x N _1-x sublayer 511;

2) Depositing the In _y Ga _1-y N sublayer 512;

3) depositing a GaN sublayer 513;

Among them, 0.6≥x≥0.4, 0.3≥y≥0.1;

The thickness of a single In _x N _1-x sublayer 511 is 1nm~5nm, the thickness of a single _{InyGa1 -yN} sublayer 512 is 1nm~5nm, and the thickness of a single GaN sublayer 513 is 6nm~10nm, the first electron The number of cycles of the storage layer 51 is 2 to 6, the growth temperature is 800° C. to 900° C., and the pressure is 100 Torr to 300 Torr.

S242. Depositing the second electron interception layer 52 on the first electron storage layer 51:

1) depositing a B _m Ga _1-m N sublayer 521;

2) Depositing a B _n N _1-n sublayer 522;

Among them, 0.3≥m≥0.1, 0.5≥n≥0.3;

The thickness of a single _{BmGa1 -mN} sublayer 521 is 6nm~10nm, the thickness of a single _{BnN1 -n} sublayer 522 is 2nm~5nm, and the number of periods of the second electron intercepting layer 52 is 2~6 , the growth temperature is 1000°C~1100°C, and the pressure is 100Torr~300Torr.

S243. Depositing the third electron expansion layer 53 on the second electron interception layer 52:

1) depositing an In _a Ga _1-a N sublayer 531;

2) depositing an N-type B _b Ga _1-b N sublayer 532;

Among them, 0.3≥a≥0.1, 0.3≥b≥0.1, the doping concentration of Si is 1×10 ¹⁶ cm ^-3 ~1×10 ¹⁷ cm ^-3 ;

The thickness of a single In _a Ga _1-a N sublayer 531 is 1nm~10nm, the thickness of a single N-type _{BbGa 1-b} N sublayer is 10nm~20nm, and the growth temperature of the third electron expansion layer 53 is 900°C~ 1000°C, the number of cycles is 2~6, and the pressure is 100Torr~300Torr.

S250. Depositing a multi-quantum well layer 6 on the electron guiding layer 5:

The multi-quantum well layer 6 is an InGaN/GaN layer, the number of periods is 3-15, the temperature of the reaction chamber is controlled at 700°C-900°C, the pressure is 100Torr-500Torr, and the thickness of the multi-quantum well layer 6 of a single period is 2nm ~5nm.

S260. Depositing an electron blocking layer 7 on the multiple quantum well layer 6:

The electron blocking layer 7 is an AlGaN/InGaN layer, the number of cycles is 3~15, the temperature of the reaction chamber is controlled at 900°C~1000°C, the pressure is 100Torr~500Torr, and the thickness of a single cycle of the electron blocking layer 7 is 20nm~100nm , where TMGa is used as the Ga source, TMAl is used as the Al source, and TMIn is used as the In source.

S270. Depositing a P-type semiconductor layer 8 on the electron blocking layer 7:

The temperature of the reaction chamber is controlled at 800°C~1000°C, the pressure is 100Torr~300Torr, NH ₃ is fed in as the N source, TMGa is fed in as the Ga source, and CP ₂ Mg is fed in as the P-type dopant. Among them, the doping of Mg The impurity concentration is 5×10 ¹⁷ ~1×10 ²⁰ cm ^-3 , and the thickness is 200nm~300nm.

Below in conjunction with accompanying drawing and embodiment the present invention will be further described:

Example 1

Referring to Fig. 1, the present embodiment discloses a light-emitting diode epitaxial wafer, including a substrate 1, on which a nucleation layer 2, an intrinsic GaN layer 3, an N-type semiconductor layer 4, and an electron guiding layer are sequentially arranged along the epitaxial direction. Layer 5, multi-quantum well layer 6, electron blocking layer 7, P-type semiconductor layer 8;

The electron guide layer 5 includes a first electron storage layer 51, a second electron interception layer 52 and a third electron expansion layer 53 arranged in sequence along the epitaxial direction;

The forbidden band width of the second electron intercepting layer 52 >the maximum forbidden band width of the third electron expanding layer 53 >the forbidden band width of the first electron storage layer 51 .

Wherein, the first electron storage layer 51 includes a first sub-layer, a second sub-layer and a third sub-layer stacked periodically, and the band gap Eg ₃ of the third sub-layer > the band gap Eg ₂ of the second sub-layer > The forbidden band of the first sublayer is Eg ₁ , and Eg ₃ /Eg ₁ >3, and the forbidden band of the second electron intercepting layer 52 is >1.5×Eg ₃ .

Referring to Fig. 2, wherein, the first electron storage layer 51 is In _x N _1-x /In _y Ga _1-y N/GaN layer, and the second electron interception layer 52 is B _m Ga _1-m N/B _n N _1-n layer, the third electron expansion layer 53 is an In _a Ga _1-a N/N type B _b Ga _1-b N layer.

Wherein, in the first electron storage layer 51, x is 0.6, and y is 0.3.

Referring to FIG. 3 , the first electron storage layer 51 includes periodically stacked In _x N _1-x sub-layers 511, In _y Ga _{1- y} N sub-layers 512 and GaN sub-layers 513, wherein a single In _x The thickness of the N _1-x sublayer 511 is 3nm, the thickness of a single In _y Ga _1-y N sublayer 512 is 3nm, the thickness of a single GaN sublayer 513 is 8nm, and the number of periods of the first electron storage layer 51 is 3 , the growth temperature is 900°C.

Wherein, in the second electron intercepting layer 52, m is 0.3, and n is 0.5.

4, wherein the second electron intercepting layer 52 includes periodically stacked B _m Ga _1-m N sub-layers 521 and B _n N _1-n sub-layers 522, wherein a single B _m Ga _1-m N The thickness of the sublayer 521 is 8nm, the thickness of a single _{BnN1 -n} sublayer 522 is 3nm, the number of cycles of the second electron intercepting layer 52 is 4, and the growth temperature is 1100°C.

Wherein, in the third electron expansion layer 53 , a is 0.3, b is 0.3, and the doping concentration of Si is 5×10 ¹⁶ cm ⁻³ .

5, wherein the third electron expansion layer 53 includes periodically stacked In _a Ga _1-a N sub-layers 531 and N-type B _b Ga _1-b N sub-layers 532, wherein a single In _a Ga _{1 -} the thickness of the a N sublayer 531 is 5 nm, the thickness of a single N-type B _b Ga _1-b N sublayer 532 is 15 nm, and the growth temperature of the third electron expansion layer 53 is 1000° C.

Referring to Figure 6, the present invention also discloses a method for preparing a light-emitting diode epitaxial wafer, including:

S100. Providing a substrate 1;

S200. sequentially depositing a nucleation layer 2, an intrinsic GaN layer 3, an N-type semiconductor layer 4, an electron guiding layer 5, a multi-quantum well layer 6, an electron blocking layer 7, and a P-type semiconductor layer 8 on the substrate 1;

The electron guide layer 5 includes a first electron storage layer 51, a second electron interception layer 52 and a third electron expansion layer 53 arranged in sequence along the epitaxial direction;

The forbidden band width of the second electron intercepting layer 52 >the forbidden band width of the third electron expanding layer 53 >the forbidden band width of the first electron storage layer 51 .

Wherein, the specific steps of step S200 are as follows:

S210. depositing a nucleation layer 2 on the substrate 1;

S220. Depositing an intrinsic GaN layer 3 on the nucleation layer 2;

S230. Depositing an N-type semiconductor layer 4 on the intrinsic GaN layer 3;

S240. Depositing an electron guiding layer 5 on the N-type semiconductor layer 4;

S250. Depositing a multi-quantum well layer 6 on the electron guiding layer 5;

S260. Depositing an electron blocking layer 7 on the multiple quantum well layer 6;

S270 . Depositing a P-type semiconductor layer 8 on the electron blocking layer 7 .

Wherein, the concrete steps of step S240 are as follows:

S241. Depositing the first electron storage layer 51 on the N-type semiconductor layer 4:

1) depositing In _x N _1-x sublayer 511;

2) Depositing the In _y Ga _1-y N sublayer 512;

3) GaN sub-layer 513 is deposited.

S242. Depositing the second electron interception layer 52 on the first electron storage layer 51:

1) depositing a B _m Ga _1-m N sublayer 521;

2) Deposit B _n N _1-n sublayer 522 .

S243. Depositing the third electron expansion layer 53 on the second electron interception layer 52:

1) depositing an In _a Ga _1-a N sublayer 531;

2) Depositing an N-type B _b Ga _1-b N sublayer 532 .

Example 2

This embodiment discloses a light-emitting diode epitaxial wafer, which includes a substrate, on which a nucleation layer, an intrinsic GaN layer, an N-type semiconductor layer, an electron guiding layer, a multi-quantum well layer, an electron blocking layer, P-type semiconductor layer;

The electron guiding layer includes a first electron storage layer, a second electron interception layer and a third electron expansion layer arranged in sequence along the epitaxial direction;

The forbidden band width of the second electron intercepting layer>the maximum forbidden band width of the third electron expanding layer>the forbidden band width of the first electron storage layer.

Wherein, the first electron storage layer includes a first sublayer, a second sublayer and a third sublayer stacked periodically, and the bandgap width Eg 3 of the third sublayer > the bandgap width Eg ₂ of the second sublayer > the bandgap width Eg ₂ of the second sublayer > The forbidden band width of the first sublayer is Eg ₁ , and Eg ₃ /Eg ₁ >3, and the forbidden band width of the second electron intercepting layer is >1.5×Eg ₃ .

Among them, the first electron storage layer is In _x N _1-x /In _y Ga _1-y N/GaN layer, the second electron interception layer is B _m Ga _1-m N/B _n N _1-n layer, and the third The electron expansion layer is an In _a Ga _1-a N/N type B _b Ga _1-b N layer.

Wherein, in the first electron storage layer, x is 0.4, and y is 0.1.

Wherein, the first electron storage layer includes periodically stacked In _x N _1-x sub-layers, In _y Ga _1-y N sub-layers and GaN sub-layers, wherein the thickness of a single In _x N _1-x sub-layer is 3nm , the thickness of a single In _y Ga _1-y N sublayer is 3nm, the thickness of a single GaN sublayer is 8nm, the period number of the first electron storage layer is 3, and the growth temperature is 900°C.

Wherein, in the second electron intercepting layer, m is 0.1, and n is 0.3.

Wherein, the second electron intercepting layer includes periodically stacked B _m Ga _1-m N sub-layers and B _n N _1-n sub-layers, wherein the thickness of a single B _m Ga _1-m N sub-layer is 8nm, and a single B The thickness of _{the n} N _1-n sublayer is 3nm, the period number of the second electron intercepting layer is 4, and the growth temperature is 1100°C.

Wherein, in the third electron expansion layer, a is 0.1, b is 0.1, and the doping concentration of Si is 5×10 ¹⁶ cm ⁻³ .

Wherein, the third electron expansion layer includes periodically stacked In _a Ga _1-a N sublayers and N-type B _b Ga _1-b N sublayers, wherein the thickness of a single In _a Ga _1-a N sublayer is 5nm , the thickness of a single N-type _{BbGa1 -bN} sublayer is 15 nm, and the growth temperature of the third electron expansion layer is 1000 °C.

The invention also discloses a method for preparing a light-emitting diode epitaxial wafer, including:

S100. providing a substrate;

S200. sequentially depositing a nucleation layer, an intrinsic GaN layer, an N-type semiconductor layer, an electron guiding layer, a multiple quantum well layer, an electron blocking layer, and a P-type semiconductor layer on the substrate;

The electron guiding layer includes a first electron storage layer, a second electron interception layer and a third electron expansion layer arranged in sequence along the epitaxial direction;

The forbidden band width of the second electron intercepting layer>the forbidden band width of the third electron expanding layer>the forbidden band width of the first electron storage layer.

Wherein, the concrete steps of step S200 are as follows:

S210. depositing a nucleation layer on the substrate;

S220. Depositing an intrinsic GaN layer on the nucleation layer;

S230. Depositing an N-type semiconductor layer on the intrinsic GaN layer;

S240. Depositing an electron guiding layer on the N-type semiconductor layer;

S250. Depositing a multiple quantum well layer on the electron guiding layer;

S260. Depositing an electron blocking layer on the multiple quantum well layer;

S270. Depositing a P-type semiconductor layer on the electron blocking layer.

Wherein, the concrete steps of step S240 are as follows:

S241. Depositing a first electron storage layer on the N-type semiconductor layer:

1) Deposit In _x N _1-x sublayers;

2) Deposit In _y Ga _1-y N sublayer;

3) GaN sublayers are deposited.

S242. Depositing a second electron interception layer on the first electron storage layer:

1) Deposit B _m Ga _1-m N sublayer;

2) Deposit _{BnN1 -n} sublayers.

S243. Depositing a third electron expansion layer on the second electron interception layer:

1) Deposit In _a Ga _1-a N sublayer;

2) Deposit the N-type _{BbGa1 -bN} sublayer.

Comparative example 1

The difference between this comparative example and Example 1 is that the epitaxial wafer of this comparative example does not include an electron guiding layer, and the preparation method does not include the preparation steps of corresponding material layers.

Comparative example 2

The difference between this comparative example and Example 1 is that the electron guiding layer of this comparative example does not include the first electron storage layer, and the preparation method does not include the preparation steps of the corresponding material layer.

Comparative example 3

The difference between this comparative example and Example 1 is that the first electron storage layer of this comparative example is an In _y Ga _1-y N/GaN layer, that is, the first electron storage layer does not include an In _x N _1-x sublayer , the preparation method does not include the preparation step of the corresponding material layer.

Comparative example 4

The difference between this comparative example and Example 1 is that the electron guiding layer of this comparative example does not include the second electron intercepting layer, and the preparation method does not include the preparation steps of the corresponding material layer.

Comparative example 5

The difference between this comparative example and Example 1 is that the second electron intercepting layer of this comparative example is a B _m Ga _1-m N sublayer, that is, the second electron intercepting layer does not include a B _n N _1-n sublayer, The preparation method does not include the preparation steps of the corresponding material layer.

Comparative example 6

The difference between this comparative example and Example 1 is that the electron guiding layer of this comparative example does not include the third electron expansion layer, and the preparation method does not include the preparation steps of the corresponding material layer.

Comparative example 7

The difference between this comparative example and Example 1 is that the third electron expansion layer of this comparative example is periodically laminated with In _a Ga _1-a N sublayers and undoped B _b Ga _1-b N sublayers, namely The B _b Ga _1-b N sublayer is not N-type doped.

Photoelectric performance test:

Test method: take the epitaxial wafers prepared in Examples 1-2 and Comparative Examples 1-7, make a 10*24mil chip, and then conduct photoelectric performance tests.

Wherein, the smaller the brightness uniformity value is, the more uniform the brightness distribution is, and the smaller the wavelength uniformity value is, the more uniform the wavelength distribution is.

The test results are as follows:

The test results show that Embodiment 1~Example 2 and Comparative Example 2~Comparative Example 7 have different degrees of improvement compared with Comparative Example 1 in terms of antistatic ability, luminous efficiency, brightness uniformity, and wavelength uniformity. Examples 1~Example 2 have significantly improved performance in various aspects. Combining Example 1, Comparative Example 2 and Comparative Example 3, it can be seen that the first electron storage layer and its specific material layer structure settings have a significant impact on luminous efficiency, brightness uniformity, wavelength Uniformity has an impact. In combination with Example 1, Comparative Example 4 and Comparative Example 5, it can be seen that the second electron interception layer and its specific material layer structure settings have an impact on antistatic ability, luminous efficiency, brightness uniformity, and wavelength uniformity. Combined with implementation Example 1, Comparative Example 6 and Comparative Example 7, it can be seen that the structure settings of the third electron expansion layer and its specific material layer have an impact on the antistatic ability, luminous efficiency, brightness uniformity, and wavelength uniformity.

The above descriptions are only preferred embodiments of the present invention, and do not limit the present invention in any form. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Anyone familiar with the technology of this patent Without departing from the scope of the technical solution of the present invention, personnel can use the technical content of the above prompts to make some changes or modify them into equivalent embodiments with equivalent changes. In essence, any simple modifications, equivalent changes and modifications made to the above embodiments still fall within the scope of the solutions of the present invention.

Claims (10)

1. A light-emitting diode epitaxial wafer, comprising a substrate, characterized in that, the substrate is sequentially provided with a nucleation layer, an intrinsic GaN layer, an N-type semiconductor layer, an electron guiding layer, a multi-quantum well layer, Electron blocking layer, P-type semiconductor layer; The electron guide layer includes a first electron storage layer, a second electron interception layer and a third electron expansion layer sequentially arranged along the epitaxial direction; The forbidden band width of the second electron intercepting layer>the maximum forbidden band width of the third electron expanding layer>the forbidden band width of the first electron storage layer. 2. The light-emitting diode epitaxial wafer according to claim 1, wherein the first electron storage layer comprises a first sub-layer, a second sub-layer and a third sub-layer stacked periodically, and the third sub-layer The forbidden band width Eg ₃ of the layer > the forbidden band width Eg ₂ of the second sublayer > the forbidden band width Eg ₁ of the first sublayer, and Eg ₃ /Eg ₁ > 3, the forbidden band width of the second electron intercepting layer >1.5×Eg ₃ . 3. The light-emitting diode epitaxial wafer according to claim 1, wherein the first electron storage layer is an In _x N _1-x /In _y Ga _1-y N/GaN layer, and the second electron interceptor The layer is a B _m Ga _1-m N/B _n N _1-n layer, and the third electron expansion layer is an In _a Ga _1-a N/N type B _b Ga _1-b N layer. 4 . The light emitting diode epitaxial wafer according to claim 3 , wherein, in the first electron storage layer, 0.6≥x≥0.4 and 0.3≥y≥0.1. 5. The light-emitting diode epitaxial wafer according to claim 4, wherein the first electron storage layer comprises periodically stacked In _x N _1-x sub-layers, In _y Ga _1-y N sub-layers and GaN sublayers, wherein the thickness of a single In _x N _1-x sublayer is 1nm~5nm, the thickness of a single In _y Ga _1-y N sublayer is 1nm~5nm, and the thickness of a single GaN sublayer is 6nm~10nm, so The number of cycles of the first electron storage layer is 2 to 6, and the growth temperature is 800°C to 900°C. 6 . The light emitting diode epitaxial wafer according to claim 3 , wherein, in the second electron intercepting layer, 0.3≥m≥0.1, 0.5≥n≥0.3. 7. The light-emitting diode epitaxial wafer according to claim 6, wherein the second electron intercepting layer comprises periodically stacked B _m Ga _1-m N sublayers and B _n N _1-n sublayers, wherein , the thickness of a single B _m Ga _1-m N sublayer is 6nm~10nm, the thickness of a single _{BnN 1-n} sublayer is 2nm~5nm, and the number of cycles of the second electron intercepting layer is 2~6 , the growth temperature is 1000℃~1100℃. 8. The light-emitting diode epitaxial wafer according to claim 3, characterized in that, in the third electron expansion layer, 0.3≥a≥0.1, 0.3≥b≥0.1, and the doping concentration of Si is 1×10 ¹⁶ cm ^-3 ~1×10 ¹⁷ cm ^-3 . 9. The light-emitting diode epitaxial wafer according to claim 8, wherein the third electron expansion layer comprises periodically stacked In _a Ga _1-a N sub-layers and N-type B _b Ga _1-b N sub-layers layer, wherein the thickness of a single In _a Ga _1-a N sublayer is 1nm~10nm, the thickness of a single N-type _{BbGa 1-b} N sublayer is 10nm~20nm, and the growth temperature of the third electron expansion layer 900°C~1000°C. 10. A method for preparing a light-emitting diode epitaxial wafer, comprising: provide the substrate; sequentially depositing a nucleation layer, an intrinsic GaN layer, an N-type semiconductor layer, an electron guiding layer, a multiple quantum well layer, an electron blocking layer, and a P-type semiconductor layer on the substrate; The electron guide layer includes a first electron storage layer, a second electron interception layer and a third electron expansion layer sequentially arranged along the epitaxial direction; The forbidden band width of the second electron intercepting layer>the maximum forbidden band width of the third electron expanding layer>the forbidden band width of the first electron storage layer.

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