CN116759500B - Light-emitting diode epitaxial wafer and preparation method thereof, light-emitting diode - Google Patents

Abstract

The invention relates to a light-emitting diode epitaxial wafer and a preparation method thereof, as well as a light-emitting diode. The epitaxial wafer includes an epitaxial wafer, a substrate and an epitaxial wafer stacked on the substrate. The epitaxial wafer includes electron blocking layers stacked sequentially along the epitaxial direction. P-type layer, an insertion layer is provided between the electron blocking layer and the P-type layer; the insertion layer includes a first hole acceleration layer, an intermediate buffer layer and a second hole acceleration layer sequentially stacked along the epitaxial direction; the first hole acceleration layer The layer is a superlattice structure formed by the periodic alternate growth of the first MgN sub-layer and the AlInGaN sub-layer. The middle buffer layer is a graphene layer, and the second hole accelerating layer is composed of the second MgN sub-layer and the InGaN sub-layer periodically. A superlattice structure formed by alternating sexual growth. The invention can effectively improve the luminous efficiency of the light-emitting diode, increase the surface flatness of the epitaxial wafer, and improve the antistatic ability.

Description

Light-emitting diode epitaxial wafer and preparation method thereof, light-emitting diode

Technical field

The present invention relates to the field of semiconductor technology, and in particular to a light-emitting diode epitaxial wafer and a preparation method thereof, and a light-emitting diode.

Background technique

In the existing technology, the structure of a gallium nitride-based light-emitting diode epitaxial wafer is generally a nucleation layer, an intrinsic GaN layer, an N-type semiconductor layer, a multi-quantum well layer, an electron blocking layer and a P-type semiconductor layer sequentially stacked on a substrate. , on the one hand, the activation rate of Mg in the existing P-type semiconductor layer is very low, and the mobility of holes is low. In addition, the high barrier height of the electron blocking layer will also block the holes to a certain extent, resulting in multi-quantum Insufficient holes in the well layer affect the luminous efficiency; on the other hand, the accumulated defects from the bottom layer extend to the P-type semiconductor layer, which will capture some holes and consume the holes, affecting the hole concentration and also affecting the luminous efficiency. , and will affect the surface flatness of the epitaxial layer, and will also become a leakage channel, resulting in a decrease in the anti-static ability of the light-emitting diode.

Contents of the invention

The purpose of the present invention is to provide a light-emitting diode epitaxial wafer, a preparation method thereof, and a light-emitting diode in view of the existing technical status. The present invention can greatly increase the hole concentration entering the multi-quantum well layer through the arrangement of the insertion layer. It reduces the blocking effect of the electron blocking layer on holes in the traditional structure, improves the growth quality of the P-type layer, and reduces the consumption of holes by defects, thereby effectively improving the luminous efficiency of the light-emitting diode and increasing the surface smoothness of the epitaxial wafer. degree and improve anti-static ability.

In order to achieve the above objects, the present invention adopts the following technical solutions:

On the one hand, the present invention provides a light-emitting diode epitaxial wafer, which includes a substrate and an epitaxial wafer stacked on the substrate. The epitaxial wafer includes an electron blocking layer and a P-type layer sequentially stacked along the epitaxial direction. An insertion layer is provided between the barrier layer and the P-type layer;

The insertion layer includes a first hole acceleration layer, an intermediate buffer layer and a second hole acceleration layer that are sequentially stacked along the epitaxial direction;

The first hole accelerating layer is a superlattice structure formed by periodically growing a first MgN sub-layer and an AlInGaN sub-layer, the intermediate buffer layer is a graphene layer, and the second hole accelerating layer is A superlattice structure formed by the periodic alternate growth of the second MgN sublayer and the InGaN sublayer.

In some embodiments, in the AlInGaN sublayer, the Al content decreases as the number of cycles of the first hole accelerating layer increases, and the In content increases as the number of cycles of the first hole accelerating layer increases. .

In some embodiments, the Al content in the AlInGaN sublayer decreases from a to b as the number of cycles of the first hole acceleration layer increases, where 0.1≤a≤0.4 and 0.01≤b≤0.05.

In some embodiments, the In content in the AlInGaN sublayer increases from c to d as the number of cycles of the first hole accelerating layer increases, where 0<c<0.05, 0.05≤d≤0.1.

In some embodiments, the In content in the InGaN sublayer is 0.05~0.1.

In some embodiments, in the first hole accelerating layer, the thickness of a single first MgN sub-layer is 0.1 nm~5 nm, and the thickness of a single AlInGaN sub-layer is 0.1 nm~5 nm; the second In the hole acceleration layer, the thickness of a single second MgN sublayer is 0.1nm~5nm, and the thickness of a single InGaN sublayer is 0.1nm~5nm.

In some embodiments, the number of cycles of the first hole accelerating layer is 1 to 5, and the growth temperature is 800°C~1000°C; the number of cycles of the second hole accelerating layer is 1 to 5 , the growth temperature is 800℃~1000℃.

In some embodiments, the thickness of the graphene layer is 1 nm to 10 nm, and the graphene layer is produced by physical vapor deposition.

On the other hand, the present invention provides a method for preparing a light-emitting diode epitaxial wafer, including:

Provide a substrate;

depositing an epitaxial layer on the substrate;

The epitaxial wafer includes an electron blocking layer and a P-type layer sequentially stacked along the epitaxial direction, and an insertion layer is provided between the electron blocking layer and the P-type layer;

The insertion layer includes a first hole acceleration layer, an intermediate buffer layer and a second hole acceleration layer that are sequentially stacked along the epitaxial direction;

The first hole accelerating layer is a superlattice structure formed by periodically growing a first MgN sub-layer and an AlInGaN sub-layer, the intermediate buffer layer is a graphene layer, and the second hole accelerating layer is A superlattice structure formed by the periodic alternate growth of the second MgN sublayer and the InGaN sublayer.

Furthermore, the present invention provides a light-emitting diode, including the above-mentioned light-emitting diode epitaxial wafer.

The beneficial effects of the present invention are:

In the present invention, an insertion layer is provided between the electron blocking layer and the P-type layer, wherein the insertion layer is provided with a second hole accelerating layer on a side close to the P-type layer, and the second hole accelerating layer is composed of a second A superlattice structure formed by the periodic and alternate growth of MgN sublayers and InGaN sublayers. The heterogeneous superlattice structure composed of the second MgN sublayer and InGaN sublayer will generate a huge polarization electric field, thereby creating a two-dimensional space. Holes help to increase the mobility of carriers, so that the holes generated in the P-type layer have improved mobility and expansion capabilities under the action of the second hole acceleration layer; at the same time, the second MgN The sublayer will generate holes, and In in the InGaN sublayer can reduce the activation energy of Mg and further increase the hole concentration.

Secondly, the insertion layer of the present invention uses a graphene layer as an intermediate buffer layer between the second hole accelerating layer and the first hole accelerating layer. On the one hand, the graphene layer can enable materials to be combined according to van der Waals force. , greatly improves the lattice quality, avoids the defects extending from the bottom layer to extend further upward, improves the antistatic ability of the light-emitting diode, and avoids the accumulation of defects in the P-type layer to capture holes and cause hole consumption, thereby increasing the effective entry The holes in the multi-quantum well layer improve the luminous efficiency; on the other hand, the graphene layer can increase the matching between the P-type layer and the electron blocking layer to avoid the damage to holes caused by the high barrier height of the electron blocking layer. The blocking effect, and the higher mobility of carriers in the graphene layer, is also conducive to increasing the concentration of holes entering the multi-quantum well layer through the electron blocking layer.

Furthermore, the insertion layer of the present invention is provided with a first hole accelerating layer on the side close to the electron blocking layer, and the first hole accelerating layer is formed by periodically alternating growth of the first MgN sub-layer and the AlInGaN sub-layer. Superlattice structure. On the one hand, the heterogeneous superlattice structure composed of the first MgN sublayer and the AlInGaN sublayer will generate a huge polarization electric field, further improving the idle mobility. At the same time, through the first MgN sublayer and the The AlInGaN sublayer can further increase the hole concentration; on the other hand, due to the bandgap width, InGaN＜AlInGaN＜AlGaN, it can increase the potential barrier and lattice matching with the electron blocking layer, allowing more holes to pass through the electrons barrier layer into the multi-quantum well layer.

In summary, through the arrangement of the insertion layer, the present invention can greatly increase the concentration of holes entering the multi-quantum well layer, reduce the blocking effect of the electron blocking layer on holes in the traditional structure, and improve the growth quality of the P-type layer. , reducing the consumption of holes by defects, thereby effectively improving the luminous efficiency of the light-emitting diode, increasing the surface flatness of the epitaxial wafer, and improving the antistatic ability.

Description of the drawings

Figure 1 is a schematic structural diagram of the light-emitting diode epitaxial wafer of the present invention.

Figure 2 is a schematic structural diagram of the insertion layer of the present invention.

FIG. 3 is a flow chart of a method for preparing a light-emitting diode epitaxial wafer of the present invention.

Detailed ways

In order to make the purpose, technical solutions and advantages of the present invention clearer, the present invention will be described in further detail below.

On the one hand, as shown in FIGS. 1 to 2 , the present invention discloses a light-emitting diode epitaxial wafer, which includes a substrate 1 and an epitaxial wafer stacked on the substrate 1 . The epitaxial wafer includes electron blocking layers 6 sequentially stacked along the epitaxial direction. and P-type layer 8, with an insertion layer 7 provided between the electron blocking layer 6 and the P-type layer 8;

The insertion layer 7 includes a first hole acceleration layer 71, an intermediate buffer layer 72 and a second hole acceleration layer 73 that are sequentially stacked along the epitaxial direction;

The first hole accelerating layer 71 is a superlattice structure formed by periodically growing the first MgN sub-layer 711 and the AlInGaN sub-layer 712. The middle buffer layer 72 is a graphene layer, and the second hole accelerating layer 73 is made of The second MgN sub-layer 731 and the InGaN sub-layer 732 grow periodically and alternately to form a superlattice structure.

In the present invention, an insertion layer 7 is provided between the electron blocking layer 6 and the P-type layer 8, wherein the insertion layer 7 is provided with a second hole acceleration layer 73 on the side close to the P-type layer 8, and the second hole acceleration layer 73 is provided on the side close to the P-type layer 8. The acceleration layer 73 is a superlattice structure formed by periodically growing the second MgN sub-layer 731 and the InGaN sub-layer 732. The heterogeneous superlattice structure composed of the second MgN sub-layer 731 and the InGaN sub-layer 732 will produce polarization. The large polarization electric field generates two-dimensional hole gas, which helps to increase the mobility of carriers, thereby causing the holes generated in the P-type layer 8 to migrate under the action of the second hole acceleration layer 73 The rate and expansion capability are improved; at the same time, the second MgN sublayer 731 will generate holes, and the In in the InGaN sublayer 732 can reduce the activation energy of Mg and further increase the hole concentration.

Secondly, the insertion layer 7 of the present invention uses a graphene layer as the intermediate buffer layer 72 between the second hole accelerating layer 73 and the first hole accelerating layer 71. On the one hand, the graphene layer can enable the material to be processed according to van der The combination of Vals force greatly improves the quality of the crystal lattice, prevents defects extending from the bottom layer from extending further upward, improves the antistatic ability of the light-emitting diode, and prevents defects from accumulating into the P-type layer 8 to capture holes and cause hole consumption. This increases the number of holes that effectively enter the multi-quantum well layer 5 and improves the luminous efficiency; on the other hand, the graphene layer can increase the matching degree between the P-type layer 8 and the electron blocking layer 6 to avoid high The barrier height causes a blocking effect on holes, and the mobility of carriers in the graphene layer is high, which is also conducive to increasing the concentration of holes entering the multi-quantum well layer 5 through the electron blocking layer 6.

Furthermore, the insertion layer 7 of the present invention is provided with a first hole acceleration layer 71 on the side close to the electron blocking layer 6, and the first hole acceleration layer 71 is composed of a first MgN sub-layer 711 and an AlInGaN sub-layer 712. A superlattice structure formed by alternating sexual growth. On the one hand, the heterogeneous superlattice structure composed of the first MgN sublayer 711 and the AlInGaN sublayer 712 will generate a huge polarization electric field, further increasing the idle mobility, and at the same time , the hole concentration can be further increased through the first MgN sub-layer 711 and the AlInGaN sub-layer 712; on the other hand, due to the forbidden band width, InGaN<AlInGaN<AlGaN, the potential barrier and lattice matching with the electron blocking layer 6 can be increased. degree, so that more holes can enter the multi-quantum well layer 5 through the electron blocking layer 6 .

In summary, through the arrangement of the insertion layer 7, the present invention can greatly increase the concentration of holes entering the multi-quantum well layer 5, reduce the blocking effect of the electron blocking layer 6 on holes in the traditional structure, and improve the P-type layer The growth quality of 8 reduces the consumption of holes by defects, thereby effectively improving the luminous efficiency of the light-emitting diode, increasing the surface flatness of the epitaxial wafer, and improving the antistatic ability.

Among them, in the AlInGaN sublayer 712, the Al content decreases as the number of cycles of the first hole accelerating layer 71 increases, and the In content increases as the number of cycles of the first hole accelerating layer 71 increases.

That is, in the i-th cycle, the Al content in the AlInGaN sub-layer 712 is k, and the In content is m. In the i+1-th cycle, the Al content in the AlInGaN sub-layer 712 is j, and the In content is n, k. > j, n > m.

Since the bandgap width is InGaN<AlInGaN<AlGaN, therefore, through the gradient setting of the Al content and In content of the AlInGaN sublayer 712, the first hole accelerating layer 71 is made from the P-type layer 8 to the electron blocking layer 6. direction, the potential barrier of the AlInGaN sub-layer 712 gradually changes from low to high. The closer the AlInGaN sub-layer 712 is to the electron blocking layer 6, the higher the matching degree with the potential barrier and lattice of the electron blocking layer 6, effectively reducing the electron blocking in the traditional structure. The potential barrier of layer 6 is too high to block holes, allowing more holes to pass through the electron blocking layer 6 and enter the multi-quantum well layer 5 .

Among them, in the AlInGaN sublayer 712, the Al content decreases from a to b as the number of cycles of the first hole acceleration layer 71 increases, where 0.1≤a≤0.4, 0.01≤b≤0.05, for example, a is 0.1, 0.2, 0.25, 0.3, 0.35 or 0.4, but not limited to this, b is 0.01, 0.02, 0.03, 0.04 or 0.05, but not limited to this. Too high Al content can easily cause the potential barrier to be too high and affect the crystal quality. If the Al content is too low, the barrier and lattice matching with the electron blocking layer 6 will be reduced.

For example, the number of cycles of the first hole accelerating layer 71 is 2. In the first cycle, the Al content of the AlInGaN sublayer 712 is 0.1, and in the second cycle, the Al content of the AlInGaN sublayer 712 is 0.05, but Not limited to this.

For example, the number of cycles of the first hole accelerating layer 71 is 4. In the first cycle, the Al content of the AlInGaN sublayer 712 is 0.4. In the second cycle, the Al content of the AlInGaN sublayer 712 is 0.1. In the third cycle, the Al content of the AlInGaN sublayer 712 is 0.08, and in the fourth cycle, the Al content of the AlInGaN sublayer 712 is 0.01, but is not limited thereto.

Among them, the In content in the AlInGaN sub-layer 712 increases from c to d as the number of cycles of the first hole acceleration layer 71 increases, where 0<c<0.05, 0.05≤d≤0.1, for example, c is 0.01, 0.02, 0.028, 0.03, 0.035, 0.04 or 0.049, but not limited to this, d is 0.05, 0.06, 0.07, 0.075, 0.08, 0.09 or 0.1, but not limited to this. Excessive In content will cause lattice quality Significant decrease, In content is too low is not conducive to reducing the activation energy of Mg.

For example, the number of cycles of the first hole accelerating layer 71 is 2. In the first cycle, the In content of the AlInGaN sublayer 712 is 0.049. In the second cycle, the In content of the AlInGaN sublayer 712 is 0.1, but Not limited to this.

For example, the number of cycles of the first hole accelerating layer 71 is 4. In the first cycle, the In content of the AlInGaN sublayer 712 is 0.01. In the second cycle, the In content of the AlInGaN sublayer 712 is 0.03. In the third cycle, the In content of the AlInGaN sublayer 712 is 0.05, and in the fourth cycle, the In content of the AlInGaN sublayer 712 is 0.08, but is not limited thereto.

Among them, the In content in the InGaN sublayer 732 is 0.05~0.1. For example, the In content is 0.05, 0.06, 0.07, 0.08, 0.09 or 0.1, but is not limited to this. Too high an In content will cause a significant decrease in the lattice quality. , too low In content is not conducive to reducing the activation energy of Mg.

Among them, in the first hole accelerating layer 71, the thickness of a single first MgN sub-layer 711 is 0.1nm~5nm, and the thickness of a single AlInGaN sub-layer 712 is 0.1nm~5nm; in the second hole accelerating layer 73, the thickness of a single first MgN sub-layer 711 is 0.1nm~5nm. The thickness of the two MgN sublayers 731 is 0.1nm~5nm, and the thickness of the single InGaN sublayer 732 is 0.1nm~5nm. For example, the thickness of the single first MgN sublayer 711 is 0.1nm, 0.5nm, 2nm, 2.5nm. , 3.5nm, 4.5nm or 5nm, the thickness of a single AlInGaN sub-layer 712 is 0.1nm, 0.5nm, 0.8nm, 1.2nm, 2.5nm, 3.5nm, 4.8nm or 5nm, but is not limited thereto; illustratively, a single The thickness of the second MgN sublayer 731 is 0.1nm, 0.5nm, 1nm, 2.8nm, 3nm, 4.8nm or 5nm, and the thickness of the single InGaN sublayer 732 is 0.1nm, 0.5nm, 0.8nm, 1.2nm, 2.5nm, 3.5nm, 4.8nm or 5nm, but not limited to this.

Among them, the number of cycles of the first hole accelerating layer 71 is 1 to 5, and the growth temperature is 800°C~1000°C; the number of cycles of the second hole accelerating layer 73 is 1 to 5, and the growth temperature is 800°C. ~1000°C. Too high a temperature is not conducive to the incorporation of In, and too low a temperature can easily cause a decrease in lattice quality.

More preferably, the number of cycles of the first hole accelerating layer 71 is 2 to 5, and the number of cycles of the second hole accelerating layer 73 is 2 to 5.

Wherein, the thickness of the graphene layer is 1nm~10nm, and the graphene layer is produced by physical vapor deposition (PVD) method. For example, the thickness of the graphene layer is 1nm, 2nm, 5nm, 7nm, 9nm or 10nm, but not Limited to this, the thickness of the graphene layer is too small to reduce the lattice defects extending upward from the bottom layer.

Among them, the preparation steps of the graphene layer are as follows:

First, using the PVD method, the growth substrate is a 300nm Ni film deposited by electron beam, the carbon source is CH ₄ , the growth temperature is 1000°C, the carrier gas is a mixture of H ₂ and Ar, the graphene layer is grown, and then transferred to the third on a hole accelerating layer 71 .

Among them, the epitaxial wafer also includes a nucleation layer 2, an intrinsic GaN layer 3, an N-type layer 4, and a multi-quantum well layer 5 deposited sequentially on the substrate 1. The electron blocking layer 6 is deposited on the multi-quantum well layer 5.

Among them, the multi-quantum well layer 5 is a periodic structure composed of InGaN quantum well layers and GaN quantum barrier layers alternately stacked, and the number of periods of the multi-quantum well layer 5 is 3 to 15.

Among them, the electron blocking layer 6 is a periodic structure grown alternately by Al _y Ga _1-y N material layers and In _z Ga _1-z N material layers, where 0.05≤y≤0.2, 0.1≤z≤0.5.

On the other hand, as shown in Figures 1 to 3, the present invention discloses a method for preparing a light-emitting diode epitaxial wafer, which includes:

S100. Provide substrate 1;

S200. Deposit an epitaxial layer on the substrate 1;

The epitaxial wafer includes an electron blocking layer 6 and a P-type layer 8 that are stacked sequentially along the epitaxial direction. An insertion layer 7 is provided between the electron blocking layer 6 and the P-type layer 8;

The insertion layer 7 includes a first hole acceleration layer 71, an intermediate buffer layer 72 and a second hole acceleration layer 73 that are sequentially stacked along the epitaxial direction;

The first hole accelerating layer 71 is a superlattice structure formed by periodically growing the first MgN sub-layer 711 and the AlInGaN sub-layer 712. The middle buffer layer 72 is a graphene layer, and the second hole accelerating layer 73 is made of The second MgN sub-layer 731 and the InGaN sub-layer 732 grow periodically and alternately to form a superlattice structure.

Among them, the substrate 1 can be a sapphire substrate, a Si substrate, a SiC substrate, etc., but is not limited thereto.

Among them, the specific steps of depositing an epitaxial layer on the substrate 1 in step S200 are as follows:

S210. Deposit nucleation layer 2 on substrate 1:

The nucleation layer 2 can be an AlGaN material layer or an AlN material layer. Taking the AlGaN material layer as an example, the MOCVD (Metal Organic Compound Chemical Vapor Deposition) method is used to control the reaction chamber temperature to 500°C~700°C and the reaction chamber pressure to 200torr~ 400torr, NH ₃ as N source, N ₂ and H ₂ as carrier gases, TMGa as Ga source, and TMAl as Al source.

S220. Deposit intrinsic GaN layer 3 on nucleation layer 2:

Using the MOCVD method, the reaction chamber temperature is controlled to 1100℃~1150℃, the reaction chamber pressure is 100torr~500torr, NH ₃ is used as the N source, N ₂ and H ₂ are used as the carrier gas, and TMGa is used as the Ga source.

S230. Deposit N-type layer 4 on intrinsic GaN layer 3:

The MOCVD method is used, the reaction chamber temperature is controlled to 1100℃~1150℃, the reaction chamber pressure is 100torr~500torr, NH ₃ is used as the N source, N ₂ and H ₂ are used as the carrier gas, TMGa is used as the Ga source, and SiH ₄ is used as the N-type doping agent to grow a Si-doped N-type GaN layer.

S240. Deposit multiple quantum well layer 5 on N-type layer 4:

The multi-quantum well layer 5 is a periodic structure composed of InGaN quantum well layers and GaN quantum barrier layers alternately stacked. The number of cycles of the multi-quantum well layer 5 is 3 to 15. During the growth process of the InGaN quantum well layer , using the MOCVD method, controlling the reaction chamber temperature to 700℃~800℃, the reaction chamber pressure to 100torr~500torr, NH ₃ as the N source, N ₂ and H ₂ as the carrier gas, TMGa as the Ga source, TMIn as the In source, GaN During the growth process of the quantum barrier layer, control the reaction chamber temperature to 800℃~900℃, the reaction chamber pressure to 100torr~500torr, turn off the In source, use _N2 and _H2 as carrier gases, TEGa as the Ga source, and _NH3 as the N source. .

S250. Deposit the electron blocking layer 6 on the multi-quantum well layer 5:

The electron blocking layer 6 is a periodic structure composed of Al _y Ga _1-y N material layers and In _z Ga _1-z N material layers alternately grown, where 0.05≤y≤0.2, 0.1≤z≤0.5, using the MOCVD method, The reaction chamber temperature is controlled to 900°C~1000°C, the reaction chamber pressure is 100torr~300torr, _NH3 is used as the N source, _N2 and _H2 are used as the carrier gas, TMGa is used as the Ga source, TMAl is used as the Al source, and TMIn is used as the In source.

S260. Deposit insertion layer 7 on electron blocking layer 6:

S261. Deposit the first hole acceleration layer 71 on the electron blocking layer 6:

Specifically, the first MgN sub-layer 711 and the AlInGaN sub-layer 712 are alternately grown, and the number of cycles is 1 to 5. The first hole accelerating layer 71 can be grown using the MOCVD method, PVD method or molecular beam epitaxy (MBE) method. Taking the MOCVD method as an example, the temperature of the reaction chamber is controlled at 800℃~1000℃, the pressure is 100torr~500torr, N2 _{and H2} are used as carrier gases, _NH3 is used as the N source, _{and CP2Mg} is used as the Mg source to grow the first MgN Sublayer 711, with a thickness of 0.1nm~5nm; then keep the growth temperature and pressure unchanged, continue to pass in NH ₃ /N ₂ /H ₂ , turn off CP ₂ Mg, TEGa as Ga source, TMIn as In source, TMAl as Al Source, grow AlInGaN sublayer 712 with a thickness of 0.1nm~5nm.

S262. Deposit the intermediate buffer layer 72 on the first hole acceleration layer 71:

Specifically, the middle buffer layer 72 is a graphene layer, and the graphene layer can be grown using the PVD method. Using the PVD method, the growth substrate is a 300nm Ni film deposited by electron beam, the carbon source is CH ₄ , and the growth temperature is 1000°C. The gas is a mixture of H ₂ and Ar, and a graphene layer is grown with a thickness of 1 nm to 10 nm, and then transferred to the first hole acceleration layer 71 .

S263. Deposit the second hole acceleration layer 73 on the intermediate buffer layer 72:

Specifically, the second MgN sublayer 731 and the InGaN sublayer 732 are alternately grown, and the number of cycles is 1 to 5. The second hole acceleration layer 73 can be grown using the MOCVD method, the PVD method, or the molecular beam epitaxy (MBE) method. Taking the MOCVD method as an example, the reaction chamber temperature is controlled at 800℃~1000℃, the pressure is 100torr~500torr, _N2 and _H2 are used as carrier gases, _NH3 is used as the N source, _CP2Mg is used as the Mg source, and the second MgN is grown. Sublayer 731, with a thickness of 0.1nm~5nm; then keep the growth temperature and pressure unchanged, continue to pass in NH ₃ /N ₂ /H ₂ , turn off CP ₂ Mg, use TEGa as the Ga source, TMIn as the In source, and grow InGaN sublayers. Layer 732 has a thickness of 0.1nm~5nm.

Among them, in step S261, during the growth process of the AlInGaN sub-layer 712, the input amount of Al and the input amount of In are adjusted between each cycle, so that the Al content changes with the number of cycles of the first hole acceleration layer 71. The In content decreases with the increase of the first hole acceleration layer 71 , and the In content increases with the increase of the number of cycles of the first hole acceleration layer 71 .

S270. Deposit P-type layer 8 on insertion layer 7:

Using the MOCVD method, the reaction chamber temperature is controlled to 800℃~1000℃, the reaction chamber pressure is 100torr~300torr, NH ₃ is used as the N source, N ₂ and H ₂ are used as the carrier gas, TMGa is used as the Ga source, and CP ₂ Mg is used as the P-type dopant. Dopant, the doping concentration of Mg is 5×10 ¹⁷ cm ^-3 ~1×10 ²⁰ cm ^-3 , and a P-type layer 8 is grown. The P-type layer 8 is a P-type GaN layer doped with Mg.

Furthermore, the present invention discloses a light-emitting diode, including the above-mentioned light-emitting diode epitaxial wafer.

The present invention will be further described below in conjunction with the accompanying drawings and examples:

Example 1

The invention discloses a light-emitting diode epitaxial wafer, which includes a substrate and an epitaxial wafer stacked on the substrate. The epitaxial wafer includes an electron blocking layer and a P-type layer that are sequentially stacked along the epitaxial direction. There is a device between the electron blocking layer and the P-type layer. There is an insert layer;

The insertion layer includes a first hole acceleration layer, an intermediate buffer layer and a second hole acceleration layer that are sequentially stacked along the epitaxial direction;

The first hole accelerating layer is a superlattice structure formed by periodically growing the first MgN sublayer and the AlInGaN sublayer. The middle buffer layer is a graphene layer. The second hole accelerating layer is formed by the second MgN sublayer. A superlattice structure formed by periodically alternating growth with InGaN sublayers.

Among them, in the AlInGaN sublayer, the Al content decreases as the number of cycles of the first hole accelerating layer increases, and the In content increases as the number of cycles of the first hole accelerating layer increases.

Among them, in the AlInGaN sublayer, the Al content decreases from 0.2 to 0.03 as the number of cycles of the first hole accelerating layer increases.

Among them, the In content in the AlInGaN sublayer increases from 0.001 to 0.08 as the number of cycles of the first hole accelerating layer increases.

Among them, the In content in the InGaN sublayer is 0.08.

Among them, in the first hole accelerating layer, the thickness of a single first MgN sub-layer is 2 nm, and the thickness of a single AlInGaN sub-layer is 3 nm; in the second hole accelerating layer, the thickness of a single second MgN sub-layer is 3 nm, and the thickness of a single AlInGaN sub-layer is 3 nm. The thickness of the InGaN sub-layer is 4nm.

Among them, the number of cycles of the first hole accelerating layer is 4, and the growth temperature is 850°C; the number of cycles of the second hole accelerating layer is 4, and the growth temperature is 850°C.

Among them, the thickness of the graphene layer is 6 nm, and the graphene layer is produced by physical vapor deposition (PVD) method.

Among them, the epitaxial wafer also includes a nucleation layer, an intrinsic GaN layer, an N-type layer, and a multiple quantum well layer that are sequentially deposited on the substrate, and the electron blocking layer is deposited on the multiple quantum well layer.

Among them, the electron blocking layer is a periodic structure grown alternately by Al _y Ga _1-y N material layers and In _z Ga _1-z N material layers, where y is 0.2 and z is 0.1.

The invention discloses a method for preparing a light-emitting diode epitaxial wafer, which includes:

S100. Provide substrate;

S200. Deposit an epitaxial layer on the substrate;

The epitaxial wafer includes an electron blocking layer and a P-type layer sequentially stacked along the epitaxial direction, and an insertion layer is provided between the electron blocking layer and the P-type layer;

The insertion layer includes a first hole acceleration layer, an intermediate buffer layer and a second hole acceleration layer that are sequentially stacked along the epitaxial direction;

The first hole accelerating layer is a superlattice structure formed by periodically growing the first MgN sublayer and the AlInGaN sublayer. The middle buffer layer is a graphene layer. The second hole accelerating layer is formed by the second MgN sublayer. A superlattice structure formed by periodically alternating growth with InGaN sublayers.

Among them, the specific steps of depositing an epitaxial layer on the substrate in step S200 are as follows:

S210. Deposit a nucleation layer on the substrate: the nucleation layer is an AlGaN material layer;

S220. Deposit the intrinsic GaN layer on the nucleation layer;

S230. Deposit an N-type layer on the intrinsic GaN layer;

S240. Deposit a multi-quantum well layer on the N-type layer: the multi-quantum well layer is a periodic structure composed of InGaN quantum well layers and GaN quantum barrier layers alternately stacked;

S250. Deposit an electron blocking layer on the multiple quantum well layer;

S260. Deposit the insertion layer on the electron blocking layer:

S261. Deposit the first hole acceleration layer on the electron blocking layer:

Specifically, the first MgN sublayer and the AlInGaN sublayer are alternately grown;

S262. Deposit an intermediate buffer layer on the first hole acceleration layer:

Specifically, the middle buffer layer is a graphene layer;

S263. Deposit a second hole acceleration layer on the intermediate buffer layer:

Specifically, the second MgN sublayer and the InGaN sublayer are alternately grown.

S270. Deposit a P-type layer on the insertion layer.

Furthermore, the present invention discloses a light-emitting diode, including the above-mentioned light-emitting diode epitaxial wafer.

Example 2

The invention discloses a light-emitting diode epitaxial wafer, which includes a substrate and an epitaxial wafer stacked on the substrate. The epitaxial wafer includes an electron blocking layer and a P-type layer that are sequentially stacked along the epitaxial direction. There is a device between the electron blocking layer and the P-type layer. There is an insert layer;

The insertion layer includes a first hole acceleration layer, an intermediate buffer layer and a second hole acceleration layer that are sequentially stacked along the epitaxial direction;

The first hole accelerating layer is a superlattice structure formed by periodically growing the first MgN sublayer and the AlInGaN sublayer. The middle buffer layer is a graphene layer. The second hole accelerating layer is formed by the second MgN sublayer. A superlattice structure formed by periodically alternating growth with InGaN sublayers.

Among them, in the AlInGaN sublayer, the Al content decreases as the number of cycles of the first hole accelerating layer increases, and the In content increases as the number of cycles of the first hole accelerating layer increases.

Among them, in the AlInGaN sublayer, the Al content decreases from 0.4 to 0.01 as the number of cycles of the first hole acceleration layer increases.

Among them, the In content in the AlInGaN sublayer increases from 0.01 to 0.1 as the number of cycles of the first hole accelerating layer increases.

Among them, the In content in the InGaN sublayer is 0.05.

Among them, in the first hole accelerating layer, the thickness of a single first MgN sub-layer is 2 nm, and the thickness of a single AlInGaN sub-layer is 3 nm; in the second hole accelerating layer, the thickness of a single second MgN sub-layer is 3 nm, and the thickness of a single AlInGaN sub-layer is 3 nm. The thickness of the InGaN sub-layer is 4nm.

Among them, the number of cycles of the first hole accelerating layer is 4, and the growth temperature is 850°C; the number of cycles of the second hole accelerating layer is 4, and the growth temperature is 850°C.

Among them, the thickness of the graphene layer is 6 nm, and the graphene layer is produced by physical vapor deposition (PVD) method.

Among them, the epitaxial wafer also includes a nucleation layer, an intrinsic GaN layer, an N-type layer, and a multiple quantum well layer that are sequentially deposited on the substrate, and the electron blocking layer is deposited on the multiple quantum well layer.

Among them, the electron blocking layer is a periodic structure grown alternately by Al _y Ga _1-y N material layers and In _z Ga _1-z N material layers, where y is 0.2 and z is 0.1.

The invention discloses a method for preparing a light-emitting diode epitaxial wafer, which includes:

S100. Provide substrate;

S200. Deposit an epitaxial layer on the substrate;

The epitaxial wafer includes an electron blocking layer and a P-type layer sequentially stacked along the epitaxial direction, and an insertion layer is provided between the electron blocking layer and the P-type layer;

The insertion layer includes a first hole acceleration layer, an intermediate buffer layer and a second hole acceleration layer that are sequentially stacked along the epitaxial direction;

The first hole accelerating layer is a superlattice structure formed by periodically growing the first MgN sublayer and the AlInGaN sublayer. The middle buffer layer is a graphene layer. The second hole accelerating layer is formed by the second MgN sublayer. A superlattice structure formed by periodically alternating growth with InGaN sublayers.

Among them, the specific steps of depositing an epitaxial layer on the substrate in step S200 are as follows:

S210. Deposit a nucleation layer on the substrate: the nucleation layer is an AlGaN material layer;

S220. Deposit the intrinsic GaN layer on the nucleation layer;

S230. Deposit an N-type layer on the intrinsic GaN layer;

S240. Deposit a multi-quantum well layer on the N-type layer: the multi-quantum well layer is a periodic structure composed of InGaN quantum well layers and GaN quantum barrier layers alternately stacked;

S250. Deposit an electron blocking layer on the multiple quantum well layer;

S260. Deposit the insertion layer on the electron blocking layer:

S261. Deposit the first hole acceleration layer on the electron blocking layer:

Specifically, the first MgN sublayer and the AlInGaN sublayer are alternately grown;

S262. Deposit an intermediate buffer layer on the first hole acceleration layer:

Specifically, the middle buffer layer is a graphene layer;

S263. Deposit a second hole acceleration layer on the intermediate buffer layer:

Specifically, the second MgN sublayer and the InGaN sublayer are alternately grown.

S270. Deposit a P-type layer on the insertion layer.

Furthermore, the present invention discloses a light-emitting diode, including the above-mentioned light-emitting diode epitaxial wafer.

Example 3

The invention discloses a light-emitting diode epitaxial wafer, which includes a substrate and an epitaxial wafer stacked on the substrate. The epitaxial wafer includes an electron blocking layer and a P-type layer that are sequentially stacked along the epitaxial direction. There is a device between the electron blocking layer and the P-type layer. There is an insert layer;

The insertion layer includes a first hole acceleration layer, an intermediate buffer layer and a second hole acceleration layer that are sequentially stacked along the epitaxial direction;

The first hole accelerating layer is a superlattice structure formed by periodically growing the first MgN sublayer and the AlInGaN sublayer. The middle buffer layer is a graphene layer. The second hole accelerating layer is formed by the second MgN sublayer. A superlattice structure formed by periodically alternating growth with InGaN sublayers.

Among them, in the AlInGaN sublayer, the Al content remains constant and the Al content is 0.2.

Among them, the In content in the AlInGaN sublayer remains constant, and the In content is 0.001.

Among them, the In content in the InGaN sublayer is 0.08.

Among them, in the first hole accelerating layer, the thickness of a single first MgN sub-layer is 2 nm, and the thickness of a single AlInGaN sub-layer is 3 nm; in the second hole accelerating layer, the thickness of a single second MgN sub-layer is 3 nm, and the thickness of a single AlInGaN sub-layer is 3 nm. The thickness of the InGaN sub-layer is 4nm.

Among them, the number of cycles of the first hole accelerating layer is 4, and the growth temperature is 850°C; the number of cycles of the second hole accelerating layer is 4, and the growth temperature is 850°C.

Among them, the thickness of the graphene layer is 6 nm, and the graphene layer is produced by physical vapor deposition (PVD) method.

Among them, the epitaxial wafer also includes a nucleation layer, an intrinsic GaN layer, an N-type layer, and a multiple quantum well layer that are sequentially deposited on the substrate, and the electron blocking layer is deposited on the multiple quantum well layer.

Among them, the electron blocking layer is a periodic structure grown alternately by Al _y Ga _1-y N material layers and In _z Ga _1-z N material layers, where y is 0.2 and z is 0.1.

The invention discloses a method for preparing a light-emitting diode epitaxial wafer, which includes:

S100. Provide substrate;

S200. Deposit an epitaxial layer on the substrate;

The epitaxial wafer includes an electron blocking layer and a P-type layer sequentially stacked along the epitaxial direction, and an insertion layer is provided between the electron blocking layer and the P-type layer;

The insertion layer includes a first hole acceleration layer, an intermediate buffer layer and a second hole acceleration layer that are sequentially stacked along the epitaxial direction;

The first hole accelerating layer is a superlattice structure formed by periodically growing the first MgN sublayer and the AlInGaN sublayer. The middle buffer layer is a graphene layer. The second hole accelerating layer is formed by the second MgN sublayer. A superlattice structure formed by periodically alternating growth with InGaN sublayers.

Among them, the specific steps of depositing an epitaxial layer on the substrate in step S200 are as follows:

S210. Deposit a nucleation layer on the substrate: the nucleation layer is an AlGaN material layer;

S220. Deposit the intrinsic GaN layer on the nucleation layer;

S230. Deposit an N-type layer on the intrinsic GaN layer;

S240. Deposit a multi-quantum well layer on the N-type layer: the multi-quantum well layer is a periodic structure composed of InGaN quantum well layers and GaN quantum barrier layers alternately stacked;

S250. Deposit an electron blocking layer on the multiple quantum well layer;

S260. Deposit the insertion layer on the electron blocking layer:

S261. Deposit the first hole acceleration layer on the electron blocking layer:

Specifically, the first MgN sublayer and the AlInGaN sublayer are alternately grown;

S262. Deposit an intermediate buffer layer on the first hole acceleration layer:

Specifically, the middle buffer layer is a graphene layer;

S263. Deposit a second hole acceleration layer on the intermediate buffer layer:

Specifically, the second MgN sublayer and the InGaN sublayer are alternately grown.

S270. Deposit a P-type layer on the insertion layer.

Furthermore, the present invention discloses a light-emitting diode, including the above-mentioned light-emitting diode epitaxial wafer.

Comparative example 1

The difference between this comparative example and Example 1 is that the insertion layer in this comparative example does not contain an intermediate buffer layer, and the preparation method of the epitaxial wafer does not include a growth step of the intermediate buffer layer.

Comparative example 2

The difference between this comparative example and Embodiment 1 is that the first hole acceleration layer of the insertion layer in this comparative example adopts the same structure as the second hole acceleration layer, specifically:

The first hole accelerating layer is a superlattice structure formed by periodically growing the second MgN sublayer and the InGaN sublayer. The number of periods is 4. In the first hole accelerating layer, a single second MgN sublayer The thickness is 3nm, and the thickness of a single InGaN sub-layer is 4nm.

Comparative example 3

The difference between this comparative example and Example 1 is that the insertion layer in this comparative example does not contain a second hole accelerating layer, and the method for preparing the epitaxial wafer does not include a growth step of the second hole accelerating layer.

Comparative example 4

The difference between this comparative example and Embodiment 1 is that this comparative example does not provide an insertion layer.

Performance Testing:

Test samples: Example 1~Example 3, Comparative Example 1~Comparative Example 4

Test Methods:

(1) Surface roughness test:

AFM equipment was used to test the surface roughness (rms) of the epitaxial wafers of each experimental group;

(2) Brightness and antistatic performance test:

The epitaxial wafers of each experimental group were processed into 10×24mil LED chips with a vertical structure, and their antistatic capabilities and luminous brightness were tested;

1) Brightness test: Test the luminous intensity of the resulting chip when the current is 120mA;

2) Antistatic performance test: Use an electrostatic meter to test the antistatic performance of the base chip under the HBM (Human Body Discharge Model) model to test the passing ratio of the chip that can withstand reverse 8000V static electricity.

The test results are shown in the table below:

The above descriptions are only preferred embodiments of the present invention, and do not limit the present invention in any form. Although the present invention has been disclosed above in preferred embodiments, it is not intended to limit the present invention. Any person familiar with the technology in the art Without departing from the scope of the technical solution of the present invention, personnel can make some changes or modify the above-mentioned technical contents into equivalent embodiments with equivalent changes. In essence, any simple modifications, equivalent changes and modifications made to the above embodiments still fall within the scope of the present invention.

Claims (7)

1. The epitaxial wafer of the light-emitting diode comprises a substrate and an epitaxial wafer which is laminated on the substrate, and is characterized in that the epitaxial wafer comprises an electron blocking layer and a P-type layer which are laminated in sequence along the epitaxial direction, and an inserting layer is arranged between the electron blocking layer and the P-type layer;

the insertion layer comprises a first hole acceleration layer, an intermediate buffer layer and a second hole acceleration layer which are sequentially laminated along the epitaxial direction;

the first hole acceleration layer is a superlattice structure formed by periodically and alternately growing a first MgN sub-layer and an AlInGaN sub-layer, the middle buffer layer is a graphene layer, and the second hole acceleration layer is a superlattice structure formed by periodically and alternately growing a second MgN sub-layer and an InGaN sub-layer;

the Al content In the AlInGaN sub-layer decreases with the increase of the cycle number of the first hole acceleration layer, and the In content increases with the increase of the cycle number of the first hole acceleration layer; the Al content in the AlInGaN sub-layer decreases from a to b along with the increase of the cycle number of the first hole acceleration layer, wherein a is more than or equal to 0.1 and less than or equal to 0.4, and b is more than or equal to 0.01 and less than or equal to 0.05;

in content In the AlInGaN sub-layer increases from c to d along with the increase of the cycle number of the first hole acceleration layer, wherein, c is more than 0 and less than 0.05,0.05, and d is more than or equal to 0.1.

2. The light-emitting diode epitaxial wafer of claim 1, wherein In content In the InGaN sublayer is 0.05-0.1.

3. The light emitting diode epitaxial wafer of claim 1, wherein in the first hole acceleration layer, the thickness of a single first MgN sub-layer is 0.1nm to 5nm, and the thickness of a single AlInGaN sub-layer is 0.1nm to 5nm; in the second hole acceleration layer, the thickness of a single second MgN sub-layer is 0.1 nm-5 nm, and the thickness of a single InGaN sub-layer is 0.1 nm-5 nm.

4. The light-emitting diode epitaxial wafer according to claim 1, wherein the number of cycles of the first hole acceleration layer is 1 to 5, and the growth temperature is 800 ℃ to 1000 ℃; the number of cycles of the second hole acceleration layer is 1-5, and the growth temperature is 800-1000 ℃.

5. The light-emitting diode epitaxial wafer of claim 1, wherein the graphene layer has a thickness of 1 nm-10 nm and is prepared by a physical vapor deposition method.

6. A method for producing the light-emitting diode epitaxial wafer according to any one of claims 1 to 5, characterized by comprising:

providing a substrate;

depositing an epitaxial layer on the substrate;

the epitaxial wafer comprises an electron blocking layer and a P-type layer which are sequentially laminated along the epitaxial direction, and an inserting layer is arranged between the electron blocking layer and the P-type layer;

the insertion layer comprises a first hole acceleration layer, an intermediate buffer layer and a second hole acceleration layer which are sequentially laminated along the epitaxial direction;

the first hole acceleration layer is a superlattice structure formed by periodically and alternately growing a first MgN sub-layer and an AlInGaN sub-layer, the middle buffer layer is a graphene layer, and the second hole acceleration layer is a superlattice structure formed by periodically and alternately growing a second MgN sub-layer and an InGaN sub-layer.

7. A light-emitting diode, characterized by comprising the light-emitting diode epitaxial wafer according to any one of claims 1 to 5.