CN116130448A - Electronic package and package substrate thereof - Google Patents

Abstract

The invention provides an electronic package and a package substrate thereof. The electronic package comprises a package substrate, a first insulating layer is arranged on the die-placing side of the package substrate, and a second insulating layer is arranged on the external side of the package substrate, so that the thermal expansion coefficient of the first insulating layer is larger than that of the second insulating layer, and the expansion and contraction amount of the first insulating layer on the die-placing side can be used for adjusting the warping degree of the package substrate so as to reduce the warping deformation amount of the package substrate.

Description

Electronic package and its packaging substrate

technical field

The invention relates to a semiconductor package, in particular to a package substrate with embedded traces and an electronic package made thereafter.

Background technique

With the vigorous development of the electronic industry, electronic products tend to be thinner and smaller in form, and are developing toward high-performance, high-function, and high-speed research and development in terms of function. Therefore, in order to meet the requirements of high integration and miniaturization of semiconductor devices, packaging substrates with high-density and fine-pitch circuits are often used in the packaging process.

As shown in FIG. 1A, the conventional package substrate 1a includes a core layer 10 having a plurality of conductive columns 100, a plurality of dielectric layers 11 respectively disposed on opposite sides of the core layer 10, and a plurality of dielectric layers 11 disposed on each of the dielectric layers 11. The circuit layers 12 on the upper core layer 10 are electrically connected to the circuit layers 12 on opposite sides of the core layer 10 through the plurality of conductive pillars 100 .

However, the existing packaging substrate 1a includes a core layer 10, so it is difficult to meet the requirements of lightness, thinness and shortness. Therefore, a packaging substrate 1b without a core layer (coreless) embodiment is developed, as shown in FIG. 1B, which includes multiple stacked The dielectric layer 11 and the circuit layer 12 disposed on each of the dielectric layers 11 .

However, in the existing packaging substrate 1b, the material and thickness of each of the dielectric layers 11 are the same, so during the packaging process, when the packaging substrate 1 is subjected to a temperature cycle (temperature cycle), it is easy to warp due to the thickness being too thin. warpage, resulting in non-wetting problems in the subsequent placement of semiconductor chips or circuit boards, resulting in poor electrical connections.

On the other hand, if the thickness of the dielectric layer 11 is increased, although the warpage can be alleviated, the thickness of the package substrate 1 b will be increased, so that it cannot meet the requirement of lightness, thinness and compactness.

Therefore, how to overcome the various problems of the above-mentioned prior art has become an urgent problem to be solved at present.

Contents of the invention

In view of the various defects of the above-mentioned prior art, the object of the present invention is to provide an electronic package and its package substrate, which can reduce the warping deformation of the package substrate.

The packaging substrate of the present invention includes: a first insulating portion comprising at least one first insulating layer; a second insulating portion comprising at least one second insulating layer, which is stacked on the first insulating portion to form an insulating structure , and the insulating structure has opposite crystal placement side and outer connection side, so that the first insulating layer is correspondingly disposed on the crystal placement side, and the second insulating layer is correspondingly disposed on the outer connection side, wherein the first insulating portion The coefficient of thermal expansion is greater than the coefficient of thermal expansion of the second insulating part; and the circuit layer is embedded in the first insulating part and the second insulating part.

In the aforementioned packaging substrate, the second insulating portion has a plurality of second insulating layers. For example, the coefficients of thermal expansion of at least two of the plurality of second insulating layers are the same or different. Alternatively, the coefficients of thermal expansion of the plurality of second insulating layers decrease or increase towards the outer side.

In the aforementioned packaging substrate, the material forming the first insulating layer is an Ajinomoto build-up film.

In the aforementioned packaging substrate, the material forming the second insulating layer is a prepreg.

In the aforementioned packaging substrate, the thicknesses of the first insulating layer and the second insulating layer are the same or different.

The aforementioned packaging substrate further includes an insulating protection layer disposed on the first and/or second insulating portion and exposing part of the circuit layer.

The present invention also provides an electronic package, comprising: the aforementioned package substrate; and an electronic component, which is disposed on the die-mounting side and electrically connected to the circuit layer.

In the aforementioned electronic package, a plurality of conductive elements electrically connected to the circuit layer are disposed on the external side.

It can be seen from the above that the packaging substrate of the present invention mainly uses the coefficient of thermal expansion of the first insulating layer to be greater than that of the second insulating layer, so that the expansion and contraction of the first insulating layer on the side where the die is placed can be used to adjust the package. The degree of warpage of the substrate, so compared with the prior art, the packaging substrate of the present invention does not need to increase the thickness of the insulating layers, and can reduce the deformation of the packaging substrate warping, thus not only improving the product yield, but also Meet the needs of thin and light.

Description of drawings

FIG. 1A is a schematic cross-sectional view of a conventional packaging substrate.

FIG. 1B is a schematic cross-sectional view of another conventional packaging substrate.

FIG. 2A is a schematic cross-sectional view of the packaging substrate of the present invention.

2B is a schematic cross-sectional view of the electronic package of the present invention.

FIG. 3 is a schematic cross-sectional view of another embodiment of the packaging substrate of the present invention.

The reference signs are as follows:

1a, 1b, 2, 3: package substrate

10: Core layer

100: Conductive column

11: Dielectric layer

12,20: line layer

2a, 3a: first insulating part

2b: Second insulating part

20a: crystal side

20b: External side

201: Conductive trace

202: Conductive blind hole

203: Electrical connection pad

204: welding pad

21: The first insulating layer

22,23,24,25: second insulating layer

26a: the first insulation protection layer

26b: the second insulation protection layer

30: Semiconductor chip

30a: Action surface

30b: Non-active surface

300: electrode pad

31: Conductive bump

32: Conductive element

t: thickness

Detailed ways

The implementation of the present invention will be described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification.

It should be noted that the structures, proportions, sizes, etc. shown in the drawings attached to this specification are only used to match the content disclosed in the specification for the understanding and reading of those skilled in the art, and are not intended to limit the implementation of the present invention. Limiting conditions, so there is no technical substantive meaning, any modification of structure, change of proportional relationship or adjustment of size, without affecting the effect and purpose of the present invention, should still fall within the scope of the present invention. The disclosed technical content must be within the scope covered. At the same time, terms such as "above", "first", "second" and "one" quoted in this specification are only for the convenience of description and are not used to limit the scope of the present invention. The change or adjustment of the relative relationship shall also be regarded as the implementable scope of the present invention without substantive change of the technical content.

FIG. 2A is a schematic cross-sectional view of the packaging substrate 2 of the present invention. As shown in FIG. 2A, the packaging substrate 2 is a coreless embodiment, which includes: a first insulating portion 2a, a second insulating portion 2b stacked on the first insulating portion 2a, and at least A circuit layer 20, and the first insulating part 2a includes at least one first insulating layer, and the second insulating part 2b includes at least one second insulating layer. In this embodiment, it has a layer of first insulating layer 21 and Four layers of second insulating layers 22 , 23 , 24 , 25 are stacked to form an insulating structure.

The first insulating part 2a is used as the crystal side 20a of the insulating structure, and the second insulating part 2b is used as the outer side 20b of the insulating structure, that is, the first insulating layer 21 is correspondingly arranged on the crystal side 20a, The second insulating layers 22, 23, 24, 25 are correspondingly disposed on the outer side 20b, wherein the coefficient of thermal expansion (such as at least 4ppm/°C) of the first insulating portion 2a (or the first insulating layer 21) is greater than that of the first insulating layer 2a. The thermal expansion coefficient of the second insulating part 2b (or the plurality of second insulating layers 22, 23, 24, 25) (eg, at most 2ppm/°C).

In this embodiment, the second insulating portion 2b has a plurality of second insulating layers 22, 23, 24, 25, whose coefficients of thermal expansion may be the same or different, but they are all smaller than the first insulating portion 2a (or the first The thermal expansion coefficient of the insulating layer 21). For example, the CTEs of the plurality of second insulating layers 22, 23, 24, 25 may decrease or increase towards the outer side 20b.

Furthermore, the material for forming the first insulating layer 21 is Ajinomoto Build-up Film (ABF for short) or other high CTE dielectric materials, and the second insulating layers 22, 23, 24 are formed. , 25 is made of a material such as prepreg (PP for short) or other low CTE dielectric materials.

In addition, the packaging substrate 2 may include an insulating protection layer such as a solder resist layer, which is disposed on the first and second insulating portions 2a, 2b and exposes the circuit layer 20, so that the circuit layer 20 can be combined with other components. For example, the first insulating protection layer 26a is disposed on the first insulating layer 21 and exposes part of the surface of the circuit layer 20, and the second insulating protection layer 26b is disposed on the second insulating layer 25 and exposes the circuit layer. 20 parts of the surface.

In addition, the thickness t of the first insulating layer 21 and the second insulating layer 22, 23, 24, 25 can be adjusted according to requirements, and the thickness t of each insulating layer can be the same or different, and the number of insulating layers can be Odd number or even number is not particularly limited.

The circuit layer 20 is embedded in the first insulating layer 21 and the second insulating layer 22, 23, 24, 25, and includes a plurality of conductive traces 201 and conductive traces electrically connected to each layer. 201 of the conductive blind via 202 . In other words, each of the conductive traces 201 and the conductive blind vias 202 does not protrude from the first insulating layer 21 and the second insulating layer 22 , 23 , 24 , 25 that embed them.

In this embodiment, the circuit layer 20 is provided with a plurality of electrical connection pads 203 corresponding to the side 20a, and a plurality of welding pads 204 are arranged corresponding to the outer side 20b, so that a plurality of electrical connections The connection pads 203 are exposed on the first insulating protection layer 26a, and the plurality of welding pads 204 are exposed on the second insulating protection layer 26b.

Therefore, in the packaging substrate 2 of the present invention, the thermal expansion coefficient of the first insulating layer 21 is greater than the thermal expansion coefficient of the second insulating layers 22, 23, 24, 25, so in the packaging process, the packaging substrate 2 will The expansion and contraction of the first insulating layer 21 and the second insulating layer 22, 23, 24, 25 are different, so as to adjust the warping direction and balance the warping degree of the packaging substrate 2 (for example, the packaging substrate 2 can reduce the figure The amount of warpage shown in 1B is 10% to 60%), so that the package substrate 2 can greatly reduce the degree of warpage during the temperature rise and fall.

Furthermore, since the warping of the packaging substrate 2 is greatly reduced, the conductive traces 201 will not be too close due to warping, so the circuit layer 20 is conducive to the design of fine pitches/fine lines, so the conductive blind The holes 202 , the electrical connection pads 203 and the welding pads 204 can be designed as fine-pitch/thin-line specifications according to requirements, so as to meet the requirements of high-density contacts of semiconductor chips.

In addition, since the circuit layer 20 can meet the requirements of fine pitch/fine circuit, under the same amount of wiring, the amount of metal material used to make the circuit layer 20 in the package substrate 2 is less than that used in the conventional package substrate 1b. The amount of metal material used in the circuit layer 12 can reduce the manufacturing cost of the packaging substrate 2 .

In addition, since the dielectric material with a larger CTE is relatively cheap, choosing a dielectric material with a larger CTE as the first insulating layer 21 at the die placement side 20 a can also effectively reduce the manufacturing cost of the packaging substrate 2 .

As shown in FIG. 2B , in subsequent applications, the package substrate 2 can be bonded to at least one semiconductor chip 30 on the plurality of electrical connection pads 203 , and bonded to the plurality of solder pads 204 such as solder balls or other metal bumps. The conductive elements 32 are used to form an electronic package, and the electronic package is connected to a circuit board (not shown) by a plurality of conductive elements 32 .

The electronic component 30 is an active component, a passive component or a combination thereof, wherein the active component is, for example, a semiconductor chip, and the passive component is, for example, a resistor, a capacitor, and an inductor.

In this embodiment, the electronic component 30 is a semiconductor chip, which has an opposite active surface 30a and a non-active surface 30b. There are a plurality of electrode pads 300 on the active surface 30a, and the electronic component 30 is borrowed by its electrode pads 300. A plurality of conductive bumps 31 are flip-chip bonded and electrically connected to the electrical connection pad 203, and then a primer (not shown) is formed between the electronic component 30 and the die side 20a to cover a plurality of conductive The bump 31 ; or, the electrode pad 300 of the electronic component 30 can be electrically connected to the electrical connection pad 203 through a plurality of bonding wires (not shown). Alternatively, the electrode pad 300 of the electronic component 30 can directly contact the electrical connection pad 203 without the first insulating protection layer 26a. However, the manner in which the electronic component 30 is electrically connected to the circuit layer 20 is not limited to the above.

The conductive element 32 is electrically connected to the circuit layer 20 and the circuit board.

FIG. 3 is a schematic cross-sectional view of another embodiment of the package substrate 3 of the present invention. As shown in FIG. 3 , the packaging substrate 3 of this embodiment is a coreless embodiment, and its first insulating portion 3 a includes a plurality of stacked first insulating layers 21 .

Therefore, in the package substrate 3 of the present invention, the coefficient of thermal expansion of the first insulating portion 3a is greater than the coefficient of thermal expansion of the second insulating portion 2b, so during the packaging process, when the package substrate 3 is in temperature cycle, the first insulating portion The expansion and contraction of the second insulating portion 3a and the second insulating portion 2b are different, so as to adjust the warping direction and balance the warping degree of the packaging substrate 3, so that the packaging substrate 3 can greatly reduce the warping degree during the temperature rise and fall process.

Furthermore, since the warpage of the packaging substrate 3 is greatly reduced, the conductive traces 201 will not be too close to each other due to the warpage, so the circuit layer 20 is conducive to the design of fine pitches/fine lines to meet the needs of semiconductor chips. The demand for high-density contacts.

In addition, since the circuit layer 20 can meet the requirements of fine pitch/fine circuit, under the same amount of wiring, the amount of metal material used to make the circuit layer 20 in the package substrate 3 is less than that used in the conventional package substrate 1b. The amount of metal material used in the circuit layer 12 can reduce the manufacturing cost of the packaging substrate 3 .

In addition, since the dielectric material with a larger CTE is relatively cheap, choosing a dielectric material with a larger CTE as the first insulating portion 2 a at the die placement side 20 a can also effectively reduce the manufacturing cost of the packaging substrate 3 .

It should be understood that the number of layers of the first insulating part and the number of layers of the second insulating part can be configured according to requirements, and there is no special limitation.

To sum up, in the package substrate of the present invention, the thermal expansion coefficient of the first insulating part is greater than that of the second insulating part, so that the expansion and contraction of the first insulating part on the die placement side can be used to adjust the packaging The degree of warpage of the substrate, so compared with the prior art, the packaging substrate of the present invention does not need to increase the thickness of the insulating layers, and can reduce the deformation of the packaging substrate warping, thus not only improving the product yield, but also Meet the needs of thin and light.

The above-mentioned embodiments are only used to illustrate the principles and effects of the present invention, but not to limit the present invention. Those skilled in the art can modify the above embodiments without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be listed in the claims.

Claims (10)

1. A package substrate, comprising:

a first insulating portion including at least a first insulating layer;

the second insulating part comprises at least one second insulating layer, is overlapped on the first insulating part to form an insulating structure, and is provided with a crystal placement side and an external side which are opposite to each other, so that the first insulating layer is correspondingly arranged on the crystal placement side, and the second insulating layer is correspondingly arranged on the external side, wherein the thermal expansion coefficient of the first insulating part is larger than that of the second insulating part; and

and a circuit layer embedded in the first insulating portion and the second insulating portion.

2. The package substrate of claim 1, wherein the second insulating portion has a plurality of the second insulating layers.

3. The package substrate of claim 2, wherein the coefficients of thermal expansion of at least two of the plurality of second insulating layers are the same or different.

4. The package substrate of claim 2, wherein the coefficients of thermal expansion of the plurality of second insulating layers decrease or increase toward the external side.

5. The package substrate of claim 1, wherein the first insulating layer is a material of a flavor enhancement film.

6. The package substrate of claim 1, wherein the second insulating layer is formed of a prepreg.

7. The package substrate of claim 1, wherein the first insulating layer and the second insulating layer have the same or different thicknesses.

8. The package substrate of claim 1, further comprising an insulating protective layer disposed on the first and/or second insulating portions and exposing a portion of the circuit layer.

9. An electronic package, comprising:

the package substrate of claim 1; and

the electronic element is arranged on the crystal placing side and is electrically connected with the circuit layer.

10. The electronic package of claim 9, wherein a plurality of conductive elements electrically connected to the circuit layer are disposed on the external side.

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