CN111755409A - Semiconductor packaging substrate and its manufacturing method and electronic package and its manufacturing method - Google Patents

Abstract

A method for preparing semiconductor package substrate includes forming solder-proof structure with open hole on circuit structure to expose circuit structure to open hole for forming cup-shaped soldering seat on exposed circuit layer and hole wall of open hole.

Description

Semiconductor packaging substrate and its manufacturing method and electronic package and its manufacturing method

technical field

The invention relates to a packaging substrate, in particular to a semiconductor packaging substrate and an electronic package thereof which can improve product reliability.

Background technique

With the development of industrial applications, in recent years, it has gradually moved towards the trend of packaging specifications for large-scale chips such as artificial intelligence (AI) chips, high-end chips or stacked chips, such as 3D or 2.5D IC processes, to be applied to high-end chips. High-end products such as artificial intelligence (AI) chips, GPUs, etc., with dense lines/high transmission speed/high stack count/large size design.

Therefore, the industry has switched to flip-chip packaging substrates with large-sized boards, such as 40*40, 70*70 or other thicker and larger-structure board types, to carry artificial intelligence (AI) chips, high-end chips or Large-sized chips such as stacked chips.

As shown in FIG. 1A , the electronic device 1 includes: a circuit board 18 , a package substrate 1 a disposed on the circuit board 18 , and a semiconductor chip 19 bonded to the package substrate 1 a . Specifically, as shown in FIG. 1B , the package substrate 1 a includes a core layer 10 , a circuit build-up portion 11 disposed on the core layer 10 , and solder resist layers 12 a and 12 b disposed on the circuit build-up portion 11 , And the solder mask layers 12a, 12b are exposed to the outermost circuit layers of the circuit build-up portion 11 for serving as contacts (ie, I/O) 11a, 11b, so as to be placed on the upper side (as shown in FIG. 1C ). The semiconductor chip 19 is connected with the solder bumps 13a and the circuit board 18 is connected with the solder balls 13b on the lower side (the ball-mounted side or BGA as shown in FIG. 1D ) to form an electronic package product.

In the production of the known core layer 10, a substrate composed of glass fiber and epoxy resin, such as BT (Bismaleimide Triazine), FR4 or FR5, is used, and then a via process is performed on it, such as mechanical drilling, laser Hole-forming steps such as drilling or double-tapered blind holes, and then electroplating in the holes to form conductive materials and fill resin (plugin). In addition, the build-up method of the line build-up portion 11 also uses an ABF type material as the dielectric layer, and the material of the solder resist layers 12a, 12b is selected to use materials such as green paint or ink.

However, the metal contact surface of the known solder ball 13b and the contact 11b is only a single surface (such as the top surface of the contact 11b), so the metal contact surface is actively small, so that the solder ball 13b is prone to break at the contact 11b, or even Dropped or dropped balls due to poor bonding (such as the top surface of the solder ball 13").

In addition, as shown in FIG. 1A , when the packaging substrate 1 a is applied to a large size in the packaging process of the conventional electronic device 1 , the rigidity of the packaging substrate 1 a is insufficient, resulting in high temperature packaging process, because the packaging substrate 1 a is in each The coefficient of thermal expansion (CTE) of the interlayer materials is inconsistent and warpage occurs, resulting in poor connection with the semiconductor chip 19 (for example, the solder material 13' is not joined), or when soldering , there will be poor connection between it and the circuit board 18 (for example, the solder balls 13 ″ are not joined), and more seriously, the semiconductor chip 19 itself may be electrically failed or broken due to stress.

On the other hand, if the thickness of the core layer 10 is increased to increase the rigidity of the package substrate 1a and reduce the warping degree of the package substrate 1a, other disadvantages will occur, for example, the thickness of the core layer 10 will be increased. This method does not meet the needs of thinning or miniaturized package design. Specifically, in order to prevent the packaging substrate 1a from warping, and further increase the thickness of the core layer 10, the entire packaging substrate 1a becomes thicker, which is not conducive to the manufacture of the substrate and increases the processing cost.

Therefore, how to overcome the above-mentioned various problems of the prior art has actually become a difficult problem to be overcome in the current industry.

SUMMARY OF THE INVENTION

In view of the above-mentioned defects of the prior art, the present invention provides a semiconductor package substrate and a manufacturing method thereof, an electronic package and a manufacturing method thereof, which can effectively prevent the solder balls from breaking or falling off.

The semiconductor package substrate of the present invention includes a circuit structure, a solder resist structure and a solder seat. The circuit structure has a circuit layer; the solder mask structure is arranged on the circuit structure, and the solder mask structure has an opening, so that the circuit layer is partially exposed to the opening; the solder seat is a cup-shaped structure, which is formed by electroplating and is self-contained. The exposed surface of the circuit layer extends to the hole wall of the opening, and the material of the solder pad is the same as that of the circuit layer, such as copper.

The present invention also provides a method for manufacturing a semiconductor package substrate, which includes: providing a circuit structure with a circuit layer; forming a solder mask structure on the circuit structure, and forming an opening in the solder mask structure to make the circuit layer part is exposed in the opening; and a solder pad is formed on the exposed circuit layer and the hole wall of the opening.

In the aforementioned semiconductor package substrate and its manufacturing method, the solder resist structure is a single insulating layer.

In the aforesaid manufacturing method, the soldering seat has a cup-shaped structure, which is formed from the exposed surface of the circuit layer by electroplating and extends to the hole wall of the opening. The material of the soldering seat is the same as that of the circuit layer, such as copper .

In the aforementioned semiconductor package substrate and its manufacturing method, the solder mask structure further includes a metal support layer and an insulating layer covering the metal support layer, and the metal support layer is combined with the circuit structure by a bonding material.

In the aforementioned semiconductor package substrate and its manufacturing method, a conductive element disposed on the soldering seat is also included.

The aforementioned semiconductor package substrate and the manufacturing method thereof further include a conducting block disposed on the soldering seat, and the conducting block is a solder ball with an area smaller than that of the opening.

In the aforementioned semiconductor package substrate and its manufacturing method, a bump bottom with an appropriate thickness is formed at the contact portion between the solder pad and the circuit layer.

The present invention also provides an electronic package, comprising the aforementioned semiconductor package substrate and electronic components. Wherein, the circuit structure has opposite first side and second side, and the circuit layer is arranged on the first side and the second side, and the solder mask structure is arranged on the second side of the circuit structure; electronic component , which is arranged on the first side of the circuit structure and is electrically connected to the circuit layer on the first side of the circuit structure.

The present invention further provides a method for manufacturing an electronic package, comprising: providing the aforementioned semiconductor package substrate, wherein the circuit structure has a first side and a second side opposite to each other, and the circuit layer is disposed on the first side and the second side. and disposing the solder mask structure on the second side of the circuit structure; and disposing an electronic component on the first side of the circuit structure, and the electronic component is electrically connected to the first side of the circuit structure circuit layer.

The aforementioned electronic package and its manufacturing method further include an encapsulation layer disposed on the semiconductor package substrate to combine the electronic element and the semiconductor package substrate.

In the aforementioned electronic package and its manufacturing method, the electronic component is disposed on the first side of the circuit structure with a plurality of conductive bumps.

As can be seen from the above, the semiconductor package substrate and its manufacturing method and the electronic package and its manufacturing method of the present invention are mainly due to the exposed circuit layer and the soldering seat formed on the hole wall of the opening of the solder mask structure, so as to increase the The metal contact area of the conductive element improves the bonding force between the conductive element (solder ball) and the solder seat. Therefore, compared with the known technology, the present invention can effectively prevent the conductive element from breaking, and can also avoid the occurrence of falling balls or falling off. Happening.

Description of drawings

FIG. 1A is a schematic cross-sectional view of a conventional electronic device.

FIG. 1B is a schematic cross-sectional view of a conventional flip-chip packaging substrate.

FIG. 1C is a schematic top view of FIG. 1B .

FIG. 1D is a schematic bottom view of FIG. 1B .

2A to 2B are schematic cross-sectional views of a method for manufacturing a semiconductor package substrate according to a first embodiment of the present invention.

2C is a schematic cross-sectional view of the first embodiment of the electronic package of the present invention.

3A to 3C are schematic cross-sectional views of a method for manufacturing a semiconductor package substrate according to a second embodiment of the present invention.

Fig. 3A' is another mode of Fig. 3A.

Fig. 3C' and Fig. 3C" are other embodiments of Fig. 3C.

3D is a schematic cross-sectional view of the second embodiment of the electronic package of the present invention.

Fig. 3D' is another embodiment of Fig. 3D.

The reference numbers are as follows:

1 Electronic device

1a Package substrate

10 core layers

11 Line build-up section

11a, 11b contacts

12a, 12b Soldermask

13a Solder bumps

13b, 13” solder balls

13' Solder Material

18 circuit boards

19 Semiconductor chips

2,3 Semiconductor packaging substrate

2a Line structure

20 core layer

20a First side

20b Second side

200 Conductive part

21 Build-up Department

210 Dielectric layer

211 Line layer

212 pads

22a, 22b, 32a, 32b Solder mask structure

220 opening

23,36,36’ Solder Socket

32 Insulation layer

320 Second opening

33 Metal Support Layer

330 first opening

34 Bonding material

361’ bump bottom

37 Lead block

4,4’,4” Electronic Package

40 Electronic Components

400 conductive bumps

41 Encapsulation layer

42 Conductive elements.

Detailed ways

The embodiments of the present invention are described below by means of specific specific embodiments, and those skilled in the art can easily understand other advantages and technical effects of the present invention from the contents disclosed in this specification.

It should be noted that the structures, proportions, sizes, etc. shown in the accompanying drawings of this specification are only used to cooperate with the contents disclosed in the specification, and are not used to limit the conditions for the implementation of the present invention with the understanding and reading of those skilled in the art. Therefore, without technical substantive significance, any structural modification, proportional relationship change or size adjustment, without affecting the technical effect that the present invention can produce and the achievable purpose, should still fall within the scope of the disclosure of the present invention. The technical content must be able to cover the scope. At the same time, the terms such as "above", "first", "second" and "one" quoted in this specification are only for the convenience of description and clarity, and are not used to limit the scope of the present invention. Changes or adjustments of their relative relationships, without substantial changes to the technical content, should be regarded as the scope of the present invention.

2A to 2B are schematic cross-sectional views of the manufacturing method of the semiconductor package substrate 2 according to the first embodiment of the present invention.

As shown in FIG. 2A, a circuit structure 2a is provided, the circuit structure 2a has opposite first sides 20a and second sides 20b, both sides can be used for placing electronic components (such as semiconductor chips, passive components, etc.), and The external side on which the semiconductor chip is placed is referred to as the die placement side, so for the convenience of the following description, the first side 20a is referred to as the die placement side.

In this embodiment, the circuit structure 2a has a core layer 20 in which a plurality of conductive parts 200 are formed. For example, the material for forming the core layer 20 is a base material containing glass fiber and organic resin, such as BT (Bismaleimide Triazine), FR4 or FR5, etc., or a high rigidity material without glass fiber but containing filler (such as SiO ₂ ) the organic substrate, and then perform a via hole process on it, such as a hole forming step such as mechanical drilling or laser drilling, and form a conductive material in the hole. Or, in another embodiment, the material for forming the core layer 20 is an organic insulating material, and the organic insulating material may be ABF (Ajinomoto Build-up Film), a prepreg with or without glass fiber, Molding compound (Molding Compound), such as the core substrate formed by epoxy molding compound (Epoxy Molding Compound, referred to as EMC), preferably, EMC with high rigidity and low coefficient of thermal expansion (CTE) is used, at this time, the conductive portion 200 can be made of A single conductive column or a plurality of conductive columns stacked in contact with each other.

In addition, the circuit structure 2 a further includes a build-up portion 21 disposed on the core layer 20 , which has at least one dielectric layer 210 and a plurality of circuit layers 211 combined with the dielectric layer 210 . For example, the dielectric layer 210 may be formed of liquid epoxy resin, film ABF, prepreg, embossing resin (EMC) or photosensitive resin. It should be understood that the layout layers of the circuit layer 211 can be designed according to requirements.

In addition, an insulating layer with a plurality of openings 220 can be formed on the build-up portion 21 of the circuit structure 2a to serve as the solder mask structure 22a and the solder mask structure 22b, and the outermost circuit of the circuit structure 2a can be formed The layer 211 is exposed to the plurality of openings 220 for serving as the bonding pads 212 . Specifically, the material for forming the solder resist structure 22a and the solder resist structure 22b can be graphene, ink, green paint, ABF or non-photosensitive dielectric material (eg EMC) or other suitable materials, which are not particularly limited.

In addition, in other embodiments, the core layer 20 can be changed to a silicon substrate, so that the build-up portion 21 is disposed on the silicon substrate, so that the circuit structure 2a is in the form of a silicon interposer. Alternatively, in other embodiments, the circuit structure 2a may be in a coreless form.

As shown in FIG. 2B , solder pads 23 are formed on the solder pads 212 on the second side 20b of the circuit structure 2a and on the hole walls of the openings 220 of the solder mask structure 22b.

In this embodiment, the material for forming the soldering seat 23 is the same as the material for the soldering pad 212 , such as copper material. For example, it is formed on the surface of the exposed pad 212 of the circuit layer 211 by electroplating and extends to the hole wall of the opening 220 .

In addition, in the subsequent application of the semiconductor package substrate 2, as shown in the electronic package 4 shown in FIG. 2C, at least one electronic component 40 can be disposed on the exposed pad 212 of the first side 20a of the circuit structure 2a to form a package The layer 41 is on the first side 20a of the circuit structure 2a for bonding the electronic component 40, and on the solder pads 23 on the second side 20b of the circuit structure 2a conductive elements 42 such as solder balls are attached for bonding to a circuit board (figure omitted).

The electronic element 40 is an active element, a passive element, or a combination of both, wherein the active element is, for example, a semiconductor chip, and the passive element is, for example, a resistor, a capacitor, and an inductor. For example, the electronic component 40 is a semiconductor chip, which is electrically connected to the plurality of bonding pads 212 in a flip-chip manner through a plurality of conductive bumps 400 containing solder. Alternatively, the electronic component 40 can also be electrically connected to the bonding pad 212 by a plurality of bonding wires (not shown) in a wire bonding manner. However, the manner in which the electronic component is electrically connected to the semiconductor package substrate 2 is not limited to the above, and the electronic component may also be disposed on the second side 20b of the circuit structure 2a or embedded in the build-up portion 21 .

The encapsulation layer 41 may be a primer, which is formed between the first side 20 a of the circuit structure 2 a and the electronic device 40 to encapsulate the plurality of conductive bumps 400 . Alternatively, the encapsulation layer 41 may be a film for lamination process, an encapsulant for a molding process, or an adhesive for a printing process, etc. to encapsulate the electronic element 40 and the plurality of conductive bumps 400 and form the encapsulation layer 41 The material is polyimide (PI), epoxy resin (epoxy) or molded packaging material. It should be understood that the packaging method of the electronic component 40 is not limited to the above.

The conductive elements 42 are formed on the plurality of solder pads 23 .

In this embodiment, the conductive element 42 includes solder material, such as solder balls.

Therefore, in the manufacturing method of the semiconductor package substrate 2 of the present embodiment, a layer of material is plated on the pads 212 on the ball-mounting side (the second side 20b of the circuit structure 2a ) and the hole walls of the openings 220 of the solder mask structure 22b The same copper material as the circuit layer 211 and the solder pads 212 (ie the solder pads 23 ) is used, so that the conductive element 42 (solder balls) will contact the bottom surface and sidewalls of the solder pads 23 in the subsequent packaging and ball-mounting operations. The metal contact area between the conductive element 42 and the soldering seat 23 is increased, thereby enhancing the bonding force between the conductive element 42 (solder ball) and the soldering seat 23. Therefore, compared with the prior art, the conductive element 42 of the present invention does not It will be broken at the joint with the solder seat 23, which can avoid the occurrence of ball dropping or falling off.

3A to 3C are schematic cross-sectional views of a method for manufacturing a semiconductor package substrate 3 according to a second embodiment of the present invention. The difference between this embodiment and the first embodiment lies in the solder mask structure, and other structures are substantially the same, so only the differences will be described below.

As shown in FIG. 3A , a metal support layer 33 is bonded on the second side 20b of the circuit structure 2a through a bonding material 34, and a plurality of first openings 330 are formed on the metal support layer 33, and a plurality of The first openings 330 extend through the bonding material 34 so that the bonding pads 212 are exposed to the first openings 330 . Next, an insulating layer 32 is formed on the bonding pad 212 , the metal support layer 33 and the first opening 330 .

In this embodiment, the metal supporting layer 33 is a steel plate, a nickel alloy (alloy 42) sheet, etc., and the bonding material 34 is an adhesive material, and the material forming the insulating layer 32 can be graphene, ink, green Paint, ABF or non-photosensitive dielectric material (such as EMC) or other suitable materials are not particularly limited.

In addition, the insulating layer 32 is arranged along the sidewall of the first opening 330 . Alternatively, the insulating layer 32 may fill the first opening 330, as shown in FIG. 3A'.

In addition, the insulating layer 32 is also formed on the first side 20a of the circuit structure 2a.

As shown in FIG. 3B, a plurality of second openings 320 are formed on the insulating layer 32 on the second side 20b of the circuit structure 2a, so that the bonding pads 212 are exposed to the second openings 320, so that the The insulating layer 32 and the metal support layer 33 serve as the solder resist structure 32 a, and the insulating layer 32 covers the metal support layer 33 .

As shown in FIG. 3C , the soldering pads 36 are formed on the soldering pads 212 on the second side 20b of the circuit structure 2a and the hole walls of the second openings 320 of the soldering resist structure 32b, so as to facilitate the connection between the soldering pads 212 and the conductive elements. 42 combined contact area, thereby effectively improving the binding force of the two.

In other embodiments, a conducting block 37 can also be formed on the cup-shaped solder seat 36 as required, and the material for forming the conducting block 37 is, for example, tin or other metal materials. Specifically, as shown in FIG. 3C ′, a solder ball with a volume smaller than the second opening 320 is attached to the cup-shaped soldering seat 36 to form a conductive block 37 , which can effectively reduce the subsequent connection The size of the conductive element 42 (please refer to the subsequent illustration in FIG. 3D ) is to meet the requirements of fine-pitch packaging.

In other embodiments, a bump bottom 361 ′ with an appropriate thickness (for example, 1/2 of the depth of the second opening 320 ) can be formed by electroplating on the pads 212 in the second opening 320 as required. (Please refer to Fig. 3C" for details), and then continue to extend electroplating to the remaining hole walls of the second opening 320, thereby forming a cup-shaped solder pad 36' with a bump bottom 361' (the material of which is the same as that of the circuit layer 211). , the same as the solder pad 212, such as copper), according to which the size of the conductive element 42 to be connected subsequently (please refer to FIG. 3D') can be effectively reduced to meet the requirements of fine-pitch packaging and further optimize the electrical properties Quality (part of the conductive elements 42 made of tin material are replaced by bump bottoms 361 ′ made of copper material with good electrical quality).

In addition, in subsequent applications, if the semiconductor package substrate 3 shown in FIG. 3C and FIG. 3C' is used, the electronic package 4' shown in FIG. 3D will be formed. Specifically, the electronic component 40 is disposed on the exposed pad 212 of the first side 20a of the circuit structure 2a, and the encapsulation layer 41 is formed on the first side 20a to bond the electronic component 40, and the electronic component 40 is formed on the semiconductor package. A plurality of conductive elements 42 are mounted on the solder pads 36 with the conductive blocks 37 on the second side 20b of the substrate 3 .

On the other hand, if the semiconductor package substrate 3 shown in FIG. 3C ″ is used, the electronic package 4 ″ shown in FIG. 3D ′ will be formed, wherein the solder pads 36 ′ with the bump bottoms 361 ′ are connected A plurality of conductive elements 42 are arranged.

Therefore, in the manufacturing method of the semiconductor package substrate 3 of the present embodiment, the bonding pad 212 on the ball-mounting side (the second side 20b of the circuit structure 2a) and the hole wall of the second opening 320 of the solder mask structure 32b are plated Coating a layer of copper material (that is, forming the cup-shaped solder seat 36, the solder seat 36'), so that the conductive element 42 (solder ball) contacts the solder seat 36, the solder seat 36' in the subsequent packaging and ball-mounting operations. The bottom surface and the side wall thus increase the metal contact area, thereby enhancing the bonding force between the conductive element 42 (solder ball) and the solder seat 36 and the solder seat 36 ′. Therefore, compared with the prior art, the bonding force between the conductive element 42 and the soldering seat 36 and the soldering seat 36' of the present invention is stronger, so that the conductive element 42 will not be in the bonding with the soldering seat 36 and the soldering seat 36'. It can also prevent the ball from falling off or falling off.

In addition, by disposing the metal support layer 33 on the second side 20b of the circuit structure 2a to increase the rigidity of the semiconductor packaging substrate 3, compared with the prior art, when the semiconductor packaging substrate 3 is used for large In the package size, even if the semiconductor package substrate 3 is thinned, the semiconductor package substrate 3 still has high rigidity, so the electronic package 4 ′, the electronic package 4 can be avoided in the subsequent high temperature process of packaging or when the product is used. ” warping occurs, thereby avoiding the problem of poor connection between it and the electronic component 40 or the circuit board.

In addition, when the semiconductor package substrate 3 is used for a large package size, the number of layers of the build-up portion 21 of the circuit structure 2a can be designed according to requirements, so the circuit structure 2a may have various degrees of warpage change, so it can be The rigidity of the semiconductor package substrate 3 can be controlled by adjusting the thickness of the metal support layer 33 or the constituent material of the metal support layer 33 . Therefore, there is no need to increase the thickness of the core layer 20 , or even reduce the thickness of the core layer 20 or configure the core layer 20 , which can avoid the warping problem of the semiconductor package substrate 3 .

In addition, by virtue of the design of the cup-shaped solder pad 36 ′ having the bump bottom 361 ′ (the material of which is the same as that of the circuit layer 211 and the solder pad 212 , such as copper), the size and material of the conductive element 42 can be effectively reduced. In order to meet the requirements of fine-pitch packaging, and further optimize the electrical quality of the semiconductor package substrate 3 (replacing part of the tin material conductive elements 42 by the copper material bump bottoms 361 ′ with good electrical quality).

To sum up, the semiconductor package substrate of the present invention and the electronic package packaged therewith utilize the design of the solder pads 23 , the solder pads 36 , and the solder pads 36 ′ to increase the contact area between the conductive element 42 and the metal. Furthermore, the bonding force between the conductive element 42 (solder ball) and the soldering seat 23, the soldering seat 36, and the soldering seat 36' is improved, so the present invention can effectively prevent the conductive element 42 from being in contact with the soldering seat 23, the soldering seat 36, and the soldering seat 36'. The bonding of the solder pads 36' is fractured, and it is also possible to avoid the occurrence of dropped balls or falling off.

The above embodiments are only used to illustrate the principles and technical effects of the present invention, but not to limit the present invention. Those skilled in the art can make modifications to the above embodiments without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be as listed in the claims.

Claims (18)

1. A semiconductor package substrate, comprising:

a line structure having a line layer;

the welding-proof structure is arranged on the circuit structure and is provided with an opening so that the circuit layer is partially exposed out of the opening; and

and the welding seat is of a cup-shaped structure, is formed by electroplating and extends to the hole wall of the opening from the exposed surface of the circuit layer, wherein the material for forming the welding seat is the same as the material for forming the circuit layer.

2. The semiconductor package substrate of claim 1, wherein the solder mask structure is a single insulating layer.

3. The semiconductor package substrate of claim 1, wherein the solder mask structure further comprises a metal support layer and an insulating layer covering the metal support layer, the metal support layer being bonded to the circuit structure with a bonding material.

4. The semiconductor package substrate of claim 1, further comprising a conductive element disposed on the solder pad, wherein the conductive element is a solder ball.

5. The semiconductor package substrate of claim 1, further comprising a solder bump disposed on the solder socket, wherein the solder bump is a solder ball having a volume smaller than the opening.

6. The substrate of claim 1, wherein the contact portion of the pad and the circuit layer is formed with a bottom bump having a suitable thickness, and the suitable thickness is not greater than or greater than the depth 1/2 of the opening.

7. An electronic package, comprising:

the semiconductor package substrate according to one of claims 1 to 6, wherein the circuit structure has a first side and a second side opposite to each other, and the circuit layer is disposed on the first side and the second side, such that the solder mask structure is disposed on the second side of the circuit structure; and

and the electronic element is arranged on the first side of the circuit structure and is electrically connected with the circuit layer on the first side of the circuit structure.

8. The electronic package according to claim 7, further comprising a packaging layer disposed on the semiconductor package substrate for bonding the electronic component and the semiconductor package substrate.

9. The electronic package of claim 7, wherein the electronic component is disposed on the first side of the circuit structure with a plurality of conductive bumps.

10. A method for manufacturing a semiconductor package substrate, the method comprising:

providing a circuit structure with a circuit layer;

forming a solder mask structure on the circuit structure, wherein the solder mask structure has an opening to expose the circuit layer out of the opening; and

and forming a welding seat in the opening, wherein the welding seat is of a cup-shaped structure, is formed by electroplating and extends to the hole wall of the opening from the exposed surface of the circuit layer, and the material for forming the welding seat is the same as the material for forming the circuit layer.

11. The method of claim 10, wherein the solder mask structure is a single insulating layer.

12. The method of claim 10, wherein the solder mask structure further comprises a metal supporting layer and an insulating layer covering the metal supporting layer, and the metal supporting layer is bonded to the circuit structure by a bonding material.

13. The method of claim 10, further comprising forming conductive elements on the solder pad, wherein the conductive elements are solder balls.

14. The method of claim 10, further comprising forming a solder bump on the pad, wherein the solder bump is a solder ball having a volume smaller than the opening.

15. The method of claim 10, wherein the contact portion of the solder pad and the circuit layer is electroplated with a bump bottom having a suitable thickness, and the suitable thickness is not greater than or greater than the 1/2 depth of the opening.

16. A method of fabricating an electronic package, the method comprising:

providing a semiconductor package substrate according to one of claims 1 to 6, wherein the circuit structure has a first side and a second side opposite to each other, and the circuit layer is disposed on the first side and the second side, and the solder mask structure is disposed on the second side of the circuit structure; and

an electronic element is arranged on the first side of the circuit structure and electrically connected with the circuit layer on the first side of the circuit structure.

17. The method of claim 16, further comprising forming an encapsulation layer on the semiconductor package substrate to bond the electronic component and the semiconductor package substrate.

18. The method of claim 16, wherein the electronic component is disposed on the first side of the circuit structure with a plurality of conductive bumps.

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