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CN110459521B - Flip chip package substrate and electronic package - Google Patents

Flip chip package substrate and electronic package Download PDF

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Publication number
CN110459521B
CN110459521B CN201810825294.XA CN201810825294A CN110459521B CN 110459521 B CN110459521 B CN 110459521B CN 201810825294 A CN201810825294 A CN 201810825294A CN 110459521 B CN110459521 B CN 110459521B
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China
Prior art keywords
layer
flip chip
conductive
chip package
substrate
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Application number
CN201810825294.XA
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Chinese (zh)
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CN110459521A (en
Inventor
胡竹青
许诗滨
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Phoenix Pioneer Technology Co Ltd
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Phoenix Pioneer Technology Co Ltd
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Publication of CN110459521A publication Critical patent/CN110459521A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

The invention discloses a flip chip package substrate and an electronic package, wherein the flip chip package substrate is provided with a strengthening structure on one side of a circuit structure thereof so as to increase the rigidity strength of the flip chip package substrate, so that when the flip chip package substrate is used for large-size package, the flip chip package substrate can have good rigidity, and the electronic package can be prevented from being warped.

Description

Flip chip package substrate and electronic package
Technical Field
The present invention relates to a flip chip package technology, and more particularly, to a flip chip package substrate with a reinforced structure. The invention also relates to an electronic package.
Background
With the development of industrial applications, in recent years, development is gradually carried out toward the trend of package specifications of large-sized chips such as Artificial Intelligence (AI) chips, advanced chips or stacked chips, such as 3D or 2.5D IC processes, so as to be applied to high-density circuits/high-stacking-number/large-sized designed advanced products such as Artificial Intelligence (AI) chips, GPUs, and the like.
Therefore, the industry has been changing to flip chip packaging substrates with large layout sizes, such as 40 x 40mm2、70*70mm2Or other thick and large structures to carry large-sized chips such as Artificial Intelligence (AI) chips, advanced chips, or stacked chips.
As shown in fig. 1A, the electronic device 1 includes a circuit board 18, a flip chip package substrate 1A disposed on the circuit board 18, and a semiconductor chip 19 bonded to the flip chip package substrate 1A. Specifically, as shown in fig. 1B, the flip chip package substrate 1a includes a core layer 10, a circuit structure 11 disposed on two sides of the core layer 10, and a solder mask 12 disposed on the circuit structure 11, wherein the core layer 10 has a conductive via 100 for electrically connecting the circuit layers 110 of the circuit structure 11, and the circuit structure 11 further includes at least one dielectric layer 111 covering the circuit layers 110, and the solder mask 12 is exposed out of the outermost circuit layer 110 of the circuit structure 11 for serving as a contact (I/O) 112 to bond the circuit board 18 and the semiconductor chip 19 through solder materials 13,13 ″.
In the conventional core layer 10, a base material made of glass fiber and epoxy resin, such as bt (bimoleimide triazine), FR4 or FR5, is used, and a via hole process, such as a mechanical drilling step, a laser drilling step or a biconical blind hole forming step, is performed thereon, and then a conductive material and a filling resin (plug) are formed by electroplating in the via hole.
However, as shown in fig. 1A, when the flip chip package substrate 1A is applied to a large size in a packaging process of the conventional electronic device 1, the rigidity of the flip chip package substrate 1A is insufficient, so that warpage (warp) may occur due to the CTE mismatch between the layers of the flip chip package substrate 1A during a high temperature packaging process, which may cause poor connection between the flip chip package substrate 1A and the semiconductor chip 19 (e.g. no soldering material 13' is bonded), or poor connection between the flip chip package substrate 1A and the circuit board 18 during soldering (e.g. no soldering material 13 ″), which may cause electrical failure or cracking of the semiconductor chip 19 itself due to stress.
In addition, if the thickness h (as shown in fig. 1B) of the core layer 10 is increased, for example, from 0.6 mm to more than 1.0 mm, the rigidity of the flip chip package substrate 1a is increased to reduce the warpage of the flip chip package substrate 1a, but when the thickness h of the core layer 10 is increased, more defects are generated, as follows:
first, the core layer 10 is thickened, which is not suitable for the requirement of a thin or miniaturized package design. Specifically, in order to prevent the flip chip package substrate 1a from warping and further increase the thickness of the core layer 10, the entire flip chip package substrate 1a becomes thicker, which is not favorable for the manufacturing of the substrate and increases the processing cost.
Second, as a result of thickening the core layer 10, it is more difficult to make a fine pitch between the conductive vias 100. Specifically, when the thickness h of the core layer 10 is increased, the diameter of the conductive via 100 is increased in the conventional art, so that the end surface (aperture w) of the conductive via 100 cannot be further reduced, and the pitch of the conductive via 100 cannot be effectively reduced.
Thirdly, as a result of thickening the core layer 10, it becomes more difficult to make a fine pitch. Specifically, when the thickness h of the core layer 10 is increased, the hole shape of the conductive via 100 and the depth ratio thereof are increased, that is, the conductive via 100 needs to have a sufficiently large aperture w to match the increase of the depth (the thickness h) (if the thickness h of the core layer 10 is originally 0.8 mm and matches the aperture of 0.1 mm, if the thickness h is 1.2 mm, the aperture w needs to match the aperture of 0.2 mm or more), so under the conventional technology, the diameter of the conductive via 100 is increased (otherwise, mechanical drilling or laser drilling cannot be performed), which leads to a reduction in the circuit wiring area of the circuit layer 110 above the conductive via, and further makes it difficult to fabricate the circuit layer 110 with fine circuit and fine pitch.
Fourth, as the depth (the thickness h) of the conductive via 100 increases, it becomes more difficult to fill the conductive via 100 or to plate the conductive layer 100a in the via. Specifically, the conductive via 100 has a thick core layer 10, which makes it difficult to uniformly fill via hole filling material or electroplate conductive material.
Fifth, the resistance of the conductive material becomes high and the electrical properties become poor. Specifically, the thickness h of the core layer 10 is increased, so that the thickness of the entire flip chip package substrate 1a is increased, and the resistance value is increased due to the longer conductive path, resulting in the deterioration of the electrical characteristics.
Sixth, heat dissipation is deteriorated. Specifically, the thickness of the core layer 10 is increased to increase the thickness of the entire flip chip package substrate 1a, which increases the difficulty of heat dissipation of the flip chip package substrate 1a, thereby deteriorating the heat dissipation and affecting the overall performance and lifetime.
The dielectric layer 111 of the conventional circuit structure 11 is made of a thin Film dielectric material, such as ABF (Ajinomoto Build-up Film). If the glass fiber Prepreg (PP) is used to resist and improve the warpage problem, other disadvantages may occur, for example, laser blind via processing is performed on the glass fiber Prepreg, and since PP is used for the dielectric layer 111, the processing cost is increased and it is difficult to fabricate fine blind vias.
In addition, as shown in fig. 1C, the flip chip package substrate 1a 'may also be in a coreless (core) form, and although the electrical quality is better than that of the flip chip package substrate 1a with the core layer 10, and the width and the distance of the circuit are not limited by the conductive vias 100 of the core layer 10, the structural rigidity of the flip chip package substrate 1 a' without the core layer is worse, so that warpage is more likely to occur during the high temperature packaging process.
Therefore, how to overcome the various problems in the prior art has become an issue to be solved.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, the present invention provides a flip chip package substrate, which can prevent an electronic package from warping.
The flip chip package substrate comprises a circuit structure and a reinforcing structure, wherein the circuit structure is provided with a first side and a second side which are opposite; the reinforcing structure is arranged on the first side and/or the second side of the circuit structure.
In the foregoing flip chip package substrate, the circuit structure includes at least one dielectric layer and a circuit layer disposed on the dielectric layer. For example, the circuit structure includes a core layer, such that the dielectric layer and the circuit layer are disposed on the core layer.
In the above-mentioned flip chip package substrate, a plurality of conductive parts electrically connected to the circuit layer are formed in the core layer. For example, the conductive portion may include a conductive via, a single pillar, or a plurality of pillars stacked in contact with each other.
In the foregoing flip chip package substrate, the reinforcing structure includes a rigid layer, which is a conductive material or an insulating material. For example, the reinforcing structure includes an insulating portion that covers the rigid layer, so that the rigid layer is bonded to the circuit structure through the insulating portion. Further, the insulating part comprises a bonding layer for bonding the circuit structure and a protective layer for wrapping the rigid layer.
In the foregoing flip chip package substrate, the reinforcing structure includes an insulating portion bonded to the circuit structure.
The flip chip package substrate further includes a conductive element disposed on the circuit structure for electrically connecting to the circuit structure, and the conductive element is disposed in the reinforcing structure and exposed from the reinforcing structure.
In the above-mentioned flip chip package substrate, the circuit structure is in the form of coreless layer.
The invention also provides an electronic package, which comprises the flip chip package substrate and an electronic element, wherein the electronic element is arranged on the first side and/or the second side of the circuit structure.
The electronic package further includes a package layer disposed on the flip chip package substrate to encapsulate and bond the electronic component.
As can be seen from the above, the flip chip package substrate and the electronic package of the present invention have the advantages and effective effects that the enhanced structure is disposed on one side of the circuit structure to increase the rigidity of the flip chip package substrate, so compared with the prior art, the electronic package of the present invention does not warp during the high temperature packaging process, and has the effects of facilitating the thinning design of the flip chip package substrate, making the conductive through holes fine-spaced, increasing the circuit density, easily plugging or plating the conductive through holes without thickening the core layer, improving the heat dissipation performance of the thin core layer, reducing the conductive resistance value to improve the electrical performance, reducing the processing cost of the core layer of the conductive through holes, and improving the heat dissipation function of the enhanced structure.
In addition, the flip chip packaging substrate is applied to the electronic packaging piece with large packaging size, and cannot generate warping due to the packaging process; or, the problems of warping, performance degradation or chip failure caused by thermal effect can be reduced during functional operation. Therefore, the flip chip package substrate is more beneficial to the thinning design.
Drawings
FIG. 1A is a schematic cross-sectional view of a conventional electronic device;
FIG. 1B is a schematic cross-sectional view of a conventional flip-chip package substrate;
FIG. 1C is a schematic cross-sectional view of another conventional flip-chip package substrate;
FIG. 2A is a schematic cross-sectional view of a flip chip package substrate according to the present invention;
FIG. 2B is another embodiment of FIG. 2A;
FIG. 2C is another embodiment of FIG. 2A;
FIG. 3A is a schematic cross-sectional view of an electronic package of the present invention;
FIG. 3B is another embodiment of FIG. 3A;
FIG. 3C is another embodiment of FIG. 3A;
fig. 4A and 4B are schematic cross-sectional views illustrating another embodiment of a reinforced structure of a flip chip package substrate according to the present invention;
fig. 5A to 5C are schematic cross-sectional views illustrating different embodiments of the reinforced structure of the flip chip package substrate according to the present invention; and
fig. 6A to 6C are schematic cross-sectional views illustrating other embodiments of the reinforced structure of the flip chip package substrate of the invention.
Description of the reference numerals
1 electronic device 1a,1 a' flip chip package substrate
10,20, 20' core layer 100 conductive vias
11,2a,2 a' line structure 110,211 line layer
111,210 dielectric layer 112 contact
12 solder mask layers 13, 13', 230,461 solder material
18 circuit board 19 semiconductor chip
2, 2' flip chip package substrate 2b,5b,6b reinforced structure
20a first side 20b second side
200, 200' conductive part 200a conductive material
200b column of filler 200c
21 build-up section 212 pad
213 Electrical contact pad 22 insulation passivation layer
23, 23' conductive bump 231 metal post
24,64 rigid layer 25 insulation
250 bonding layer 251,551 protective layer
26,46a,46b conductive element 3, 3' electronic package
30 electronic component 31, 31' encapsulation layer
32 solder ball 460 copper block
H, H, t thickness S end surface junction
And w pore diameter.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification.
It should be understood that the structures, ratios, sizes, and the like shown in the drawings and described in the specification are only used for matching with the disclosure of the specification to provide understanding and reading for those skilled in the art, and are not used to limit the limit conditions of the present invention, so they have no technical significance, and any structural modification, ratio relationship change or size adjustment should still fall within the scope of the present invention without affecting the function and the achievable purpose of the present invention. In addition, the terms "above" and "a" and the like in the present specification are used for clarity of description only, and are not used to limit the scope of the present invention, and changes or adjustments of the relative relationship thereof are also regarded as the scope of the present invention without substantial changes in the technical content.
Fig. 2A is a schematic cross-sectional view of the flip chip package substrate 2 of the present invention. As shown in fig. 2A, the flip chip package substrate 2 includes a circuit structure 2A and a reinforcing structure 2 b.
The circuit structure 2a has a first side 20a and a second side 20b opposite to each other, both sides can be used for placing electronic components (such as semiconductor chips, passive components, etc.), and the external side where the semiconductor chips are placed is referred to as a die side, so for convenience of the following description, the first side 20a is referred to as the die side.
In the present embodiment, the circuit structure 2a has a core layer 20 in which a plurality of conductive portions 200 are formed. For example, the core layer 20 may be formed by using a substrate containing glass fibers and organic resin, such as bt (bimoleimide triazine), FR4 or FR5, or by using an organic substrate without glass fibers and containing a filler (e.g. SiO2), and then performing a via process, such as mechanical drilling or laser drilling, to form a conductive material 200a in the via and a filler 200b in the via.
In another embodiment, as shown in fig. 2B, the core layer 20' is formed of an organic insulating material, which may be ABF (Ajinomoto fabric-up Film), a Prepreg (Prepreg) with or without glass fiber, a Molding Compound (Molding Compound), such as a core substrate formed of Epoxy Molding Compound (EMC), preferably, EMC with high rigidity and low thermal expansion Coefficient (CTE). In addition, the conductive portion 200' may be composed of a single conductive cylinder or a plurality of conductive cylinders 200c stacked in contact with each other, and the widths of at least two of the cylinders 200c may be different, so that the boundary S of the end surfaces of the cylinders 200c is stepped. It should be understood that the number of stacked layers or the peripheral shape of the pillars 200c of the conductive part 200' can be designed as required.
Therefore, the conductive portions 200,200 'can be formed integrally or laminated, and the outline of the conductive portions 200, 200' is not particularly limited.
The circuit structure 2a further includes a build-up portion 21 disposed on the core layer 20, 20', and having at least one dielectric layer 210 and a plurality of circuit layers 211 combined with the dielectric layer 210, and an insulating protection layer 22 may be formed on the build-up portion 21 corresponding to the first side 20a without a protection layer or as required, so that the insulating protection layer 22 is exposed out of the circuit layer 211 at the outermost layer of the first side 20a for serving as a pad 212 combined with the conductive bump 23. For example, the dielectric layer 210 may be formed of liquid epoxy, film-like ABF, prepreg, molding resin (EMC) or photosensitive resin, the insulating protective layer 22 may be solder resist such as photosensitive ink, ABF or non-photosensitive dielectric (e.g., EMC), and the conductive bump 23 includes solder material 230 (shown in FIGS. 2A and 2B) and/or metal pillar 231 (shown in FIG. 2B as conductive bump 23'). It should be understood that the number of layers of the circuit layer 211 can be designed according to the requirement.
The reinforcing structure 2b is arranged on the second side 20b of the line structure 2 a.
In the present embodiment, the reinforcing structure 2b includes a rigid layer 24, and the rigid layer 24 is formed of a high-rigidity material. For example, the rigid layer 24 may be made of aluminum, aluminum alloy, stainless steel, copper alloy, nickel-iron alloy, or other metal materials. Alternatively, as shown in fig. 6A to 6C of the reinforcing structure 6b, the rigid layer 64 may be made of a high-rigidity ceramic material (such as Al2O3 or AlN), plastic, carbon fiber or other insulating materials. Accordingly, the material of the rigid layers 24,64 can be designed according to the requirements, and is not limited to the above.
In addition, the reinforcing structure 2b includes an insulating portion 25 covering the rigid layer 24, so that the rigid layer 24 is bonded to the second side 20b through the insulating portion 25. For example, the insulating portion 25 includes a bonding layer 250 for bonding the second side 20b and a protection layer 251 for covering the rigid layer 24, wherein the material of the insulating portion 25 (or the protection layer 251) may be an organic dielectric material (e.g., solder resist) or an inorganic dielectric material (e.g., insulating oxide). Specifically, the kind of the organic dielectric material further includes ABF, prepreg, mold compound, epoxy molding resin (EMC), or primer. The insulation portion 25 is used to isolate the electrical conduction between the metal rigid layer 24 and the conductive element 26, so as to prevent short circuit.
For example, the material of the bonding layer 250 and the material of the passivation layer 251 may be the same, such as the reinforced structure 2B shown in fig. 2A, 2B, 4A and 4B; alternatively, as shown in the reinforced structure 5b of fig. 5A to 5C, the material of the bonding layer 250 and the material of the passivation layer 551 may be different.
The flip-chip package substrate 2 further includes a plurality of conductive elements 26 embedded in the stiffener structure 2b and exposed from the stiffener structure 2b, which are combined with and electrically connected to the electrical contact pads 213 of the circuit layer 211 at the outermost layer of the second side 20 b. For example, the conductive element 26 is a pillar made of copper (Cu), nickel (Ni) or copper/nickel/gold (Cu/Ni/Au). Alternatively, as shown in FIG. 4A, the conductive element 46a comprises a metal mass, such as copper mass 460 and solder material 461 encapsulating the copper mass 460. Alternatively, as shown in FIG. 4B, the conductive element 46B has a pillar structure made of a conductive metal paste, such as copper paste, silver paste, tin paste or solder ball.
In addition, the processes related to the reinforcing structures 2b,5b,6b are various. For example, the rigid layers 24,64 may be attached to the second side 20b by the insulating portion 25 (or the bonding layer 250), an opening may be formed in the insulating portion 25 to expose the electrical contact pad 213, and then the conductive element 26,46a,46b may be formed (plated, embedded or filled) in the opening to electrically connect the electrical contact pad 213. Alternatively, the conductive elements 26,46a,46b may be formed (plated or embedded) on the electrical contact pads 213, the insulating portion 25 (or the bonding layer 250) is used to attach the rigid layers 24,64 to the second side 20b, so that the conductive elements 26,46a,46b are embedded in the reinforcing structures 2b,5b,6b (or the insulating portion 25), and then openings are formed by photolithography, etching or Laser (Laser) to expose the conductive elements 26,46a,46 b. It should be understood that the end surfaces of the conductive elements 26,46a,46b may be higher than, lower than or even with the surface of the reinforcing structure 2b,5b,6b, so that the end surfaces of the conductive elements 26,46a,46b are exposed to the surface of the reinforcing structure 2 b.
On the other hand, as shown in fig. 2C, the circuit structure 2a ' of the flip chip package substrate 2 ″ may also be in a coreless (core) form, and the stiffener structure 2b is disposed on the second side 20b of the circuit structure 2a ', wherein the circuit structure 2a ' includes the build-up portion 21 and the insulating protection layer 22, the interlayer electrical connection manner of the circuit layer 211 of the build-up portion 21 adopts a conductive pillar manner (also may adopt a conductive blind via manner), and the bonding pad 212 for combining the conductive bump 23 is embedded in the dielectric layer 210 and flush with the surface of the dielectric layer 210 (also may be slightly concave or slightly convex on the surface of the dielectric layer 210), so that the bonding pad 212 is exposed out of the dielectric layer 210, and the insulating protection layer 22 is exposed out of the outermost circuit layer 211, so that the exposed circuit layer 211 serves as an electrical contact pad 213 for combining the conductive element 26. It should be understood that the insulating protection layer 22 may be disposed on the first side 20a or not disposed on the second side 20b, and the configuration of the insulating protection layer 22 is not particularly limited.
Fig. 3A and 3B are schematic cross-sectional views of electronic packages 3, 3' according to the present invention.
As shown in fig. 3A or fig. 3B, at least one electronic component 30 is disposed on the first side 20a of the flip chip package substrate 2,2 'shown in fig. 2A or fig. 2B, and a package layer 31, 31' is formed on the first side 20a to combine the electronic component 30; alternatively, solder balls 32 may be mounted on the conductive elements 26 in the reinforcing structure 2b of the flip chip package substrate 2, 2' for bonding to a circuit board (not shown).
In the present embodiment, the electronic component 30 is an active component, such as a semiconductor chip, a passive component, such as a resistor, a capacitor, and an inductor, or a combination thereof. For example, the electronic component 30 is a semiconductor chip electrically connected to the circuit layer 211 of the circuit structure 2a in a flip-chip manner through the conductive bumps 23, 23'. Alternatively, the electronic device can be electrically connected to the circuit structure by wire bonding through a plurality of bonding wires (not shown). However, the way of electrically connecting the electronic component to the circuit structure 2a is not limited to the above, and the electronic component may be disposed on the second side 20b or embedded in the enhanced portion 21.
In addition, the encapsulation layer 31 can be an underfill, which is formed between the first side 20a and the electronic component 30 to encapsulate the conductive bumps 23. Alternatively, the package layer 31 ' may be a film for a lamination process, a molding compound for a molding process, or a printing compound for a printing process, etc. to cover the electronic component 30 and the conductive bumps 23 ', and the material forming the package layer 31 ' is Polyimide (PI), epoxy (epoxy) or a molding compound. It should be understood that the package layers 31 and 31' of fig. 3A and 3B can be used together, and the package method of the electronic component 30 is not limited to the above.
On the other hand, as the electronic package 3 ″ shown in fig. 3C, the electronic element 30 and the related processes thereof may also be disposed on the first side 20a of the circuit structure 2a ″ of the flip-chip package substrate 2 ″ shown in fig. 2C, which will not be described herein again.
In summary, the flip chip package substrate 2,2 ', 2 ″ and the electronic package 3,3 ', 3 ″ packaged thereby according to the present invention increase the rigidity of the flip chip package substrate 2,2 ', 2 ″ by disposing the reinforcing structure 2b,5b,6b on the second side 20b of the circuit structure 2a,2a ', so that compared with the prior art, when the flip chip package substrate 2,2 ', 2 ″ is used in a large package size, the flip chip package substrate 2,2 ', 2 ″ still has high rigidity even if the flip chip package substrate 2,2 ', 2 ″ is thinned, thereby preventing the electronic package 3,3 ', 3 ″ from warping during a subsequent packaging high temperature process or during product use, and further preventing the problem of poor connection between the electronic package 3,3 ', 3 ″ and the electronic component 30 or the circuit board.
In addition, the flip chip package substrate 2, 2', 2 ″ is used for large package size (e.g., 55 × 55, 70 × 70, 80 × 80 mm)2Etc.), the number of layers of the build-up portion 21 of the wiring structure 2a,2a 'may be designed as desired, so that the wiring structure 2a,2 a' may be warped to various degrees, and thus the thickness t of the reinforcing structure 2b,5b,6b or the material and construction material of the reinforcing structure 2b may be used. Therefore, by adjusting the thickness t and the material of the reinforced structure 2b,5b,6b, the rigidity of the flip chip package substrate 2,2 ', 2 ″ can be controlled, so that the thickness of the core layer 20 does not need to be increased, and even the thickness of the core layer 20 can be reduced or the core layer 20 does not need to be configured, thereby avoiding the warpage problem of the flip chip package substrate 2, 2', 2 ″. Therefore, the end faces of the conductive parts 200,200 'can be designed to be miniaturized or the conductive parts 200, 200' do not need to be configured according to requirements, so that the circuit wiring limitation of the circuit layer 211 can be reduced, the circuit layer 211 with fine circuits and fine pitches can be manufactured easily, and the effect of high-density packaging is achieved.
Moreover, since the thickness of the core layer 20 does not need to be increased, even the thickness of the core layer 20 can be reduced, the conductive portion 200' employs a metal conductive column to reduce the conductive resistance value, so as to improve the electrical performance, and further provide good heat dissipation.
In addition, since the core layer 20 is thinned, the processing difficulty of the conductive part 200 is reduced, and thus the overall manufacturing cost of the electronic package 3 and the flip chip package substrate 2 can be greatly reduced.
Thus, the efficacy achieved by the features of the present invention is summarized as follows:
first, the flip chip package substrate 2,2 ', 2 ″ of the present invention has the supporting function of the high rigidity reinforcing structure 2b,5b,6b, so that the flip chip package substrate 2,2 ', 2 ″ and the electronic package 3,3 ', 3 ″ completed by the same can be packaged in large size and designed to be thin.
Second, since the core layer 20 of the present invention can maintain a thin design, the end face of the conductive part 200 of the present invention can be designed to be miniaturized as required, thereby achieving the purpose of making the pitch of the conductive part 200 fine.
Third, since the conductive part 200 of the present invention can be designed with a fine pitch, even without disposing the conductive part 200, the wiring restriction of the wiring layer 211 can be reduced, and the wiring layer 211 with a high density can be easily manufactured.
Fourth, since the core layer 20 of the present invention can maintain a thin design, the depth ratio between the diameter of the conductive part 200 and the thickness of the core layer 20 is not increased, so that it is easy to fill the via hole of the conductive part 200 or plate the conductive pillar of the conductive part 200, thereby effectively and uniformly filling the material.
Fifth, since the core layer 20 of the present invention can maintain a thin design, the height of the conductive part 200 is not increased, thereby reducing the conductive resistance and further improving the electrical performance.
Sixth, since the core layer 20 of the present invention can maintain a thin design, the depth ratio between the hole shape of the conductive part 200 and the thickness of the core layer 20 is not increased, and thus the difficulty and cost of processing the via hole in the core layer 20 can be greatly reduced.
Seventh, the characteristics of the thick rigid layer 24 and the thin core layer 20 (even without the core layer 20) of the reinforcing structures 2b,5b,6b of the present invention can effectively improve the heat dissipation of the electronic package 3, 3', 3 ″, so that the high temperature during the packaging process can be matched without warpage deformation, and the performance stability of the application end during operation and heat generation can be ensured. Furthermore, when the reinforcing structures 2b and 5b are made of metal, the reinforcing structures can provide good electrical grounding function and reduce noise in use.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Those skilled in the art can modify the above-described embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of the invention should be determined from the following claims.

Claims (11)

1. A flip chip package substrate, comprising:
a circuit structure having opposing first and second sides;
the reinforcing structure is arranged on the first side and/or the second side of the circuit structure, the reinforcing structure comprises a rigid layer which is a conductive material or an insulating material, the reinforcing structure further comprises an insulating part which is used for coating the rigid layer so that the rigid layer is combined on the circuit structure through the insulating part, and the insulating part is arranged on the outermost side of the first side and/or the second side of the circuit structure;
the conductive element is in a copper material column structure, is arranged on the circuit structure and is electrically connected with the circuit structure, is positioned in the reinforced structure, and enables the end face of the conductive element not to protrude out of the surface of the reinforced structure so as to be exposed out of the reinforced structure; and
solder balls attached to the conductive elements in the reinforcing structure.
2. The substrate of claim 1, wherein the circuit structure comprises at least one dielectric layer and a circuit layer disposed on the dielectric layer.
3. The substrate of claim 2, wherein the circuit structure further comprises a core layer, such that the dielectric layer and the circuit layer are disposed on the core layer.
4. The substrate for flip chip package according to claim 3, wherein a plurality of conductive portions electrically connected to the circuit layer are formed in the core layer.
5. The substrate for flip chip package according to claim 4, wherein the conductive portion comprises a single pillar or a plurality of pillars stacked in contact with each other.
6. The substrate for flip chip package according to claim 4, wherein the conductive portions are conductive through holes.
7. The substrate for flip chip package according to claim 1, wherein the insulating portion comprises a bonding layer for bonding the circuit structure and a protective layer for covering the rigid layer.
8. The substrate of claim 1, wherein the stiffener structure comprises an insulating portion bonded to the trace structure.
9. The substrate of claim 1, wherein the circuit structure is in the form of a coreless layer.
10. An electronic package, characterized in that the electronic package comprises:
the flip chip package substrate according to one of claims 1 to 9; and
and the electronic element is arranged on the first side and/or the second side of the circuit structure.
11. The electronic package of claim 10, further comprising an encapsulation layer disposed on the circuit structure to encapsulate the electronic component.
CN201810825294.XA 2018-05-07 2018-07-25 Flip chip package substrate and electronic package Active CN110459521B (en)

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