CN106356357A - Package substrate and method for fabricating the same - Google Patents
Package substrate and method for fabricating the same Download PDFInfo
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- CN106356357A CN106356357A CN201510529973.9A CN201510529973A CN106356357A CN 106356357 A CN106356357 A CN 106356357A CN 201510529973 A CN201510529973 A CN 201510529973A CN 106356357 A CN106356357 A CN 106356357A
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Abstract
A packaging substrate and a manufacturing method thereof are provided, the manufacturing method comprises the steps of forming a first circuit layer, a first dielectric layer, an internal circuit layer, a second dielectric layer and a second circuit layer on a bearing piece in sequence, wherein the thermal expansion coefficient of the first dielectric layer is larger than that of the second dielectric layer, and the wiring area of the first circuit layer is larger than that of the second circuit layer, so that in the packaging process, the first dielectric layer is made of a material with a high thermal expansion coefficient, so that the packaging substrate can provide a larger shrinkage force in the cooling stage in the thermal process, and the warping phenomenon caused by the different densities of the first circuit layer and the second circuit layer of the packaging substrate is eliminated.
Description
Technical field
The present invention relates to a kind of base plate for packaging and its preparation method, espespecially a kind of encapsulation reducing warpage
Board structure and its preparation method.
Background technology
Flourishing with electronic industry, electronic product is also gradually marched toward multi-functional, high-performance
Trend.In order to meet running gear for the frivolous and inexpensive market demand, base plate for packaging
Also gradually coreless substrate (coreless substrate) is developed into by the substrate with core,
To reduce the thickness of base plate for packaging, and the compact purpose of encapsulating structure can be reached.
As shown in figure 1, existing packaging part 1 comprises a coreless substrate 11, this coreless substrate
It is provided with line layer in 11, and the both sides one of this coreless substrate 11 are to put brilliant side 11a, Ling Yixiang
Offside is to plant ball side 11b, and puts brilliant side and be provided with a chip 12 in this.
Only, the very thin thickness of existing coreless substrate 11, therefore in encapsulation process, when carrying out heat
During temperature-fall period in processing procedure, because coreless substrate 11 in the circuit putting brilliant side 11a closeer and with
The circuit planting ball side 11b is thinner, causes coreless substrate because of upper and lower side thermal coefficient of expansion not
Join (cte mismatch) and such as the anti-warpage (as indicated by the dashed line in figure 1) smiled occurs, enter
And lead to packaging part 1 flatness not good, so that when rear continued access is placed on circuit board, can send out
The problem of raw Non-Dewetting (non-wetting), and make electric connection not good.
Additionally, the situation of warpage (warpage) to also result in this semiconductor wafer 12 chipping,
Product yield is caused to reduce.
If also, increasing the thickness of packaging part 1, though the situation of warpage can be slowed down, so will not
Meet frivolous, short and small demand.
Therefore, how to overcome the variety of problems of above-mentioned prior art, become current industry urgently in fact
A difficult problem to be overcome.
Content of the invention
In view of the disappearance of above-mentioned prior art, the present invention provides a kind of base plate for packaging and its preparation method,
Base plate for packaging first line layer caused warpage different from the second line layer closeness can be offseted existing
As.
The base plate for packaging of the present invention a, comprising: dielectric structure, including at least there being the first dielectric layer
With the second dielectric layer, and dielectric structure have the first surface of side of corresponding first dielectric layer with
The second surface of the side of the second dielectric layer, wherein, the thermal coefficient of expansion of the first dielectric layer is more than
The thermal coefficient of expansion of the second dielectric layer；First line layer, it is located at the first surface of dielectric structure
On；And second line layer, it is on the second surface of dielectric structure, and first line layer
Layout area be more than the second line layer layout area.
In aforesaid base plate for packaging, this dielectric structure has internal wiring layer.This first dielectric another
It is provided with least one conductive blind hole in layer and the second dielectric layer, so that this internal wiring layer is electrically connected
Connect this first line layer and the second line layer.
In aforesaid base plate for packaging, this first line layer and the second line layer are provided with a welding resisting layer.
The first surface of this dielectric structure another is to put brilliant side, and the second surface of this dielectric structure is to plant ball side,
Wherein, it is provided with the opening exposing outside this first line layer of part positioned at the welding resisting layer putting brilliant side, with
Put for connecing and be electrically connected with a chip, be provided with positioned at the welding resisting layer planting ball side expose outside part this
The perforate of two line layers, plants ball pad for being formed.
The present invention also provides a kind of preparation method of base plate for packaging, comprising: forming one on a bearing part
First line layer；Form one first dielectric layer on this first line layer；Form one second dielectric
Layer is on this first dielectric layer；Form one second line layer on this second dielectric layer, wherein,
The thermal coefficient of expansion of this first dielectric layer is more than the thermal coefficient of expansion of this second dielectric layer, and this
The layout area of one line layer is more than the layout area of this second line layer.
The preparation method of aforesaid base plate for packaging, also includes forming a protective layer on this second line layer；
Remove this bearing part, to expose this first line layer；Remove this protective layer, with expose this second
Line layer；And form a welding resisting layer on this first line layer and the second line layer.
The preparation method of aforesaid base plate for packaging, also includes forming at least one internal wiring layer in first Jie
In electric layer and the second dielectric layer, and form at least one conductive blind hole in the first dielectric layer and second
In dielectric layer, this internal wiring layer is made to be electrically connected with first line layer and the second line layer.
The preparation method of aforesaid base plate for packaging, the welding resisting layer being also included on this first line layer is formed
At least one opening, to be provided as chip connecting area, and the welding resisting layer on this second line layer
Form at least one perforate, to be provided as planting ball pad.
From the foregoing, it will be observed that compared to prior art, the base plate for packaging of the present invention and its preparation method, mainly
Thermal coefficient of expansion by the first dielectric layer is more than the thermal coefficient of expansion of the second dielectric layer, and first
The layout area of line layer is more than the layout area of the second line layer, in follow-up encapsulation process,
When carrying out the temperature-fall period in hot processing procedure, because the first dielectric layer uses high thermal expansion coefficient material,
Larger contractility can be provided, to provide base plate for packaging one reverse contractility, to offset because of
The warping phenomenon of one line layer different from the second line layer closeness caused " anti-smile ".
Brief description
Fig. 1 is the cross-sectional schematic of existing semiconductor package part；
Fig. 2 a to Fig. 2 h is the cross-sectional schematic of the preparation method first embodiment of base plate for packaging of the present invention,
And Fig. 2 a ' is another embodiment of corresponding diagram 2a；And
Fig. 3 a to Fig. 3 c is the cross-sectional schematic of the preparation method second embodiment of base plate for packaging of the present invention.
Symbol description
1 packaging part
11 substrates
11a puts brilliant side
11b plants ball side
12 chips
21st, 31 bearing part
211st, 311 crystal seed layer
22nd, 32 first line layer
23rd, 33 first dielectric layer
230th, 330 dielectric structure
230a, 330a first surface
230b, 330b second surface
231st, 251,331,351 conductive blind hole
24th, 34 internal wiring layer
25th, 35 second dielectric layer
26th, 36 second line layer
27th, 37 protective layer
28th, 38 first welding resisting layer
28 ', 38 ' second welding resisting layers
280th, 380 opening
280 ', 380 ' perforates.
Specific embodiment
By particular specific embodiment, embodiments of the present invention, art technology are described below
Personnel can be understood other advantages and the work(of the present invention easily by content disclosed in the present specification
Effect.
It should be clear that structure depicted in this specification institute accompanying drawings, ratio, size etc., all only use
To coordinate the content disclosed in description, for understanding and the reading of people skilled in the art,
It is not limited to the enforceable qualificationss of the present invention, therefore do not have technical essential meaning,
The adjustment of the modification of any structure, the change of proportionate relationship or size, is not affecting institute of the present invention
Under the effect that can produce and the purpose that can reach, all should still fall in disclosed technology
In the range of content obtains and can cover.Meanwhile, in this specification cited as " on ", "
One ", the term such as " second " and " ", is also only and is easy to understanding of narration, and be not used to
Limit the enforceable scope of the present invention, being altered or modified of its relativeness, change in no essence
Under technology contents, when being also considered as the enforceable category of the present invention.
Refer to Fig. 2 a to Fig. 2 h, be the cuing open of preparation method first embodiment of the base plate for packaging of the present invention
Depending on schematic diagram.
As shown in Figure 2 a, a bearing part 21 is provided, and forms one first on this bearing part 21
Line layer 22.In the present embodiment, this bearing part 21 is, for example, that corrosion resistant plate etc. is conductive or non-leads
The hard plate of electricity, and first line layer 22 is, for example, copper or other conductive materials.
In certain embodiments, as shown in Fig. 2 a ', on this bearing part 21, form this First Line
Before road floor 22, a crystal seed layer 211, such as copper crystal seed layer can be formed prior to this bearing part 21
(copper seed layer), forms this first line layer 22 so that profit is follow-up through modes such as plating.
As shown in Figure 2 b, first Jie is formed on this bearing part 21 and this first line layer 22
Thermal coefficient of expansion (the coefficient of thermal of electric layer 23, wherein this first dielectric layer 23
Expansion, cte) it is more than 10ppm/ DEG C.In the present embodiment, this first dielectric layer 23
Material is, for example, glass fibre (glass fiber).
As shown in Figure 2 c, form internal wiring layer 24 on this first dielectric layer 23, and in this
Form conductive blind hole 231 to be electrically connected with this internal wiring layer 24 and to be somebody's turn to do in first dielectric layer 23
First line layer 22.
As shown in Figure 2 d, second Jie is formed on this first dielectric layer 23 and internal wiring layer 24
Electric layer 25.In the present embodiment, the material of this second dielectric layer 25 is, for example, glass fibre.
As shown in Figure 2 e, form the second line layer 26 on the second dielectric layer 25, and in this
Formed in two dielectric layers 25 conductive blind hole 251 be electrically connected with this internal wiring layer 24 and this
Two line layers 26.
In this, this first dielectric layer 23 and this second dielectric layer 25 constitute a dielectric structure 230,
Wherein, this dielectric structure 230 have to should first line layer 23 side first surface
230a with to should the second line layer 26 side second surface 230b, wherein, this first
The layout area of line layer 22 is more than the layout area of this second line layer 26, and this first Jie
The thermal coefficient of expansion of electric layer 23 is more than the thermal coefficient of expansion of this second dielectric layer 25.In this enforcement
In example, the layout area of this first line layer 22 is this first line layer 22 in this first dielectric
Area about 53% shared by layer 23；The layout area of this second line layer 26 is this second line layer
26 areas about 47% shared by this second dielectric layer 25, but be not limited.Separately, this first
For example, 11ppm/ DEG C of the thermal coefficient of expansion of dielectric layer 23, and the heat of this second dielectric layer 25 is swollen
For example, 3ppm/ DEG C of swollen coefficient, but be not limited.
As shown in figure 2f, protection is formed on this second line layer 26 and this second dielectric layer 25
Layer 27.This protective layer 27 is used to protect this second line layer 26 exposing in successive process.
In the present embodiment, this protective layer 27 is, for example, dry film (dry film), but is not limited.
As shown in Figure 2 g, remove this bearing part 21, to expose outside this first line layer 22, its
In the exposed surface of this first line layer 22 flush with the exposed surface of this first dielectric layer 23.
In addition, as corresponding diagram 2a ' when being previously formed with crystal seed layer 211 on this bearing part 21,
Also remove this crystal seed layer 211 to expose this first line layer while removing this bearing part 21
22.
As shown in fig. 2h, remove this protective layer 27 to expose outside this second line layer 26.
Then on the first surface 230a and second surface 230b of this dielectric structure 230
Form the first welding resisting layer 28 and second covering this first line layer 22 and this second line layer 26
Welding resisting layer 28 ', wherein, this first welding resisting layer 28 is formed with least one opening 280, to expose
Go out part this first line layer 22, wherein this opening 280 as chip connecting area, with for this
Connect in opening 280 and put and be electrically connected with semiconductor wafer (not shown), in addition, this is second anti-welding
Layer 28 ' is also formed with least one perforate 280 ', this second line layer 26 of exposed portion in addition,
To be provided as planting the plant ball pad of soldered ball.
Refer to Fig. 2 h, the present invention also provides a kind of base plate for packaging 2, comprising: a dielectric structure
230, including at least having the first dielectric layer 23 and the second dielectric layer 25, and this dielectric structure 230
Have to should the first dielectric layer 23 side first surface 230a and this second dielectric layer 25
Side second surface 230b, wherein, the thermal coefficient of expansion of this first dielectric layer 23 is more than the
The thermal coefficient of expansion of two dielectric layers 25；One first line layer 22, it is located at this dielectric structure 230
First surface 230a on；One second line layer 26, it is located at the second of this dielectric structure 230
On the 230b of surface, the layout area of wherein this first line layer 22 is more than the second line layer 26
Layout area.
In the base plate for packaging 2 of the present invention, also include in this dielectric structure 230
Portion's line layer 24, additionally, be respectively equipped with this first dielectric layer 23 and this second dielectric layer 25
At least one conductive blind hole 231,251, makes this internal wiring layer 24 be electrically connected with this first line layer
22 and second line layer 26.
According in front described base plate for packaging 2, also include located at this first line layer 22 with this
The first welding resisting layer 28 in two line layers 26 and the second welding resisting layer 28 '.Additionally, this dielectric knot
This first surface 230a of structure 230 is to put brilliant side, and this second surface 230b is to plant ball side, and
This first welding resisting layer 28 that this puts brilliant side is provided with least one opening 280, in addition exposed portion this
One line layer 22, and then electron-donating connection semiconductor wafer, this second welding resisting layer of this plant ball side
28 ' are provided with least one perforate 280 ', are formed for exposing outside this second line layer 26 of part
Plant ball pad.
In addition, in aforementioned encapsulation substrate and its preparation method, this dielectric structure can be not restricted to two layers
Dielectric layer and one layer of internal wiring layer, that is, this dielectric structure can be provided with more than two layers multiple
Dielectric layer and multiple internal wiring layer, this internal wiring layer plurality of can pass through be formed at multiple
Conductive blind hole in this dielectric layer and be electrically connected with each other, be even electrically connected to this first line
Layer and the second line layer.
Additionally, main in the preparation method of aforementioned encapsulation substrate pass through to put brilliant side (First Line layer side) in this
Proceed by processing procedure, certainly also can proceed by processing procedure from this plant ball side (the second line layer side).
Refer to Fig. 3 a to Fig. 3 c, be the cuing open of preparation method second embodiment of the base plate for packaging of the present invention
Depending on schematic diagram.The preparation method of second embodiment is roughly the same with the preparation method of first embodiment, mainly poor
Has larger layout area by being initially formed on bearing part in the different preparation method being first embodiment
First line layer, re-forms the second line layer of tool smaller wiring area, and in second embodiment
Preparation method in by the second line layer of tool smaller wiring area, then shape are initially formed on bearing part
Become to have the first line layer of larger layout area.
As shown in Figure 3 a, a bearing part 31 is provided, and forms one second on this bearing part 31
Line layer 36.This bearing part 31 is, for example, the conductive or non-conductive hard plates such as corrosion resistant plate, and
This second line layer 36 is, for example, copper or other conductive material.
In certain embodiments, before forming this second line layer 36 on this bearing part 31,
A crystal seed layer 311, such as copper crystal seed layer can be formed prior to this bearing part 31, pass through so that profit is follow-up
The modes such as plating form this second line layer 36.
Form the second dielectric layer 35 on this bearing part 31 and this second line layer 36, its
In the material of this second dielectric layer 35 be, for example, glass fibre.
Form internal wiring layer 34 on this second dielectric layer 35, and in this second dielectric layer
Form conductive blind hole 351 to be electrically connected with this internal wiring layer 34 and this second line layer in 35
36.
First dielectric layer 33 is then formed on this second dielectric layer 35 and internal wiring layer 24.
Wherein, the thermal coefficient of expansion (cte) of this first dielectric layer 33 is more than the heat of this second dielectric layer 35
The coefficient of expansion, is greater than 10ppm/ DEG C.The material of this first dielectric layer 33 another is, for example, glass
Fiber.
Form first line layer 32 on the first dielectric layer 33, and in this first dielectric layer 33
Middle formation conductive blind hole 331 is to be electrically connected with this internal wiring layer 34 and this first line layer 32.
In this, this first dielectric layer 33 and this second dielectric layer 35 constitute a dielectric structure 330,
Wherein, this dielectric structure 330 have to should first line layer 32 side first surface
330a with to should the second line layer 36 side second surface 330b, wherein, this first
The layout area of line layer 32 is more than the layout area of this second line layer 36, and this first Jie
The thermal coefficient of expansion of electric layer 33 is more than the thermal coefficient of expansion of this second dielectric layer 35.
In the present embodiment, the layout area of this first line layer 32 is this first line layer 32
Area about 53% shared by this first dielectric layer 33；The layout area of this second line layer 36 is
Area about 47% shared by this second dielectric layer 35 for this second line layer 36, but be not limited.
Separately, for example, 11ppm/ DEG C of the thermal coefficient of expansion of this first dielectric layer 33, and this second dielectric layer
For example, 3ppm/ DEG C of 35 thermal coefficient of expansion, but be not limited.
Then protective layer 37 is formed on this first line layer 32 and this first dielectric layer 33.Should
Protective layer 37 is used to protect this first line layer 32 exposing in successive process.This protective layer
37 is, for example, dry film.
As shown in Figure 3 b, remove this bearing part 31, to expose outside this second line layer 36, its
In the exposed surface of this second line layer 36 flush with the exposed surface of this second dielectric layer 35.
In addition, as correspondence previously on this bearing part 31, be formed with crystal seed layer 311 when, in removing
This crystal seed layer 311 is also removed to expose the second line layer 36 while this bearing part 31.
Then remove this protective layer 37 to expose outside this first line layer 32.
As shown in Figure 3 c, respectively at first surface 330a and second table of this dielectric structure 330
The first welding resisting layer covering this first line layer 32 and this second line layer 36 is formed on the 330b of face
38 and second welding resisting layer 38 ', wherein, this first welding resisting layer 38 is formed with least one opening 380,
This first line layer 32 of exposed portion in addition, to be provided as chip connecting area, in addition, this second
Welding resisting layer 38 ' is also formed with least one perforate 380 ', in addition this second line layer of exposed portion
36, to be provided as planting the plant ball pad of soldered ball.
In sum, embodiments of the invention can reach following advantages or effect.The envelope of the present invention
Dress substrate, mainly by the first dielectric layer 23,33 thermal coefficient of expansion be more than the second dielectric layer 25,
35 thermal coefficient of expansion, and the layout area of first line layer 22,32 is more than the second line layer
26th, 36 layout area, with follow-up encapsulation process, when carrying out the cooling rank in hot processing procedure
Duan Shi, the first dielectric layer because of substrate uses high thermal expansion coefficient material, it is possible to provide larger receipts
Contracting power, to provide base plate for packaging 2 one reverse contractility, with offset because first line layer 22,
The warping phenomenon of 26 different from the second line layer 26,36 closenesses caused " anti-smile ".
The principle only in order to the illustrative present invention for the above-described embodiment and its effect, not for
Limit the present invention.Any those skilled in the art all can be in the spirit and the scope without prejudice to the present invention
Under, above-described embodiment is modified.Therefore the scope of the present invention, should be as right
Listed by claim.
Claims (13)
1. a kind of base plate for packaging, it is characterized by, this base plate for packaging includes:
One dielectric structure, including at least having one first dielectric layer and one second dielectric layer, and this Jie
Electric structure have to should the first dielectric layer side a first surface and this second dielectric layer
One second surface of side, wherein, the thermal coefficient of expansion of this first dielectric layer is more than this second Jie
The thermal coefficient of expansion of electric layer；
One first line layer, it is on this first surface of this dielectric structure；And
One second line layer, it is on this second surface of this dielectric structure, and this First Line
The layout area of road floor is more than the layout area of this second line layer.
2. base plate for packaging as claimed in claim 1, it is characterized by, this base plate for packaging also comprises
There is an internal wiring layer in this dielectric structure.
3. base plate for packaging as claimed in claim 2, it is characterized by, respectively this first dielectric layer with
This second dielectric layer includes at least one conductive blind hole, so that this internal wiring layer passes through this conduction
Blind hole is electrically connected with this first line layer and this second line layer.
4. base plate for packaging as claimed in claim 1, it is characterized by, this first surface is to put crystalline substance
Side, this second surface is to plant ball side.
5. base plate for packaging as claimed in claim 1, it is characterized by, this base plate for packaging also comprises
There is one first welding resisting layer and one second being respectively arranged on this first line layer and this second line layer
Welding resisting layer.
6. base plate for packaging as claimed in claim 5, it is characterized by, this first welding resisting layer is provided with
At least one opening, puts a chip for connecing, and this second welding resisting layer is provided with least one perforate, for
As plant ball pad.
7. base plate for packaging as claimed in claim 1, it is characterized by, the heat of this first dielectric layer
The coefficient of expansion is more than 10ppm/ DEG C.
8. a kind of preparation method of base plate for packaging, it is characterized by, this preparation method includes:
One first line layer is formed on a bearing part；
One first dielectric layer is formed on this first line layer；
One second dielectric layer is formed on this first dielectric layer, with make this first dielectric layer and this
Two dielectric layers constitute a dielectric structure；And
Form one second line layer on this second dielectric layer, wherein when the cloth of this first line layer
When line area is more than the layout area of this second line layer, the thermal coefficient of expansion of this first dielectric layer
Thermal coefficient of expansion more than this second dielectric layer；Wherein when the layout area of this first line layer is little
When the layout area of this second line layer, the thermal coefficient of expansion of this first dielectric layer be less than this
The thermal coefficient of expansion of two dielectric layers.
9. the preparation method of base plate for packaging as claimed in claim 8, it is characterized by, this preparation method is also wrapped
Include:
Form a protective layer on this second line layer；
Remove this bearing part, to expose this first line layer；And
Remove this protective layer, to expose this second line layer.
10. the preparation method of base plate for packaging as claimed in claim 9, it is characterized by, this preparation method is also wrapped
Include:
One first welding resisting layer and one the are formed on this first line layer and this second line layer
Two welding resisting layers.
The preparation method of 11. base plate for packaging as claimed in claim 10, it is characterized by, this preparation method is also
Including:
Form at least one opening in this first welding resisting layer, put a chip for connecing, and in this
Form at least one perforate, to be provided as planting ball pad in second welding resisting layer.
The preparation method of 12. base plate for packaging as claimed in claim 8, it is characterized by, this preparation method is also wrapped
Include:
Form at least one internal wiring layer in this dielectric structure.
The preparation method of 13. base plate for packaging as claimed in claim 12, it is characterized by, this preparation method is also
Including:
Form at least one conductive blind hole in respectively this first dielectric layer with this second dielectric layer, make this
Internal wiring layer is electrically connected with this first line layer and this second line layer through this conductive blind hole.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW104123199A TWI573231B (en) | 2015-07-17 | 2015-07-17 | Package substrate and method of manufacture thereof |
| TW104123199 | 2015-07-17 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106356357A true CN106356357A (en) | 2017-01-25 |
Family
ID=57842746
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510529973.9A Pending CN106356357A (en) | 2015-07-17 | 2015-08-26 | Package substrate and method for fabricating the same |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN106356357A (en) |
| TW (1) | TWI573231B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114695308A (en) * | 2021-11-08 | 2022-07-01 | 友达光电股份有限公司 | Package structure |
| CN116130448A (en) * | 2021-11-15 | 2023-05-16 | 芯爱科技(南京)有限公司 | Electronic package and package substrate thereof |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10522512B2 (en) * | 2018-05-02 | 2019-12-31 | Powertech Technology Inc. | Semiconductor package and manufacturing method thereof |
| TWI835561B (en) * | 2023-02-16 | 2024-03-11 | 大陸商芯愛科技（南京）有限公司 | Electronic package, package substrate and fabricating method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001217514A (en) * | 2000-02-03 | 2001-08-10 | Denso Corp | Multi-layered wiring board |
| US20130240258A1 (en) * | 2012-03-19 | 2013-09-19 | Ibiden Co., Ltd. | Printed wiring board |
| CN104284511A (en) * | 2013-07-12 | 2015-01-14 | 揖斐电株式会社 | Printed wiring board |
| CN104582252A (en) * | 2013-10-25 | 2015-04-29 | 三星电机株式会社 | Printed curcuit board and manufacturing method of the same |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW564533B (en) * | 2002-10-08 | 2003-12-01 | Siliconware Precision Industries Co Ltd | Warpage-preventing substrate |
| JP2009135184A (en) * | 2007-11-29 | 2009-06-18 | Shinko Electric Ind Co Ltd | Wiring substrate and manufacturing method thereof |
| KR20110030152A (en) * | 2009-09-17 | 2011-03-23 | 삼성전기주식회사 | Package board and manufacturing method |
| TWI476841B (en) * | 2012-03-03 | 2015-03-11 | 矽品精密工業股份有限公司 | Semiconductor package and fabrication method thereof |
| TWI518852B (en) * | 2013-10-02 | 2016-01-21 | 矽品精密工業股份有限公司 | Semiconductor package and manufacturing method thereof |
-
2015
- 2015-07-17 TW TW104123199A patent/TWI573231B/en active
- 2015-08-26 CN CN201510529973.9A patent/CN106356357A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001217514A (en) * | 2000-02-03 | 2001-08-10 | Denso Corp | Multi-layered wiring board |
| US20130240258A1 (en) * | 2012-03-19 | 2013-09-19 | Ibiden Co., Ltd. | Printed wiring board |
| CN104284511A (en) * | 2013-07-12 | 2015-01-14 | 揖斐电株式会社 | Printed wiring board |
| CN104582252A (en) * | 2013-10-25 | 2015-04-29 | 三星电机株式会社 | Printed curcuit board and manufacturing method of the same |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114695308A (en) * | 2021-11-08 | 2022-07-01 | 友达光电股份有限公司 | Package structure |
| CN116130448A (en) * | 2021-11-15 | 2023-05-16 | 芯爱科技(南京)有限公司 | Electronic package and package substrate thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201705381A (en) | 2017-02-01 |
| TWI573231B (en) | 2017-03-01 |
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