CN115633265B

CN115633265B - Photosensitive pixel circuit, image sensor, and electronic apparatus

Info

Publication number: CN115633265B
Application number: CN202211220426.9A
Authority: CN
Inventors: 罗轶
Original assignee: Vivo Mobile Communication Co Ltd
Current assignee: Vivo Mobile Communication Co Ltd
Priority date: 2022-09-30
Filing date: 2022-09-30
Publication date: 2024-09-03
Anticipated expiration: 2042-09-30
Also published as: CN115633265A; WO2024067510A1

Abstract

The application discloses a photosensitive pixel circuit, and belongs to the technical field of image sensors. The photosensitive pixel circuit comprises: a photosensitive unit, a photosensitive signal processing circuit and a gain mode selection circuit; the photosensitive unit is connected with the photosensitive signal processing circuit; the gain mode selection circuit outputs a gain mode selection signal, and the gain mode selection circuit is connected with the photosensitive signal processing circuit; the photosensitive signal processing circuit comprises a photosensitive signal reading unit and a gain processing unit, the photosensitive signal reading unit is connected with the photosensitive unit to receive the initial photosensitive signal, the gain processing unit is connected with the gain mode selection circuit to receive the gain mode selection signal, and the gain processing unit is connected with the photosensitive signal reading unit; the photosensitive signal processing circuit determines a gain processing mode for the initial photosensitive signal according to the gain mode selection signal. The embodiment of the application can realize the dynamic range modulation of the pixel level, reduce the energy consumption, and has the advantages of relatively simple structure and wider application range.

Description

Photosensitive pixel circuit, image sensor, and electronic apparatus

Technical Field

The application belongs to the technical field of image sensors, and particularly relates to a photosensitive pixel circuit, an image sensor and electronic equipment.

Background

With the development of shooting technology, a dual gain-high dynamic range (Dual Conversion Gain-HIGH DYNAMIC RANGE, DCG-HDR) technology in an image sensor is also becoming more and more important. Currently, there are two ideas for DCG-HDR technology:

The first idea is as follows: since the mobile terminal is limited by wiring space or the like, pixel-by-pixel modulation cannot be achieved. Therefore, in the related art, each pixel structure in the pixel array is exposed in a high conversion gain (High Conversion Gain, HCG) mode, and the first image information in the HCG mode is read; exposing each pixel structure in a low conversion gain (Low Conversion Gain, LCG) mode, and reading second image information in the LCG mode; finally, the final HDR (HIGH DYNAMIC RANGE ) image is output after the first image information and the second image information are selected/cropped/optimized/synthesized by a back-end image signal Processor (IMAGE SIGNAL Processor, ISP).

The second idea is as follows: a complex system is formed by adopting a complex image sensor chip and an off-chip optical coding device, and step-by-step exposure is performed. The off-chip optical coding device comprises various components, such as an ocular lens, a conductive head group, a polarization beam splitter, an encoder and the like, which are installed through a complex connecting structure.

The inventors found during the course of the study that:

For the first idea, since the first image information in the HCG mode and the second image information in the LCG mode (i.e., two frames of images are required) are required at the same time, time is consumed, and at the same time, powerful image signal processing capability of the ISP is required, so that energy consumption is also consumed; furthermore, because of the processing defect of ISP in choosing the image signal, the HDR image synthesized by the first image information and the second image information may have brightness or/and color layering and signal to noise ratio (Signal to Noise Ratio, SNR) drop (Dip), that is, in some scenes with complex brightness variation, the synthesized HDR image may have a problem that a part of pixels are partially overexposed or a part of pixels are partially underexposed, and the overexposed part of pixels or the underexposed part of pixels cannot be simultaneously compensated.

For the second approach, current pixel-by-pixel exposure time control techniques, while implementing pixel-level dynamic range modulation, avoid overexposure or underexposure problems. However, the implementation of the pixel-by-pixel exposure time control technology is too complex, and precise calibration between different devices is required, that is, the pixel-by-pixel exposure time control technology has the problems of volume, power consumption, difficult teaching and the like, so that the application range of the pixel-by-pixel exposure time control technology is limited.

Disclosure of Invention

The embodiment of the application aims to provide a photosensitive pixel circuit, an image sensor and electronic equipment, which can realize pixel-level dynamic range modulation and avoid the problem of overexposure or underexposure.

In a first aspect, an embodiment of the present application provides a photosensitive pixel circuit, including a photosensitive unit, a photosensitive signal processing circuit, and a gain mode selection circuit;

the photosensitive unit comprises a photosensitive element (PD) for generating an initial photosensitive signal, and the photosensitive unit is connected with the photosensitive signal processing circuit;

The gain mode selection circuit outputs a gain mode selection signal, and the gain mode selection circuit is connected with the photosensitive signal processing circuit;

The photosensitive signal processing circuit comprises a photosensitive signal reading unit and a gain processing unit, the photosensitive signal reading unit is connected with the photosensitive unit to receive the initial photosensitive signal, the gain processing unit is connected with the gain mode selection circuit to receive the gain mode selection signal, and the gain processing unit is connected with the photosensitive signal reading unit;

the photosensitive signal processing circuit determines a gain processing mode for the initial photosensitive signal according to the gain mode selection signal.

In a second aspect, embodiments of the present application provide an image sensor comprising the photosensitive pixel circuit of the first aspect.

In a third aspect, an embodiment of the present application provides an electronic device, including the image sensor of the second aspect.

In the embodiment of the application, the gain mode selection circuit is arranged and can output the gain mode selection signal to the gain processing unit of the photosensitive signal processing circuit, so that the photosensitive signal processing circuit can determine the gain processing mode of the initial photosensitive signal according to the gain mode selection signal, and then the gain processing mode of each photosensitive pixel circuit can be controlled by the gain mode selection circuit, so that the photosensitive pixel circuit and a use scene can be enabled to select and use the working mode of the scene, the dynamic range modulation of the pixel level is realized, and the overexposure or underexposure conditions are reduced.

And because the circuit structure is simple, the gain processing mode of the initial photosensitive signal can be adaptively adjusted, two images are not required to be acquired for processing, and the energy consumption is reduced. The method can also effectively reduce the problem of partial overexposure or partial underexposure of partial pixels in some scenes with complicated brightness and darkness changes, and can simultaneously compensate the overexposed partial pixels or the underexposed partial pixels.

Furthermore, the pixel structure of the application comprises a photosensitive unit, a photosensitive signal processing circuit and a gain mode selection circuit, and the photosensitive pixel circuit capable of performing pixel-by-pixel control is formed by the circuits, so that the structure for realizing the pixel-by-pixel exposure time is relatively simple, and the application range is wider.

Drawings

Fig. 1 is a schematic structural diagram of a photosensitive pixel circuit according to an embodiment of the present application;

FIG. 2 is a schematic diagram of a photosensitive pixel circuit according to another embodiment of the present application;

FIG. 3 is a schematic diagram of a photosensitive pixel circuit according to another embodiment of the present application;

FIG. 4 is a schematic diagram of a photosensitive pixel circuit according to another embodiment of the present application;

fig. 5 is a schematic structural diagram of a gain mode selection circuit according to an embodiment of the present application;

FIG. 6 is a schematic diagram of a gain mode selection circuit according to an embodiment of the present application;

FIG. 7 is a schematic circuit diagram of a photosensitive pixel circuit according to an embodiment of the present application;

FIG. 8 is a schematic circuit diagram of a photosensitive pixel circuit according to another embodiment of the present application;

FIG. 9 is a schematic circuit diagram of yet another embodiment of a photosensitive pixel circuit;

FIG. 10 is a schematic circuit diagram of a photosensitive pixel circuit according to another embodiment of the present application;

FIG. 11 is a schematic circuit diagram of a photosensitive pixel circuit according to another embodiment of the present application;

FIG. 12 is a schematic circuit diagram of a photosensitive pixel circuit according to another embodiment of the present application;

FIG. 13 is a schematic circuit diagram of a photosensitive pixel circuit according to another embodiment of the present application;

fig. 14 is a schematic circuit diagram of another photosensitive pixel circuit according to an embodiment of the application.

Detailed Description

The technical solutions of the embodiments of the present application will be clearly described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which are obtained by a person skilled in the art based on the embodiments of the present application, fall within the scope of protection of the present application.

In the present application, "ground terminal", "first ground terminal", "second ground terminal", "third ground terminal" may represent the same ground terminal to which ground level is connected in an actual circuit.

The terms first, second and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate, such that embodiments of the application may be practiced otherwise than as specifically illustrated and described herein, and that the objects identified by "first," "second," etc. are generally of the same type and are not limited to the number of objects, such as the first object may be one or at least two. Furthermore, in the description and claims, "and/or" means at least one of the connected objects, and the character "/", generally means that the associated object is an "or" relationship.

The photosensitive pixel circuit provided by the embodiment of the application is described in detail below through specific embodiments and application scenes thereof with reference to the accompanying drawings.

An embodiment of the present application provides a pixel structure, as shown in fig. 1, the photosensitive pixel circuit includes: a photosensitive unit 10, a photosensitive signal processing circuit 11, and a gain mode selection circuit 12;

The photosensitive unit 11 includes a photosensitive element 101 for generating an initial photosensitive signal, and the photosensitive unit 10 is connected to the photosensitive signal processing circuit 11;

The gain mode selection circuit 12 outputs a gain mode selection signal, and the gain mode selection circuit 12 is connected with the photosensitive signal processing circuit 11;

The photosensitive signal processing circuit 11 includes a photosensitive signal reading unit 112 and a gain processing unit 111, the photosensitive signal reading unit 112 is connected with the photosensitive unit 10 to receive the initial photosensitive signal, the gain processing unit 111 is connected with the gain mode selection circuit 11 to receive the gain mode selection signal, and the gain processing unit 111 is connected with the photosensitive signal reading unit 112;

The photosensitive signal processing circuit 11 determines a gain processing mode for the initial photosensitive signal based on the gain mode selection signal.

The output end of the photosensitive signal processing circuit 11 is the output end of the photosensitive pixel circuit.

The input terminal of the gain mode selection circuit 12 inputs an initial selection signal, then outputs a gain mode selection signal to the gain processing unit 111, and then the gain processing unit 111 selects a gain processing mode corresponding to the gain mode selection signal according to the gain mode selection signal.

In the embodiment of the present application, the specific circuit structures of the photosensitive unit 10, the photosensitive signal processing circuit 12, and the gain mode selection circuit 12 of the photosensitive unit 10 are not limited, as long as the response function is satisfied within the range of protection of the photosensitive pixel circuit provided by the embodiment of the present application.

In one possible implementation, the gain processing modes may include two modes of operation, HCG and LCG, with different gain mode selection signals corresponding to different modes of operation.

The gain mode selection signal is, for example, a high level signal corresponding to HCG and a high level signal corresponding to LCG.

In some possible embodiments, the initial selection signal input by the selection signal input terminal dcg_sel may be different level signals in the configuration phase and the reading phase within a frame time, or may be the same level signal, which determines the operation mode of each pixel structure according to the current usage scenario.

For the configuration stage, the gain mode selection signal may be at a first level or a second level, and specifically needs to be determined according to the relationship between the gain mode selection signal output by the gain mode selection circuit 12 and the input initial selection signal; for the reading stage, the operation mode of each pixel structure determined according to the current usage scenario may be determined, for example, the gain mode selection signal corresponding to the photosensitive pixel circuit 1 may be 1, and the gain mode selection signal corresponding to the photosensitive pixel circuit 2 may be 0 for the same usage scenario. The usage scene may be identified by the electronic device to determine a preview image of the camera, for example, identify the content of the preview image, determine that the preview image is overexposed or underexposed, if the preview image is overexposed, the LCG mode needs to be entered, if the preview image is underexposed, the HCG mode needs to be entered, or identify the usage scene according to a scene mode selected by a user, and determine that the LCG mode or the HCG mode needs to be entered.

In the embodiment of the present application, since the gain mode selection circuit 12 is provided, the gain mode selection circuit 12 can output a gain mode selection signal to the gain processing unit 111 of the photosensitive signal processing circuit 11, so that the photosensitive signal processing circuit 11 can determine the gain processing mode for the initial photosensitive signal according to the gain mode selection signal, and each photosensitive pixel circuit can control the gain processing mode thereof through the gain mode selection circuit 12, so that the photosensitive pixel circuit and the usage scene can select and use the working mode of the scene, the dynamic range modulation of the pixel level can be realized, and the overexposure or underexposure conditions can be reduced.

Furthermore, since the pixel structure of the present application includes the photosensitive unit 10, the photosensitive signal processing circuit 11 and the gain mode selection circuit 12, the above-mentioned several circuits constitute a photosensitive pixel circuit capable of performing pixel-by-pixel control, so that the structure for realizing the pixel-by-pixel exposure time is relatively simple, and the application range is wider.

In some embodiments of the present application, referring to fig. 2, the photosensitive signal processing circuit further includes a reset unit 113, the reset unit 113 is connected to the gain processing unit 111, and the reset unit 113 is configured to reset the photosensitive signal processing circuit 11.

Referring to fig. 7, the reset unit 113 includes a fourth transistor M4, a reset signal input terminal, a power signal input terminal VDD, and a reset signal output terminal.

When the fourth transistor is a P-type transistor, the gate of the fourth transistor M4 is used as a reset signal input terminal and is connected to the reset signal terminal RST; the source of the fourth transistor M4 is connected to the power supply VDD as a power supply signal input terminal, and the drain of the fourth transistor M4 is connected to the fifth transistor M5 as a reset signal output terminal. RST inputs a reset signal, such as a low level, and the fourth transistor M4 is turned on to reset the photosensitive pixel circuit. The fourth transistor M4 is turned off at high level

When the fourth transistor is an N-type transistor, the gate of the fourth transistor M4 is connected to the reset signal terminal RST, and the drain of the fourth transistor M4 is connected to the power supply VDD as the power supply signal input terminal; the source of the fourth transistor M4 is connected to the fifth transistor M5 as a reset signal output terminal. RST inputs a reset signal, such as a high level, and the fourth transistor M4 is turned on to reset the photosensitive pixel circuit.

It should be noted that, the transistors at other positions in the embodiments of the present application may be N-type or P-type, and then electrically connected according to the N-type or P-type principle and provide corresponding on or off signals.

In some embodiments of the present application, the gain mode selection circuit 12 has a selection signal input dcg_sel, a selection signal output and a selection control signal input CTRL, the selection signal output being electrically connected to the gain processing unit 111;

The selection signal input end is used for accessing an initial selection signal DCG_SEL, the selection control signal input end is used for accessing a selection control signal CTRL, and the selection signal output end is used for outputting the gain mode selection signal according to the initial selection signal DCG_SEL under the control of the selection control signal CTRL.

It will be appreciated that the initial selection signal dcg_sel for selecting the access of the control signal input may be a constant first level signal or a square wave signal during a frame time. In the case where the initial selection signal dcg_sel is constant to the first level signal, the gain mode selection signal output from the selection signal output terminal is directly output to the input terminal of the gain processing unit 111 of the photosensitive signal processing circuit 11; in the case where the initial selection signal dcg_sel is a square wave signal, and the square wave signal includes a first level signal and a second level signal, the voltage of the first level signal is greater than the voltage of the second level signal, the initial selection signal dcg_sel input to the selection signal input terminal or the gain mode selection signal obtained based on the initial selection signal dcg_sel may be buffered in the gain mode selection circuit 11 first, and then the gain mode selection signal is output to the photosensitive signal processing circuit 11 when necessary.

Referring to fig. 7, the gain mode selection circuit 12 has a selection signal input terminal, a selection control signal input terminal, and a selection signal output terminal, the selection signal output terminal being connected to the gate of the fifth transistor M5. The selection control signal input terminal is used for receiving a selection control signal CTRL; the selection signal input terminal is connected to the initial selection signal dcg_sel, and then the selection control signal input terminal may control the gain mode selection signal output from the selection signal output terminal to be at a high level or a low level, so as to turn on or off the fifth transistor M5, thereby controlling the 2-photosensitive signal processing circuit 11 to use the HCG or LCG mode, i.e., the high exposure operation mode or the low exposure operation mode.

Note that, referring to fig. 3 and 7, only the buffer element 121 having the buffer function is included, and the buffer element 121 includes the second transistor M2 and the first buffer capacitor C1. The output end of the first buffer element is a selection signal output end. Referring to fig. 8, with respect to fig. 7, a selection switching element 122 is added on the basis of fig. 7, and the selection switching element 122 may be the first transistor M1 in fig. 8, and then the output terminal of the first transistor M1 is a selection signal output terminal.

In some embodiments of the present application, the gain mode selection circuit 12 further includes a buffer element 121 and a selection switch element 122,

The buffer element 121 is electrically connected to the selection signal input terminal, the buffer element 121 is electrically connected to the selection signal output terminal, and the buffer element is used for storing the initial selection signal dcg_sel or the gain mode selection signal;

The first end of the selection switch element 122 is connected to the selection signal output end to receive the gain mode selection signal, the second end of the selection switch element 122 is connected to the gain processing unit 111, and the control end of the selection switch element 122 is connected to an enable control signal to output the gain mode selection signal to the gain processing unit 122 when the gain processing mode of the initial photosensitive signal needs to be switched.

It is understood that the selection switch element 122 may be the first transistor M1 as shown in fig. 8. A first transistor M1 controlled by an enable control signal EN is provided between the output of the buffer element 121 and the gain processing unit 111, and the enable control signal EN may be kept low or "0" such that the first transistor M1 is turned off when the photosensitive pixel circuit is being updated with the gain mode selection signal in the read phase. After the photosensitive pixel circuit updates the initial selection signal dcg_sel or the gain mode selection signal buffered in the corresponding buffer element 121, the photosensitive pixel circuit is determined according to the shooting requirement, and the enable control signal EN corresponding to the photosensitive pixel circuit can be pulled up, so that the gain mode selection signal buffered in the buffer element 121 of the photosensitive pixel circuit is output to the gain processing unit 111, so as to control the photosensitive signal reading unit 112 to operate in HCG or LCG mode. The photosensitive signal processing circuit 11 in each pixel structure is favorable for obtaining a mode selection signal, amplifying the electric signal of the photosensitive unit 10 and reading the image information.

Of course, the enable control signal EN may be held low or "0" such that the first transistor M1 is turned off while each photosensitive pixel circuit in the pixel array is being updated with the gain mode selection signal in the read phase. After the pixel structures in the pixel array are updated with the gain mode selection signals buffered in the corresponding buffer element 121, the enable control signals EN corresponding to all the photosensitive pixel circuits in the pixel array can be pulled up simultaneously, so that the gain mode selection signals 112 buffered in the buffer element 121 of the photosensitive pixel circuit are output to the gain processing unit simultaneously, so as to control the photosensitive signal reading unit 112 to work in the HCG or LCG mode, which is beneficial for the photosensitive signal processing circuit 11 in each pixel structure to obtain the gain mode selection signals, and simultaneously amplify the electrical signals of the photosensitive unit, and simultaneously read the image information, thereby realizing the global shutter of the CMOS image sensor.

Through the mode, the gain mode selection signal can be temporarily stored by the buffer element, and then the gain mode selection signal temporarily stored by the buffer element is output through the selection switch element when the gain mode needs to be changed. Or by the above way, the initial selection signal can be temporarily stored by the buffer element, and then the initial selection signal temporarily stored by the buffer element is adjusted to the required gain mode selection signal by the selection switch element when the gain mode needs to be changed for output operation.

In some embodiments of the present application, the gain mode selection circuit 12 includes a first switching element M2 and a first buffer capacitor C1;

the control end of the first switching element M2 is the selection control signal input end, the first end of the first switching element M2 is the selection signal input end, the second end of the first switching element M2 is electrically connected to the first end of the buffer capacitor, the first end of the buffer capacitor is electrically connected to the selection signal output end, and the second end of the first buffer capacitor C1 is grounded.

It should be noted that the first switching element M2 and the first buffer capacitor C1 may form the buffer element 121.

As shown in fig. 7, the first switching element M2 may be a second transistor M2, the buffer capacitor is C1, and the buffer element 121 is formed by the first buffer capacitor C1 and the ground GND; the control end of the second transistor M2 is a selection control signal input end CTRL; the first end of the second transistor M2 is a selection signal input end and receives an initial selection signal DCG_SEL; the second end of the second transistor M2 is connected to the first end of the first buffer capacitor C1, and the second end of the first buffer capacitor C1 is grounded GND. By means of the buffer capacitor, the gain mode selection signal can be buffered more simply.

In some embodiments of the present application, the gain mode selection circuit 12 includes a flip-flop 123, the flip-flop 123 having the selection signal input D, the selection signal output Q, and the selection control signal input.

The selection signal input end D is used for accessing an initial selection signal DCG_SEL, the selection control signal input end is used for accessing a selection control signal CTRL, and the selection signal output end Q is used for outputting the gain mode selection signal according to the initial selection signal under the control of the selection control signal CTRL.

In the embodiment of the present invention, the output of the gain mode selection signal can also be realized by adopting the manner of the trigger 123, thereby realizing the selection of the gain mode.

In an embodiment of the present invention, the trigger 123 may be an implementation of the buffer element 121.

Alternatively, referring to fig. 5, a selection switch element 122 may be added after the flip-flop 123, the selection signal output terminal of the flip-flop 123 is connected to the first terminal of the selection switch element 122, and the second terminal of the selection switch element 122 is connected to the gain processing unit 111. Referring to fig. 13, the flip-flop 123 includes a signal input terminal D for receiving an initial selection signal dcg_sel. The selection signal output terminal Q and the selection control signal input terminal are configured to receive a selection control signal CTRL. The selection signal output terminal Q is connected to the input terminal of the first transistor M1, and the output terminal of the first transistor M1 is connected to the gain processing unit 111.

In the embodiment of the present invention, the gain mode selection signal may be temporarily stored by the trigger 123, and then the gain mode selection signal temporarily stored by the trigger 123 is output by the selection switch 122 when the gain mode needs to be changed. Or by the above way, the initial selection signal can be temporarily stored by the trigger 123, and then the initial selection signal temporarily stored by the trigger 123 is adjusted to the required gain mode selection signal to perform the output operation by selecting the switching element when the gain mode needs to be changed.

In one embodiment of the present application, only the flip-flop 123 may be left, the selection switch element 122 may be omitted, and the selection signal output terminal of the flip-flop 123 may be connected to the gain processing unit 111. Referring to fig. 11, the flip-flop G1 includes a signal input terminal D for receiving an initial selection signal dcg_sel. The selection signal output terminal Q and the selection control signal input terminal are configured to receive a selection control signal CTRL. The selection signal output terminal Q is connected to the gain processing unit 111.

In some embodiments of the present application, referring to fig. 11, the flip-flop 123 is a digital signal flip-flop G1, and the flip-flop 123 further has a set signal terminal S and a reset signal terminal R; under the condition that the setting signal end loads a first level, the gain mode selection signal output by the selection signal output end Q enables the photosensitive signal processing circuit 11 to work in a first gain processing mode; when the reset signal terminal is loaded with a second level, the gain mode selection signal output by the selection signal output terminal Q makes the photosensitive signal processing circuit 11 operate in a second gain processing mode.

The setting signal end S and the resetting signal end R of the digital signal trigger G1 can cancel the self-adaptive selection mode function of the gain mode selection circuit when being triggered respectively, so that the photosensitive pixel circuit is fixed in a certain gain mode, and the power consumption can be reduced.

In some embodiments of the present application, the digital signal Flip-Flop G1 may be a digital DFlip-Flop (Data Flip-Flop), i.e., a D signal Flip-Flop G1; the selection signal input terminal D of the D signal flip-flop G1 receives the initial selection signal dcg_sel; the selection control signal input end of the D signal trigger G1 receives a control signal CTRL; the selection signal output terminal Q of the D signal flip-flop G1 outputs a gain mode selection signal. The selection control signal input terminal may be an input terminal of a clock signal.

Based on the operating principle of the D-signal flip-flop G1, if the dcg_sel signal needs to be buffered, the control signal CTRL needs a rising edge signal (the rising edge of the clock signal, i.e. the process of changing the signal from "0" to "1"). At this time, the external gain mode selection signal dcg_sel will be buffered in this D signal flip-flop G1. When the control signal CTRL signal provides a falling edge signal (falling edge of the clock signal, i.e., the process of changing the signal from "1" to "0"), the selection signal output terminal Q of the D signal flip-flop G1 outputs the buffered gain mode selection signal dcg_sel. The gain mode selection signal dcg_sel outside the D signal flip-flop G1 needs to cooperate with the control signal CTRL to complete the buffering and outputting of the mode selection signal dcg_sel signal, and control the pixel structure to operate in HCG or LCG mode. When the control signal CTRL signal is maintained at "0", the dcg_sel signal buffered in the D signal flip-flop G1 remains unchanged regardless of the change of the gain mode selection signal dcg_sel signal external to the D signal flip-flop G1.

It will be understood that, in the D signal flip-flop G1, the S signal of the set signal terminal S (when the signal is set to "1", the selection signal output terminal Q forcibly outputs "1", Q 'forcibly outputs "0") and the R signal of the reset signal terminal R (when the signal is set to "1", the output terminal Q forcibly outputs "0", Q' forcibly outputs "1") are set as optional signals, and the operation of the D signal flip-flop G1 is ensured without providing (not using). The signals at the two output terminals Q and Q' of the D signal flip-flop G1 are reciprocal signals. Therefore, the gain processing unit can be forced to be in a mode by setting the S signal of the signal terminal S or resetting the R signal of the signal terminal R.

Thus, in another embodiment, the selection signal output terminal of the D signal flip-flop G1 may also be Q ', and the gain mode selection signal is output using Q'. In the middle mode, the corresponding relation between the gain mode selection signal and the HCG and LCG is adjusted according to the relation that the Q and Q' signals are reciprocal signals.

In some embodiments of the present application, referring to fig. 5, the gain mode selection circuit 12 includes a digital signal buffer 124, the digital signal buffer 124 having the selection signal input, the selection signal output, the selection control signal input, and a selection control signal input;

the selection signal input terminal is used for receiving an initial selection signal dcg_sel.

The selection signal output terminal is used for outputting a gain mode selection signal dcg_sel'.

The selection control signal input terminal is configured to receive a selection control signal CTRL, and a digital signal buffer unit 1241 configured to store the gain mode selection signal.

In the above manner, the initial selection signal dcg_sel may be converted into the gain mode selection signal dcg_sel' by the digital signal buffer 124 to be output, so as to select the operation mode.

In some embodiments of the present application, referring to fig. 5, the gain mode selection circuit 12 includes a first switching element M2 and a digital signal buffer unit 1241;

the digital signal buffer unit 1241 includes a first switching tube M11, a second switching tube M12, a third switching tube M13, and a fourth switching tube M14;

the control end of the first switching element M2 is the selection control signal input end CTRL, the first end of the first switching element M2 is the selection signal input end dcg_sel, the second end of the first switching element M2 is electrically connected to the first end of the first switching tube M11, and the second end of the first switching element M2 is also electrically connected to the second end of the second switching tube M12;

the first switching tube M11 is of an N type, the control end of the first switching tube M11 is electrically connected with the control end of the second switching tube M12, and the second end of the first switching tube M11 is grounded;

The second switching tube M12 is of a P type, the control end of the second switching tube M12 is electrically connected with the first end of the third switching tube M13, the first end of the second switching tube M12 is connected with a power signal, and the second end of the second switching tube M12 is electrically connected with the control end of the third switching tube M13;

the third switching tube M13 is of an N type, a first end of the third switching tube M13 is electrically connected with a second end of the fourth switching tube M14, and a second end of the third switching tube M13 is grounded;

the fourth switching tube M14 is of a P type, the control end of the fourth switching tube M14 is electrically connected with the control end of the third switching tube M14, the first end of the fourth switching tube M14 is connected with the power signal, and the second end of the fourth switching tube M14 is electrically connected with the output end of the selection control signal.

The embodiment of the invention adopts four transistors, and can realize the buffer function and the gain mode selection signal output function with a simple circuit structure.

In some embodiments of the present application, the first switching element M2 may be a second transistor M2, and referring to fig. 5, the digital signal buffer 124 includes: a second transistor M2 and a digital signal buffer unit 1241; the control electrode of the second transistor M2 is electrically connected with the first control signal input end; a first electrode of the second transistor M2 is electrically connected to the selection signal input terminal; the second pole of the second transistor M2 is electrically connected with the input end of the digital signal buffer unit 1241; the output terminal of the digital signal buffer unit 1241 is connected to the first switching element M1 or to the gain processing unit 111.

It can be appreciated that the initial selection signal dcg_sel enters the digital signal buffer unit 1241 through the second transistor M2 controlled by the control signal CTRL. The buffered initial select signal dcg_sel is inverted to dcg_sel' and then output. Wherein, if the signal of the initial selection signal dcg_sel is "1", the signal of dcg_sel' is "0", and vice versa.

Referring to fig. 6, the first terminal of the selection switching element M8 is the selection signal input terminal dcg_sel, and the second terminal is connected to the first terminal of the first switching element M2. The control terminal of the switching element M8 is selected as the enable signal input terminal EN. In the embodiment of the present invention, before the first switching element M2, a selection switching element M8 may be further disposed, where the selection switching element M8 is configured to receive an enable signal, so as to start or stop the operation of the digital signal buffer 124.

In some embodiments of the present application, the gain mode selection circuit 12 further includes a selection switch element 122, a first end of the selection switch element 122 is connected to the selection signal output end to receive the gain mode selection signal, a second end of the selection switch element 122 is connected to the gain processing unit 111, and a control end of the selection switch element 122 is used for accessing an enable control signal EN to output the gain mode selection signal to the gain processing unit 111 when the gain processing mode of the initial photosensitive signal needs to be switched.

In the embodiment of the present invention, only the buffer element 121 may be provided, and the output end of the buffer element 121 may be directly connected to the gain processing unit 111, for example, the combination of the first switch element 121 and the first buffer capacitor C1, or the trigger 123, or the digital signal buffer G1, or the combination of the first switch element M2 and the digital signal buffer unit 1241. On the basis of this, as shown in fig. 3 and 4, a selection switch element 122 may be added on the basis of the above components, and an output terminal of the buffer element 121 may be connected to a first terminal of the selection switch element 122, and a second terminal of the selection switch element 122 is connected to the gain processing unit 111.

In some embodiments of the present application, referring to fig. 7, the photosensitive signal reading unit 11 includes a first storage capacitor C2, a signal amplifying element SF, and a read switching element M7;

a first end of the first storage capacitor C2 is electrically connected to the photosensitive unit 10 to receive the initial photosensitive signal, the first end of the first storage capacitor C2 is further connected to the gain processing unit 111, and a second end of the first storage capacitor C2 is grounded;

An input end of the signal amplifying element SF is connected with a first end of the first storage capacitor C2, and an output end of the signal amplifying unit SF is connected with a first end of the reading switch element M7 for outputting an amplified photosensitive signal;

the control end of the read switch element M7 is used for accessing an output control signal SEL, and the second end of the read switch element M7 is a photosensitive signal output end pix_out of the photosensitive pixel circuit.

In the embodiment of the present application, the signal amplifying element SF may be a transistor, an amplifier formed by a plurality of transistors, such as CTIA (Capacitive Transimpedance Amplifie) amplifier, or other amplifiers, which is not limited herein.

In some embodiments of the present application, referring to fig. 7, the signal amplifying element SF is an amplifying switch element SF, a control terminal of the amplifying switch element SF is connected to the first terminal of the first storage capacitor C2, a first terminal of the amplifying switch element is connected to the power signal VDD, and a second terminal of the amplifying switch element is electrically connected to the first terminal of the reading switch element M7.

In the embodiment of the present application, the Gate of the amplifying switch element SF is connected to the first end of the first storage capacitor C2. The Drain Drain of the amplifying switch element SF is connected to the power signal VDD, and the Source Source of the amplifying switch element SF is electrically connected to the Source Source of the second switch element M6. Wherein the read switching element M7 may be a seventh transistor M7.

In some embodiments of the present application, referring to fig. 7, the photosensitive unit 10 further includes a second switching element M6 connected to the photosensitive element PD,

The control end of the second switching element M6 is used for accessing the read control signal TX, the first end of the second switching element M6 is electrically connected with the photosensitive element PD to receive the initial photosensitive signal, and the second end of the second switching element M6 is connected with the photosensitive signal reading unit 112.

In fig. 7, the second switching element M6 may be a sixth transistor M6, and the second terminal of the sixth transistor M6 is further connected to the control terminal (gate) of the signal amplifying element SF.

In some embodiments of the present application, the photosensitive pixel circuit includes a plurality of photosensitive pixel units, each of the photosensitive pixel units includes at least one of the photosensitive units 10, and the plurality of photosensitive pixel units are connected to the same photosensitive signal reading unit.

In the embodiment of the present application, the photosensitive pixel circuit may include N photosensitive pixel units, where N is an integer greater than 0. Each of the photosensitive pixel units may include 1, 4, 9, 16, etc. photosensitive units 10. The present application is not limited thereto.

In some embodiments of the present application, referring to fig. 7, the gain processing unit 111 includes a mode switching element M5 and a second storage capacitor C;

A control end (gate) of the mode switching element M5 is connected to the gain mode selection circuit 12, the control end of the mode switching element M5 is used for accessing the gain mode selection signal, a first end of the mode switching element M5 is connected to a first end of the second storage capacitor C, and a second end of the mode switching element M5 is connected to a first end of the first storage capacitor C2 in the photosensitive signal reading unit 112;

The second end of the second storage capacitor C is grounded, and the second end of the first storage capacitor C2 is grounded.

The control terminal of the mode switching element M5 may be connected to the first terminal of C1 and the second terminal of M2 as shown in fig. 7.

The control terminal of the mode switching element M5 may be connected to the output terminal of the first transistor M1 as in fig. 8.

In some embodiments of the present application, referring to fig. 7, the photosensitive signal processing circuit 10 further includes a reset unit 113, the reset unit 113 being connected to the gain processing unit 111, the reset unit 113 being configured to reset the photosensitive signal processing circuit 11;

The reset unit 113 includes a reset switch element M4, a control terminal of the reset switch element is configured to be connected to a reset control signal RST, a first terminal of the reset switch element M4 is connected to a power signal, and a second terminal of the reset switch element M4 is connected to a first terminal of the mode switching switch element M5.

In one embodiment, the photosensitive signal processing circuit 11 is reset in a case where the control terminal of the reset switching element T3 is loaded with a first level (high level). In the case where the control terminal of the reset switching element T3 is loaded with the second level (low level), the two mode selection signals outputted from the two selection signal output terminals enable the photosensitive signal processing circuit 11 to select a certain operation mode.

The reset switching element M4 may be a fourth transistor M4.

In some embodiments of the present application, the photosensitive signal processing circuit 11 switches between a high gain processing mode HCG and a low gain processing mode LCG according to the gain mode selection signal output from the gain mode selection circuit 12.

In the embodiment of the present application, the first gain processing mode includes one of a high gain processing mode HCG and a low gain processing mode LCG, and the second gain processing mode includes the other of the high gain processing mode HCG and the low gain processing mode LCG. And each photosensitive pixel circuit specifically selects which gain mode to adopt, and the gain mode is determined according to the current shooting scene requirement. If a part of the photosensitive pixel circuits are required to work in a high-gain processing mode HCG with stronger exposure capability in the current shooting scene, namely, a part of the photosensitive pixel circuits are required to work in the high-gain processing mode HCG with larger gain on the initial photosensitive signal, the gain mode selection circuit corresponding to the photosensitive pixel circuits is controlled to output a signal for selecting the HCG, then the signal for selecting the HCG is output to the photosensitive signal processing circuit, and the photosensitive signal processing circuit enters the HCG according to the signal. If a part of photosensitive pixel circuits are required to work in a low-gain processing mode LCG with weaker exposure capability in the current shooting scene, namely, a part of photosensitive pixel circuits are required to work in a low-gain processing mode LCG with smaller gain on an initial photosensitive signal, a gain mode selection circuit is controlled to output a signal for selecting the LCG, then the signal for selecting the LCG is output to a photosensitive signal processing circuit, and the photosensitive signal processing circuit enters the LCG according to the signal. The adaptive selection control of the gain processing mode of the photosensitive pixel circuit at the pixel level can be realized through the design.

In the embodiment of the present application, M1 to M14 may be MOS transistors, N-type transistors or P-type transistors, and when a certain type of transistor is adopted, the connection relationship among the gate, the source and the drain may be adjusted according to the principle of the transistor and the requirement of the circuit of the present application.

In the embodiment of the present application, the mode switching element M5 may be a fifth transistor M5, fig. 7 may correspond to each of the RGGB pixel arrays, and in fig. 7, the photosensitive unit 10 includes a Photodiode (PD) and a fourth ground GND; in each frame time, the PD is responsible for sensing an optical signal and photoelectrically converting the optical signal to generate a charge e-, and then the generated charge e-is buffered in the first storage capacitor C2 after being turned on by the sixth transistor M6 controlled by the selection control signal TX. In the reading stage, the charge e-in the first storage capacitor C2 is amplified by the amplifying transistor SF and converted into a corresponding voltage, and after the control signal SEL controls the seventh transistor M7 to be turned on, the read pixel signal pix_out is output to the outside of the pixel structure through the output terminal of the photosensitive signal processing circuit. In the embodiment of the present application, M1-M15 may be N-type Metal-Oxide-Semiconductor (NMOS) transistors.

It can be understood that the initial selection signal dcg_sel buffered in the buffer capacitor C1 is directly electrically connected to the gate electrode of the fifth transistor M5, and controls the fifth transistor M5 to be turned on or off. When the mode control signal dcg_sel is "1" (dcg_sel is a digital signal) or high (dcg_sel is an analog signal), the fifth transistor M5 is turned on, the second storage capacitor C is connected to the buffer first storage capacitor C2, and the photosensitive pixel circuit is connected to the first storage capacitor C2 in parallel and operates in LCG mode. If the mode control signal dcg_sel is "0" (dcg_sel is a digital signal) or low (dcg_sel is an analog signal), the fifth transistor M5 is turned off, and the buffer capacitor C and the buffer node disconnect the photosensitive pixel circuit to operate in HCG mode.

In order to understand the technical solution of the embodiment of the present application, the working principle of the pixel structure of fig. 7 will be described in stages in one frame time:

In the reset stage, dcg_ SEL, CTRL, RST is high level "1" (ensuring that M2, M4 and M5 are all on) (first refresh), and the second storage capacitor C and the first storage capacitor C2 are emptied; wherein the end of the reset phase is marked by RST becoming "0", i.e. M4 is turned off.

In the exposure phase, the PD in the photosensitive unit 10 operates, induces an optical signal to generate a charge, and stores the charge in the intrinsic capacitance of the PD. M5 may be in an off state or an on state;

In the reading stage, CTRL is at a high level so as to refresh the actual DCG_SEL into C1 (second refresh), and the DCG_SEL input M5 controls the on or off of M5 so that the pixel structure works in a mode corresponding to the DCG_SEL; when DCG_SEL corresponds to HCG, M5 is turned off, and C is disconnected from C2; TX and SEL are both high, M6 and M7 are on (M6 and M7 are N-type transistors), charges generated for the photosensitive unit 10 are stored in C2, amplified by SF, and output is output through the output end of the photosensitive signal processing circuit 11. When DCG_SEL corresponds to LCG, M5 is conducted, and C is connected with C2; TX and SEL are both high, M6 and M7 are conducted, charges generated by the photosensitive unit 10 are stored in C2 and C, and the charges are amplified by SF and then output through the output end of the photosensitive signal processing circuit 11.

It can be understood that, because of the leakage characteristic of M2 in the embodiment of the present application, the buffering of the buffering capacitor C1 has a time limit. Therefore, it is necessary to refresh the memory after a certain period of time. The refresh frequency is no less than the time required to update all pixels in the pixel array once. Here, if the time in the reset phase or the exposure phase exceeds the preset time, it is necessary to refresh (re-swish the control electrode of M5 into the mode control signal) as needed; meanwhile, in the reading stage, if the M6 and the M7 are turned on in a delayed manner, the refreshing is required as required.

In the embodiment of the present application, referring to fig. 8, compared with fig. 7, the difference is only that the first transistor M1 is provided between the first node and the mode selection signal output terminal. The first node is the connection point between the second end of M2 and the first end of C1.

In the embodiment of the present application, fig. 9 corresponds to the pixel structure of each pixel unit in the 4-in-1 pixel array, and referring to fig. 9, compared with fig. 7, the gain mode selection circuit 12 is the same, and the difference is that the photosensitive pixel unit includes four photosensitive units 10 with the same structure; wherein the first photosensitive unit includes a first photodiode PD1 and a transistor M4a; the second photosensitive unit includes a second photodiode PD2 and a transistor M4b; the third photosensitive unit includes a third photodiode PD3 and a transistor M4c; the fourth photosensitive unit includes a fourth photodiode PD4 and a transistor M4d; the positive electrode of PD1 is connected with GND; the negative electrode of PD1 is connected to the first electrode of M4a; the control electrode of the PD1 is connected with a control signal TX1; the positive electrode of PD2 is connected with GND; the negative electrode of PD2 is connected to the first electrode of M4b; the control electrode of the PD2 is connected with a control signal TX2; the positive electrode of PD3 is connected with GND; the negative electrode of PD3 is connected to the first electrode of M4c; the control electrode of the PD3 is connected with a control signal TX3; the positive electrode of PD4 is connected with GND; the negative electrode of PD4 is connected to the first electrode of M4d; the control electrode of the PD4 is connected with a control signal TX4; the output terminals (drains) of M4a, M4b, M4c, M4d are all connected to the photosensitive signal processing circuit 11.

In the embodiment of the present application, referring to fig. 10, compared with fig. 9, the difference is only that the first transistor M1 is provided between the first node and the mode selection signal output terminal. The first node is the connection point between the second end of M2 and the first end of C1.

In the embodiment of the present application, as shown in fig. 11, the difference is only that the buffer element 121 including the second transistor M2, the buffer capacitor C1, and the first ground GND1 in fig. 7 is replaced with the buffer element 121 including the D signal flip-flop G1, compared with fig. 7.

In the embodiment of the present application, as shown in fig. 12, the difference is only that the buffer element 121 including the second transistor M2, the buffer capacitor C1, and the first ground GND1 in fig. 9 is replaced with the buffer element 121 including the D signal flip-flop G1, compared with fig. 9.

In the embodiment of the present application, referring to fig. 13, compared with fig. 11, the difference is only that the first transistor M1 is provided between the Q output terminal and the mode selection signal output terminal.

In the embodiment of the present application, referring to fig. 14, compared with fig. 12, the difference is only that the first transistor M1 is provided between the Q output terminal and the mode selection signal output terminal.

It can be appreciated that the pixel structure in the embodiment of the present application can effectively independently buffer the mode selection signal, so that each pixel structure can independently operate in the DCG or LCG mode according to the requirement, and realize or/achieve the adaptive DCG-HDR function.

Meanwhile, a mature and widely used DRAM (Dynamic Random Access Memory, dynamic random storage) structure is adopted as a DCG selection signal buffer module, so that the increase of circuit elements in pixels can be effectively reduced, the compact structure of the 4T-APS pixel is kept, and the implementation of small pixels is benefited.

Furthermore, the DCG select signal buffering step can be flexibly skipped for the case where there is no adaptive DCG-HDR requirement. And this embodiment may be applicable to rolling shutter or global shutter CMOS image sensors.

It can be understood that the pixel structure provided by the embodiment of the application is not only suitable for the pixel array of 4 in 1, but also can be extended to the pixel arrays of 9 in 1 and 16 in 1, and the structures are similar.

Likewise, the pixel structure provided by the embodiment of the application can be applied to a pixel array of RGBW (Red, green, blue, white) with four primary colors, and can be applied to pixel arrays of other primary colors.

On the basis of the above embodiments, an embodiment of the present application provides an image sensor, which includes the above pixel structure.

On the basis of the embodiment, the embodiment of the application provides electronic equipment, which comprises the image sensor.

Furthermore, an embodiment of the present application provides a driving method of a pixel structure, which is applied to driving the pixel structure, and the method includes:

S1501: a first period of time in which a first level signal or a first variation signal is input to the selection control signal input terminal; inputting a first level signal to a selection signal input terminal; the first change signal represents a signal changed from the second level signal to the first level signal; the level of the first level signal is greater than that of the second level signal;

s1502: a second period of time for inputting a second level signal to the selection control signal input terminal; inputting a first level signal or a second level signal to the selection signal input terminal;

S1503: a third period of time for inputting the first level signal or the second variation signal to the selection control signal input terminal; the second change signal represents a signal changed from the first level signal to the second level signal; inputting a target level signal to the selection control signal input terminal; the target level signal corresponds to a target operating mode of the pixel structure.

The embodiment of the application provides a driving method of a pixel structure, by which a photosensitive signal processing circuit in the pixel structure can work in a corresponding mode. Meanwhile, under the condition that the gain mode selection signal of each pixel structure corresponds to the use scene of the image sensor comprising the pixel unit, the gain mode selection signal buffered in the buffer unit of the buffer circuit also corresponds to the use scene, and the gain mode selection signal output to the photosensitive signal processing circuit also corresponds to the use scene, so that the photosensitive signal processing circuit can work in a mode corresponding to the use scene, the dynamic range modulation of the pixel level is realized, the overexposure or underexposure problem is avoided, the power consumption can be reduced, the circuit structure is simple, the gain processing mode of the initial photosensitive signal can be adaptively adjusted, two images are not acquired for processing, and the energy consumption is reduced. The method can also effectively reduce the problem of partial overexposure or partial underexposure of partial pixels in some scenes with complicated brightness and darkness changes, and can simultaneously compensate the overexposed partial pixels or the underexposed partial pixels.

It should be noted that, in the embodiment of the present application, the electronic device includes, but is not limited to, a mobile phone, a tablet computer, a notebook computer, a palm computer, a vehicle-mounted terminal, a wearable device, a pedometer, and the like.

It should be noted that, in the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described as different from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.

While alternative embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following appended claims be interpreted as including alternative embodiments and all such alterations and modifications as fall within the scope of the embodiments of the application.

Finally, it is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity from another entity without necessarily requiring or implying any actual such relationship or order between such entities. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such article or terminal. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude that an additional identical element is present in an article or terminal device comprising the element.

While the foregoing has been described in some detail by way of illustration of the principles and embodiments of the application, and while in accordance with the principles and implementations of the application, those skilled in the art will readily recognize that the application is not limited thereto.

Claims

1. A photosensitive pixel circuit is characterized by comprising a photosensitive unit, a photosensitive signal processing circuit and a gain mode selection circuit;

the photosensitive unit comprises a photosensitive element for generating an initial photosensitive signal, and is connected with the photosensitive signal processing circuit;

the photosensitive signal processing circuit determines a gain processing mode of the initial photosensitive signal according to the gain mode selection signal;

The gain mode selection circuit is provided with a selection signal input end, a selection signal output end and a selection control signal input end, and the selection signal output end is electrically connected with the gain processing unit; the selection signal input end is used for accessing an initial selection signal, the selection control signal input end is used for accessing a selection control signal, and the selection signal output end is used for outputting the gain mode selection signal according to the initial selection signal under the control of the selection control signal;

The gain mode selection circuit further comprises a buffer element and a selection switch element, wherein the buffer element is electrically connected with the selection signal input end, and the buffer element is electrically connected with the selection signal output end;

the first end of the selection switch element is connected with the selection signal output end to receive the gain mode selection signal, the second end of the selection switch element is connected with the gain processing unit, and the control end of the selection switch element is connected with an enabling control signal to output the gain mode selection signal to the gain processing unit when the gain processing mode of the initial photosensitive signal needs to be switched.

2. The photosensitive pixel circuit of claim 1, wherein the photosensitive signal processing circuit further comprises a reset unit, the reset unit being coupled to the gain processing unit, the reset unit being configured to reset the photosensitive signal processing circuit.

3. The photosensitive pixel circuit of claim 1, wherein the buffer element comprises a first switching element and a buffer capacitor;

the control end of the first switching element is the selection control signal input end, the first end of the first switching element is the selection signal input end, the second end of the first switching element is electrically connected with the first end of the buffer capacitor, the first end of the buffer capacitor is electrically connected with the selection signal output end, and the second end of the buffer capacitor is grounded.

4. The photosensitive pixel circuit of claim 1, wherein the gain mode selection circuit comprises a flip-flop having the select signal input, the select signal output, and the select control signal input.

5. The photosensitive pixel circuit of claim 4, wherein the flip-flop is a digital signal flip-flop, the flip-flop further having a set signal terminal and a reset signal terminal; under the condition that the setting signal end loads a first level, the gain mode selection signal output by the selection signal output end enables the photosensitive signal processing circuit to work in a first gain processing mode; and under the condition that the reset signal end loads the second level, the gain mode selection signal output by the selection signal output end enables the photosensitive signal processing circuit to work in a second gain processing mode.

6. The photosensitive pixel circuit of claim 1, wherein the gain mode selection circuit comprises a digital signal buffer having the selection signal input, the selection signal output, and the selection control signal input, and a digital signal buffer unit for storing the selection signal.

7. The photosensitive pixel circuit of claim 1, wherein the buffer element comprises a first switching element and a digital signal buffer unit;

the digital signal buffer unit comprises a first switching tube, a second switching tube, a third switching tube and a fourth switching tube;

The control end of the first switching element is the selection control signal input end, the first end of the first switching element is the selection signal input end, the second end of the first switching element is electrically connected with the first end of the first switching tube, and the second end of the first switching element is also electrically connected with the second end of the second switching tube;

The first switching tube is of an N type, the control end of the first switching tube is electrically connected with the control end of the second switching tube, and the second end of the first switching tube is grounded;

The second switching tube is of a P type, the control end of the second switching tube is electrically connected with the first end of the third switching tube, the first end of the second switching tube is connected with a power supply signal, and the second end of the second switching tube is electrically connected with the control end of the third switching tube;

the third switching tube is of an N type, a first end of the third switching tube is electrically connected with a second end of the fourth switching tube, and a second end of the third switching tube is grounded;

The fourth switching tube is of a P type, the control end of the fourth switching tube is electrically connected with the control end of the third switching tube, the first end of the fourth switching tube is connected with the power signal, and the second end of the fourth switching tube is electrically connected with the output end of the selection control signal.

8. The photosensitive pixel circuit according to any one of claims 3 to 7, wherein the gain mode selection circuit further comprises a selection switch element, a first terminal of the selection switch element is connected to the selection signal output terminal to receive the gain mode selection signal, a second terminal of the selection switch element is connected to the gain processing unit, and a control terminal of the selection switch element is used for accessing an enable control signal to output the gain mode selection signal to the gain processing unit when the gain processing mode of the initial photosensitive signal needs to be switched.

9. The photosensitive pixel circuit according to claim 1, wherein the photosensitive signal reading unit includes a first storage capacitor, a signal amplifying element, and a read switching element;

The first end of the first storage capacitor is electrically connected with the photosensitive unit to receive the initial photosensitive signal, the first end of the first storage capacitor is also connected with the gain processing unit, and the second end of the first storage capacitor is grounded;

The input end of the signal amplifying element is connected with the first end of the first storage capacitor, and the output end of the signal amplifying unit is connected with the first end of the reading switch element for outputting an amplified photosensitive signal;

The control end of the reading switch element is used for being connected with an output control signal, and the second end of the reading switch element is a photosensitive signal output end of the photosensitive pixel circuit.

10. The photosensitive pixel circuit of claim 9, wherein the signal amplifying element is an amplifying switch element, a control terminal of the amplifying switch element is connected to the first terminal of the first storage capacitor, the first terminal of the amplifying switch element is connected to a power signal, and a second terminal of the amplifying switch element is electrically connected to the first terminal of the reading switch element.

11. The photosensitive pixel circuit of any of claims 1, 9 or 10, comprising a plurality of photosensitive pixel cells, each of the photosensitive pixel cells comprising at least one of the photosensitive cells, the plurality of photosensitive pixel cells being connected to the same photosensitive signal reading unit.

12. The photosensitive pixel circuit of claim 5, wherein the gain processing unit comprises a mode switching element and a second storage capacitor;

the control end of the mode switching switch element is connected with the gain mode selection circuit, the control end of the mode switching switch element is used for accessing the gain mode selection signal, the first end of the mode switching switch element is connected with the first end of the second storage capacitor, and the second end of the mode switching switch element is connected with the first end of the first storage capacitor in the photosensitive signal reading unit;

The second end of the second storage capacitor is grounded, and the second end of the first storage capacitor is grounded.

13. The photosensitive pixel circuit of claim 12, wherein the photosensitive signal processing circuit further comprises a reset unit, the reset unit being connected to the gain processing unit, the reset unit being configured to reset the photosensitive signal processing circuit;

The reset unit comprises a reset switch element, wherein the control end of the reset switch element is used for being connected with a reset control signal, the first end of the reset switch element is connected with a power supply signal, and the second end of the reset switch element is connected with the first end of the mode switching switch element;

The gain mode selection signal output by the selection signal output end enables the photosensitive signal processing circuit to work in a first gain processing mode; and under the condition that the reset signal end loads the second level, the gain mode selection signal output by the selection signal output end enables the photosensitive signal processing circuit to work in a second gain processing mode.

14. The photosensitive pixel circuit of claim 1, wherein the photosensitive signal processing circuit switches between a high gain processing mode and a low gain processing mode in accordance with the gain mode selection signal output by the gain mode selection circuit.

15. An image sensor comprising a photosensitive pixel circuit as claimed in any one of claims 1 to 14.

16. An electronic device comprising the image sensor of claim 15.