CN216057242U - Pixel circuit and CMOS image sensor - Google Patents
Pixel circuit and CMOS image sensor Download PDFInfo
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- CN216057242U CN216057242U CN202122717370.5U CN202122717370U CN216057242U CN 216057242 U CN216057242 U CN 216057242U CN 202122717370 U CN202122717370 U CN 202122717370U CN 216057242 U CN216057242 U CN 216057242U
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Abstract
The present invention provides a pixel circuit, including: the device comprises a reset module, a gain control module, a photosensitive control module and a reading module; the reading module comprises a high-gain reading unit and a low-gain reading unit which are connected to the floating diffusion point, the high-gain reading unit is used for reading and outputting a voltage signal of the floating diffusion point in a high-gain transmission mode, and the low-gain reading unit is used for reading and outputting a voltage signal of the floating diffusion point in a low-gain transmission mode; the high-gain reading unit comprises a first capacitor, the low-gain reading unit comprises a second capacitor, the first capacitor is used for obtaining the voltage difference between an image signal and a reset signal in a high-gain transmission mode, and the second capacitor is used for obtaining the voltage difference between the image signal and the reset signal in a low-gain transmission mode. The pixel circuit provided by the utility model solves the problem of low dynamic range of the existing CMOS image sensor.
Description
Technical Field
The present invention relates to the field of CMOS image sensors, and in particular, to a pixel circuit and a CMOS image sensor.
Background
The global exposure technology (global shutter) is an imaging technology which needs to be applied in high-speed photography, all signals are exposed at the same time, and an image without distortion is generated; the main realization principle is that a storage capacitor is added in each pixel circuit, all the pixel circuits are exposed at the same time, and then photoelectric conversion signals are stored in the storage capacitor to wait for the reading of the subsequent circuits.
In some environments with large light difference, the dynamic range is a key index influencing the imaging effect; the method determines the light intensity distribution range from the darkest shadow part to the brightest highlight part which can be accepted by the CMOS image sensor, namely the details, the levels and the characteristics of the shot image. Therefore, how to increase the dynamic range of a CMOS image sensor is a problem that those skilled in the art are in the pursuit of.
SUMMERY OF THE UTILITY MODEL
In view of the above-mentioned shortcomings of the prior art, the present invention provides a pixel circuit and a CMOS image sensor, which are used to solve the problem of low dynamic range of the conventional CMOS image sensor.
To achieve the above and other related objects, the present invention provides a pixel circuit, including: a reset module, a gain control module, a photosensitive control module and a reading module, wherein,
the reset module comprises a reset transistor, a grid end of the reset transistor is connected with a reset control signal, a first connecting end is connected with power voltage, and a second connecting end is connected to the floating diffusion point;
the gain control module is connected between the second connecting end of the reset transistor and the floating diffusion point, is controlled by a gain control signal, and is used for adjusting the equivalent charge storage capacity of the floating diffusion point according to the gain control signal so as to enable the pixel circuit to work in different gain transmission modes;
the photosensitive control module is connected between the floating diffusion point and a first reference voltage, is controlled by a transmission control signal, and is used for generating exposure charges according to a photoelectric effect and transferring and outputting the exposure charges according to the transmission control signal;
the reading module comprises a high-gain reading unit and a low-gain reading unit which are connected to the floating diffusion point, wherein the high-gain reading unit is used for reading and outputting a voltage signal of the floating diffusion point in a high-gain transmission mode; the low-gain reading unit is used for reading and outputting a voltage signal of the floating diffusion point in a low-gain transmission mode; the high-gain reading unit comprises a first capacitor, the low-gain reading unit comprises a second capacitor, the first capacitor is used for obtaining the voltage difference between an image signal and a reset signal in a high-gain transmission mode, and the second capacitor is used for obtaining the voltage difference between the image signal and the reset signal in a low-gain transmission mode.
Optionally, the high-gain transmission modes include a first high-gain transmission mode in which the left plate of the first capacitor stores a high-gain reset voltage signal Vrst hcg and the right plate stores a first power supply voltage signal Vdd, and a second high-gain transmission mode in which the left plate of the first capacitor stores a high-gain image voltage signal Vsig hcg and the right plate stores a high-gain output voltage signal Vsig hcg + (Vdd-Vrst hcg); and/or the low-gain transmission mode comprises a first low-gain transmission mode and a second low-gain transmission mode, in the first low-gain transmission mode, the left plate of the second capacitor stores a low-gain reset voltage signal Vrst lcg, the right plate stores a first power supply voltage signal Vdd, in the second low-gain transmission mode, the left plate of the second capacitor stores a low-gain image voltage signal Vsig lcg, and the right plate stores an output low-gain voltage signal Vsig lcg + (Vdd-Vrst lcg).
Optionally, the high gain reading unit further comprises at least: the first high-gain source following transistor, the first high-gain storage control transistor, the second high-gain source following transistor and the first row selection transistor; the grid end of the first high-gain source following transistor is connected to the floating diffusion point, the first connecting end is connected to a first variable voltage, and the second connecting end is connected with the first connecting end of the first high-gain storage control transistor; the grid end of the first high-gain storage control transistor is connected with a first high-gain storage control signal, and the second connecting end of the first high-gain storage control transistor is connected with the left pole plate of the first capacitor; the right pole plate of the first capacitor is connected with the second connecting end of the second high-gain storage control transistor and the gate end of the second high-gain source follower transistor; the grid end of the second high-gain storage control transistor is connected with a second high-gain storage control signal, and the first connecting end is connected with a first power supply voltage; the first connection end of the second high-gain source following transistor is connected with a second power supply voltage, and the second connection end of the second high-gain source following transistor is connected with the first connection end of the first row of selection transistors; the grid end of the first row selection transistor is connected with a high-gain row selection signal, and the second connecting end is used as the output end of the high-gain reading unit;
the low-gain reading unit further includes at least: the first low-gain source following transistor, the first low-gain storage control transistor, the second low-gain source following transistor and the second row selecting transistor; the grid end of the first low-gain source following transistor is connected to the floating diffusion point, the first connecting end is connected to a second variable voltage, and the second connecting end is connected with the first connecting end of the first low-gain storage control transistor; the grid end of the first low-gain storage control transistor is connected with a first low-gain storage control signal, and the second connecting end of the first low-gain storage control transistor is connected with the left pole plate of the second capacitor; the right pole plate of the second capacitor is connected with the second connecting end of the second low-gain storage control transistor and the gate end of the second low-gain source follower transistor; the grid end of the second low-gain storage control transistor is connected with a second low-gain storage control signal, and the first connecting end is connected with a third power supply voltage; the first connecting end of the second low-gain source follower transistor is connected with a fourth power supply voltage, and the second connecting end of the second low-gain source follower transistor is connected with the first connecting end of the second row selection transistor; and the grid end of the second row selection transistor is connected with a low-gain row selection signal, and the second connecting end is used as the output end of the low-gain reading unit.
Optionally, the first high-gain source follower transistor and the first low-gain source follower transistor are the same source follower transistor, a gate of the shared source follower transistor is connected to the floating diffusion point, a first connection end is connected to a variable voltage, and a second connection end is respectively connected to the first connection end of the first high-gain storage control transistor and the first connection end of the first low-gain storage control transistor.
Optionally, the high-gain reading unit includes a third capacitor, and the third capacitor is connected between the second connection terminal of the first high-gain storage control transistor and a second reference voltage; and/or the low-gain reading unit comprises a fourth capacitor, and the fourth capacitor is connected between the second connecting end of the first low-gain storage control transistor and a third reference voltage.
Optionally, the gain control module comprises: the gate end of the gain control transistor is connected with the gain control signal, the first connecting end is connected with the second connecting end of the reset transistor and is connected with a fourth reference voltage through the gain adjusting capacitor, and the second connecting end is connected with the floating diffusion point.
Optionally, the gain adjustment capacitor is a parasitic capacitor of the reset transistor and the gain control transistor, which is connected to the ground; or, the gain adjusting capacitor is a device capacitor.
Optionally, the photosensitive control module comprises: the output end of the photoelectric conversion element is connected with the first connecting end of the transmission transistor, and the other end of the photoelectric conversion element is connected with the first reference voltage; and the grid end of the transmission transistor is connected with the transmission control signal, and the second connecting end is connected to the floating diffusion point.
Optionally, the high-gain reading unit and the low-gain reading unit correspond to the same or different column lines to respectively realize serial output or parallel output of signals.
The present invention also provides a CMOS image sensor including: a pixel circuit as claimed in any one of the above.
Optionally, the image sensor comprises a first semiconductor substrate and a second semiconductor substrate arranged in a stacked manner, the photosensitive control module is located in the first semiconductor substrate, and the reading module is located in the second semiconductor substrate; or, the image sensor comprises a first semiconductor substrate, a second semiconductor substrate and a third semiconductor substrate which are stacked, the photosensitive control module is located in the first semiconductor substrate, the reading module is located in the second semiconductor substrate, and the image sensor further comprises a logic circuit which is located in the third semiconductor substrate; or, the image sensor includes a first semiconductor substrate and a second semiconductor substrate stacked, the light sensing control module and the reading module are located in the first semiconductor substrate, and the image sensor further includes a logic circuit located in the second semiconductor substrate.
As described above, according to the pixel circuit and the CMOS image sensor of the present invention, the dynamic range of the CMOS image sensor is effectively increased by the dual conversion gain technology through the design of the gain control module and the reading module; the high-intensity illumination area is provided with a large capacitor, so that stored charges are improved, the gain is reduced to improve the dynamic range, the low-intensity illumination area is provided with a small capacitor, the gain is improved, and the high sensitivity is realized.
Drawings
Fig. 1 is a schematic diagram of a parallel output pixel circuit according to a first embodiment of the utility model.
Fig. 2 is a schematic diagram of the pixel circuit shown in fig. 1 when the first source follower transistor is shared.
Fig. 3 is a schematic diagram of a serial output pixel circuit according to an embodiment of the utility model.
Fig. 4 is a timing diagram of signals in the pixel circuit shown in fig. 2.
Description of the element reference numerals
100 reset module
200 gain control module
300 photosensitive control module
400 read module
401 high gain read cell
402 low gain read cell
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The utility model is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 4. It should be noted that the drawings provided in the present embodiment are only schematic and illustrate the basic idea of the present invention, and although the drawings only show the components related to the present invention and are not drawn according to the number, shape and size of the components in actual implementation, the form, quantity and proportion of the components in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
Example one
As shown in fig. 1, fig. 1 is a schematic diagram of a parallel output pixel circuit according to a first embodiment of the utility model. The present embodiment provides a pixel circuit, including: a reset module 100, a gain control module 200, a photosensitive control module 300 and a reading module 400.
As shown in fig. 1, the reset module 100 includes a reset transistor M1, a gate terminal of the reset transistor M1 is connected to a reset control signal rst, a first connection terminal is connected to a power voltage VDD, and a second connection terminal is connected to the floating diffusion point FD for resetting a voltage of the floating diffusion point FD according to the reset control signal rst, thereby completing a reset operation of the photoelectric conversion element (e.g., the photodiode PD) in the light sensing control module 300. Optionally, the reset transistor M1 is an NMOS transistor, and the first connection terminal thereof is a drain terminal and the second connection terminal thereof is a source terminal.
As shown in fig. 1, the gain control module 200 is connected between the second connection terminal of the reset transistor M1 and the floating diffusion point FD, and is controlled by the gain control signal dcg to adjust the equivalent charge storage capacity of the floating diffusion point FD according to the gain control signal dcg, so that the pixel circuit operates in different gain transfer modes, that is, the CMOS image sensor formed by the pixel circuit operates in different gain transfer modes.
Specifically, as shown in fig. 1, the gain control module 200 includes: gain control transistor M2 and gain control capacitor Cdcg, wherein the gate of gain control transistor M2 is connected to gain control signal dcg, the first connection terminal is connected to the second connection terminal of reset transistor M1 and to the fourth reference voltage through gain control capacitor Cdcg, and the second connection terminal is connected to floating diffusion point FD. Optionally, the gain control transistor M2 is an NMOS transistor, and a first connection end thereof is a drain end, and a second connection end thereof is a source end; the gain adjusting capacitor Cdcg may be a parasitic capacitor of the connection point of the reset transistor M1 and the gain control transistor M2 to ground, or may be a device capacitor (i.e., an external capacitor); optionally, the fourth reference voltage is a ground voltage.
In this embodiment, when the gain control signal dcg is at a high level, the gain control transistor M2 is turned on, and the equivalent charge storage capacity of the floating diffusion point FD is increased by the gain adjustment capacitor Cdcg, so that the final charge storage capacity is the sum of the charge storage capacity of the floating diffusion point FD itself and the charge storage capacity of the gain adjustment capacitor Cdcg, and at this time, the CMOS image sensor constituted by the pixel circuit operates in a low gain transfer mode (LCG); on the contrary, when the gain control signal dcg is at a low level, the gain control transistor M2 is turned off, so that the charge storage capacity of the floating diffusion FD itself is the final charge storage capacity, and at this time, the CMOS image sensor including the pixel circuit operates in a high gain transfer mode (HCG).
As shown in fig. 1, the sensing control module 300 is connected between the floating diffusion FD and a first reference voltage, and is controlled by a transfer control signal tx for generating exposure charges according to a photoelectric effect and transferring and outputting the exposure charges according to the transfer control signal tx.
Specifically, as shown in fig. 1, the photosensitive control module 300 includes: the photoelectric conversion element and the transmission transistor M3, wherein the output end of the photoelectric conversion element is connected with the first connection end of the transmission transistor M3, and the other end of the photoelectric conversion element is connected with a first reference voltage; the gate terminal of the transfer transistor M3 is connected to the transfer control signal tx, and the second connection terminal is connected to the floating diffusion point FD. Optionally, the photoelectric conversion element is a photodiode PD, an output end of the photoelectric conversion element is a cathode of the photodiode PD, and the other end of the photoelectric conversion element is an anode of the photodiode PD; the transmission transistor M3 is an NMOS transistor, a first connection end of which is a drain end, and a second connection end of which is a source end; in the embodiment of the present invention, optionally, the first reference voltage is a ground voltage.
In the present embodiment, the photodiode PD generates exposure charge in response to incident light according to the photoelectric effect, and the transfer transistor M3 is turned on when the transfer control signal tx is at a high level, and transfers and outputs the exposure charge generated by the photodiode PD.
As shown in fig. 1, the reading module 400 includes a high-gain reading unit 401 and a low-gain reading unit 402, both connected to the floating diffusion point FD; the high-gain reading unit 401 is configured to read and output a voltage signal of the floating diffusion point FD in the high-gain transmission mode; the low-gain reading unit 402 is configured to read and output a voltage signal of the floating diffusion point FD in the low-gain transmission mode; the high-gain reading unit 401 includes a first capacitor C1, the low-gain reading unit 402 includes a second capacitor C2, the first capacitor C1 is used for obtaining a voltage difference between the image signal and the reset signal in the high-gain transmission mode, and the second capacitor C2 is used for obtaining a voltage difference between the image signal and the reset signal in the low-gain transmission mode.
Specifically, the high-gain transmission mode includes a first high-gain transmission mode in which the left plate of the first capacitor C1 stores a high-gain reset voltage signal Vrst hcg and the right plate stores a first power supply voltage signal Vdd, and a second high-gain transmission mode in which the left plate of the first capacitor stores a high-gain image voltage signal Vsig hcg and the right plate stores a high-gain output voltage signal Vsig hcg + (Vdd-Vrst hcg), so as to obtain a voltage difference between the image signal and the reset signal in the high-gain transmission mode by using the first capacitor C1; and/or the low-gain transmission mode comprises a first low-gain transmission mode and a second low-gain transmission mode, in the first low-gain transmission mode, the left plate of the second capacitor stores a low-gain reset voltage signal Vrst lcg, the right plate stores a first power supply voltage signal Vdd, in the second low-gain transmission mode, the left plate of the second capacitor stores a low-gain image voltage signal Vsig lcg, and the right plate stores and outputs a low-gain voltage signal Vsig lcg + (Vdd-Vrst lcg), so that the voltage difference between the image signal and the reset signal in the low-gain transmission mode is obtained by using the second capacitor C2. Alternatively, the first power supply voltage Vdd is a positive potential power supply voltage Vdd.
Specifically, as shown in fig. 1, the high gain reading unit 401 at least further includes: a first high-gain source follower transistor M4, a first high-gain memory control transistor M5, a second high-gain memory control transistor M6, a second high-gain source follower transistor M7, and a first row select transistor M8; the gate end of the first high-gain source follower transistor M4 is connected to the floating diffusion point FD, the first connection end is connected to the first variable voltage Vrsf1, and the second connection end is connected to the first connection end of the first high-gain storage control transistor M5; the gate end of the first high-gain storage control transistor M5 is connected with a first high-gain storage control signal SHCG, and the second connecting end is connected with the left plate of the first capacitor C1; the right plate of the first capacitor C1 is connected with the second connection end of the second high-gain storage control transistor M6 and the gate end of the second high-gain source follower transistor M7; the gate terminal of the second high-gain storage control transistor M6 is connected to the second high-gain storage control signal rstH, and the first connection terminal is connected to the first power voltage Vdd 1; the first connection end of the second high-gain source follower transistor M7 is connected to a second power supply voltage Vdd2, and the second connection end is connected to the first connection end of the first row selection transistor M8; the gate terminal of the first row select transistor M8 is connected to the high-gain row select signal rsH, and the second connection terminal is used as the output terminal of the high-gain read unit 401. Optionally, the first high-gain source follower transistor M4, the first high-gain storage control transistor M5, the second high-gain storage control transistor M6, the second high-gain source follower transistor M7, and the first row select transistor M8 are all NMOS transistors, the first connection terminal is a drain terminal, and the second connection terminal is a source terminal.
The low-gain reading unit 402 further includes at least: a first low-gain source follower transistor M9, a first low-gain memory control transistor M10, a second low-gain memory control transistor M11, a second low-gain source follower transistor M12, and a second row select transistor M13; the gate terminal of the first low-gain source follower transistor M9 is connected to the floating diffusion point FD, the first connection terminal is connected to the second variable voltage Vrsf2, and the second connection terminal is connected to the first connection terminal of the first low-gain storage control transistor M10; the gate end of the first low-gain storage control transistor M10 is connected to a first low-gain storage control signal SLCH, and the second connecting end is connected to the left plate of the second capacitor C2; the right plate of the second capacitor C2 is connected to the second connection terminal of the second low-gain storage control transistor M11 and the gate terminal of the second low-gain source follower transistor M12; the gate terminal of the second low-gain storage control transistor M11 is connected to the second low-gain storage control signal rstL, and the first connection terminal is connected to the third power voltage Vdd 3; the first connection end of the second low-gain source follower transistor M12 is connected to a fourth power supply voltage Vdd4, and the second connection end is connected to the first connection end of the second row selection transistor M13; the gate of the second row select transistor M13 is coupled to the low gain row select signal rsL, and the second connection is used as the output of the low gain read unit 402.
Optionally, the first high-gain source follower transistor M4, the first high-gain storage control transistor M5, the second high-gain storage control transistor M6, the second high-gain source follower transistor M7, the first row selection transistor M8, the first low-gain source follower transistor M9, the first low-gain storage control transistor M10, the second low-gain storage control transistor M11, the second low-gain source follower transistor M12, and the second row selection transistor M13 are NMOS transistors, the first connection terminal is a drain terminal, and the second connection terminal is a source terminal; optionally, the first variable voltage Vrsf1 and the second variable voltage Vrsf2 are the same variable voltage Vrsf, that is, the first high-gain storage control transistor M5 and the first low-gain source follower transistor M9 are the same source follower transistor, and the drain of the source follower transistor is connected to the variable voltage Vrsf; optionally, the first variable voltage Vrsf1 and the second variable voltage Vrsf2 are different variable voltages, that is, the first high-gain storage control transistor M5 and the first low-gain source follower transistor M9 are different source follower transistors, and drains of the first high-gain storage control transistor M5 and the first low-gain source follower transistor M9 are respectively connected to the first variable voltage Vrsf1 and the second variable voltage Vrsf 2; the first power supply voltage Vdd1, the second power supply voltage Vdd2, the third power supply voltage Vdd3, and the fourth power supply voltage Vdd4 are all positive power supply voltages Vdd.
In this embodiment, for the high gain reading unit 401: in the first high-gain transmission mode, the variable voltage Vrsf is at a high level, the first high-gain source follower transistor M4, the first high-gain storage control transistor M5 and the second high-gain storage control transistor M6 are turned on, so that the left plate of the first capacitor C1 stores the high-gain reset voltage signal Vrst hcg, and the right plate stores the power supply voltage signal VDD; in the second high-gain transmission mode, the variable voltage Vrsf is at a high level, the first high-gain source follower transistor M4 and the first high-gain storage control transistor M5 are turned on, the second high-gain storage control transistor M6 is turned off, so that the left plate of the first capacitor C1 stores the high-gain image voltage signal Vsig hcg, and the right plate of the first capacitor C1 stores the high-gain output voltage signal Vsig hcg + (VDD-Vrst hcg) in order to maintain the voltage difference between the left and right plates of the first capacitor C1. For low gain read unit 402: in the first low-gain transmission mode, the variable voltage Vrsf is at a high level, the first low-gain source follower transistor M9, the first low-gain storage control transistor M10 and the second low-gain storage control transistor M11 are turned on, so that the left plate of the second capacitor C2 stores a low-gain reset voltage signal Vrst lcg, and the right plate stores a power supply voltage signal VDD; in the second low-gain transmission mode, the variable voltage Vrsf is at a high level, the first low-gain source follower transistor M9 and the first low-gain storage control transistor M10 are turned on, the second low-gain storage control transistor M11 is turned off, so that the left plate of the second capacitor C2 stores the low-gain image voltage signal Vsig lcg, and the right plate of the second capacitor C2 stores and outputs the low-gain voltage signal Vsig lcg + (VDD-Vrst lcg) in order to maintain the voltage difference between the left and right plates of the second capacitor C2.
Further, as shown in fig. 1, the high-gain reading unit 401 includes a third capacitor C3, the third capacitor C3 is connected between the second connection terminal of the first high-gain storage control transistor M5 and the second reference voltage, and is used for absorbing the charges at the moment when the first high-gain storage control transistor M5 is turned off; and/or, the low-gain reading unit 402 includes a fourth capacitor C4, the fourth capacitor C4 is connected between the second connection terminal of the first low-gain storage control transistor M10 and the third reference voltage, and is used for absorbing the charges at the moment when the first low-gain storage control transistor M10 is turned off. It should be noted that, in the reading module 400 of the present embodiment, only one of the third capacitor C3 and the fourth capacitor C4 may be included, or both the third capacitor C3 and the fourth capacitor C4 may be included. Optionally, the read module 400 includes a third capacitor C3 and a fourth capacitor C4, and both the second reference voltage and the third reference voltage are ground voltages.
To simplify the circuit, as shown in fig. 2, fig. 2 is a schematic diagram of the pixel circuit shown in fig. 1 when the first source follower transistor is shared. The first high-gain source follower transistor M4 and the first low-gain source follower transistor M9 are the same source follower transistor, the gate of the common source follower transistor is connected to the floating diffusion point FD, the first connection end is connected to the variable voltage Vrsf, and the second connection end is respectively connected to the first connection end of the first high-gain storage control transistor M5 and the first connection end of the first low-gain storage control transistor M10. Specifically, the high-gain reading unit 401 and the low-gain reading unit 402 correspond to the same or different column lines to respectively realize serial output or parallel output of signals; for example, the high-gain reading unit 401 and the low-gain reading unit 402 correspond to different column lines to realize parallel output of signals (as shown in fig. 1 and 2); the high-gain reading unit 401 and the low-gain reading unit 402 correspond to the same column line to realize serial output of signals (as shown in fig. 3, fig. 3 is a schematic diagram of a serial output pixel circuit according to an embodiment of the present invention). In practical applications, the parallel output and the serial output can be selected according to specific requirements, which has no influence on the embodiment, and only the on-timings of the high-gain row selection signal rsH and the low-gain row selection signal rsL need to be adjusted.
Referring to fig. 4 in conjunction with fig. 2, fig. 4 is a timing diagram of signals in the pixel circuit shown in fig. 2, to explain the operation of the pixel circuit of this embodiment in detail.
Before time t0, a global reset phase (global reset); in this stage, the transfer transistor M3 is turned on while the reset transistor M1 and the gain control transistor M2 are in a turned-on state, the voltage of the floating diffusion point FD is reset by the reset transistor M1, and the reset operation of the photodiode PD is completed; after the reset operation is completed, the transfer transistor M3 is turned off and global exposure starts.
time t1 to time t2, a reset signal precharge (pre-chg rst) phase; at this stage, the reset transistor M1, the gain control transistor M2, the second high-gain memory control transistor M6, and the second low-gain memory control transistor M11 are all in a conductive state, the variable voltage Vrsf changes from a high potential to a low potential, and at the same time, the first high-gain memory control transistor M5 and the first low-gain memory control transistor M10 are turned on, the left plate of the first capacitor C1 and the left plate of the second capacitor C2 are set to a low potential, and the right plate of the first capacitor C1 and the right plate of the second capacitor C2 are set to VDD. After the setting is completed, the first high-gain memory control transistor M5 and the first low-gain memory control transistor M10 are turned off first, and then the variable voltage Vrsf is set to a high level.
From time t2 to time t3, which is the reset voltage sampling phase (global sample LCG rst) of the global LCG; in this stage, the reset transistor M1 is turned off first, that is, the reset is finished; then the first low-gain storage control transistor M10 is turned on, and the low-gain reset voltage signal voltage Vrst _ lcg is stored on the left plate of the second capacitor C2 through the first source follower transistor M4, at this time, the voltage difference of the capacitor plate of the second capacitor C2 is (VDD-Vrst _ lcg); after the voltage holding is completed, the first low-gain storage control transistor M10 returns to the off state.
the stages t3 to t4 are reset voltage sampling stages (global sample HCG rst) of the global HCG; in this stage, the second low-gain memory control transistor M11 is turned off, the gain control transistor M2 is turned off, the first high-gain memory control transistor M5 is turned on, and the high-gain reset voltage signal Vrst _ hcg is stored on the left plate of the first capacitor C1 through the first source follower transistor M4, at this time, the voltage difference of the capacitor plate of the first capacitor C1 is (VDD-Vrst _ hcg); after the voltage holding is completed, the first high-gain memory control transistor M5 returns to the off state.
A period t4 to t5, which is a pixel voltage precharge period (pre-chg sig); in this phase, the variable voltage Vrsf changes from high to low, and at the same time, the first high-gain memory control transistor M5 and the first low-gain memory control transistor M10 turn on, setting the left plate of the first capacitor C1 and the left plate of the second capacitor C2 to low.
A stage t5 to t6, namely an HCG image voltage sampling stage (global sample HCG sig); in this phase, the transfer transistor M3 is turned on, the photodiode PD transfers the exposure charge to the floating diffusion point FD, the voltage at this point is changed, and then the first high-gain storage control transistor M5 is turned on, the source terminal of the first source follower transistor M4 is connected to the left plate of the first capacitor C1, and the high-gain image voltage signal Vsig — hcg is sampled onto the left plate of the first capacitor C1; the second high-gain storage control transistor M6 is in an off state and the right plate of the first capacitor C1 is in a floating state, at which time the voltage of the right plate of the first capacitor C1 is Vsig — hcg + (VDD-Vrst — hcg) in order to maintain the voltage difference between the left and right plates of the first capacitor C1.
A stage t6 to t7, namely an LCG image voltage sampling stage (global sample LCG sig); in this stage, the gain control transistor M2 is turned on, then the transfer transistor M3 is turned on, the photodiode PD transfers the exposure charge to the floating diffusion FD and the gain adjustment capacitor Cdcg to realize the redistribution of the charge, and finally the first low-gain storage control transistor M10 is turned on, the source terminal of the first source follower transistor M4 is connected to the left plate of the second capacitor C2, and the low-gain image voltage signal Vlsig _ lcg is sampled onto the left plate of the second capacitor C2; the second low-gain storage control transistor M11 is in an off state, the right plate of the second capacitor C2 is in a floating state, and at this time, in order to maintain the voltage difference between the left and right plates of the second capacitor C2, the voltage of the right plate of the second capacitor C2 is Vsig — lcg + (VDD-Vrst — lcg); after the sampling is completed, the first low-gain memory control transistor M10 returns to the off state, the reset transistor M1 returns to the on state, and the subsequent readout operation is controlled by the high-gain row select signal rsH and the low-gain row select signal rsL (e.g., at the stage t9 to t 10).
In the whole process from t2 to t7, the global conversion operation is completed; with the property of the capacitors storing charge, a high gain image voltage signal is stored on the first capacitor C1, a low gain image voltage signal is stored on the second capacitor C2, and image voltages will be read out row by the high gain row select signal rsH and the low gain row select signal rsL. In the read-out stage, the signal on the capacitor plate is read first, then a power supply signal VDD is read, and the difference between the two is made, so that the required Vrst-Vsig can be obtained. Note that az in fig. 4 represents a clear signal of the readout circuit, clk represents a clock signal of the readout circuit, and clock-on represents readout.
Example two
The present embodiment provides a method for controlling a pixel circuit, including the following steps: the pixel circuit according to the first embodiment is provided, and global exposure is realized based on the pixel circuit, and the voltage difference between the image signal and the reset signal in the high-gain transmission mode is obtained through the first capacitor, and the voltage difference between the image signal and the reset signal in the low-gain transmission mode is obtained through the second capacitor, so that the pixel circuit operates in different gain transmission modes.
Specifically, in the process of implementing global exposure based on the pixel circuit shown in fig. 1 (the high-gain reading unit 401 and the low-gain reading unit 402 do not share a source follower transistor), the signal transmission manner may include: reset signal resetting, low gain reset signal acquisition, high gain reset signal acquisition, image signal resetting, high gain image signal acquisition and low gain image signal acquisition are carried out in proper order, also can include: the image signal of the low-gain reading unit is reset while the reset signal is reset, the low-gain reset signal is collected, the high-gain reset signal is collected, the image signal of the low-gain reading unit is reset while the high-gain image signal is collected, and the low-gain image signal is collected.
In practical application, the first high-gain source follower transistor M4 and the first low-gain source follower transistor M9 are switched in different high and low variable voltages, for example, the first high-gain source follower transistor M4 is switched in a high-level variable voltage, the first low-gain source follower transistor M9 is switched in a low-level variable voltage, so that image signal reset of the low-gain reading unit is performed at the same time of high-gain reset signal acquisition, the first low-gain source follower transistor M9 is switched in a high-level variable voltage, and the first high-gain source follower transistor M4 is switched in a low-level variable voltage, so that image signal reset of the high-gain reading unit is performed at the same time of low-gain image signal acquisition. Compared with the first signal transmission mode, the second signal transmission mode (namely, the signal transmission sequence is reset signal, low-gain reset signal acquisition, high-gain reset signal acquisition, image signal reset of the low-gain reading unit and high-gain image signal acquisition, image signal reset of the low-gain reading unit and low-gain image signal acquisition) saves the time of resetting one image signal, thereby saving the time of a pixel period, wherein the second signal transmission mode can be realized based on a circuit which does not share the first source follower transistor.
After the reset signal is reset, the reset transistor M1 is reset to a first potential, and low-gain reset signal acquisition, high-gain reset signal acquisition, image signal reset, high-gain image signal acquisition and low-gain image signal acquisition are carried out at the first potential; when the first high-gain source follower transistor and the first low-gain source follower transistor are present, the potential of the first high-gain source follower transistor is the same and the potential of the first low-gain source follower transistor is the same in the reset signal resetting process and the image signal resetting process. Optionally, the first potential, the potential of the first high-gain source follower transistor, and the potential of the first low-gain source follower transistor are all at or near ground potential. In the reset signal reset process and the image signal reset process, the potential of the first high-gain source following transistor and the potential of the first low-gain source following transistor are set at a sufficiently low level, so that the problem that the rear-end source following transistor cannot be conducted due to the reduction of the FD potential of the floating diffusion point (the potential is reduced due to the overlong exposure time) is solved, and the low-gain reset signal acquisition, the high-gain reset signal acquisition, the image signal reset, the high-gain image signal acquisition and the low-gain image signal acquisition can be carried out at the first potential, so that the power consumption is saved; also, due to the design of the gain control transistor M2, the potential of the floating diffusion point FD is less affected by the exposure time.
Specifically, in the process of implementing global exposure based on the pixel circuit (the high-gain reading unit 401 and the low-gain reading unit 402 share the source follower transistor) shown in fig. 2, the signal transmission manner includes: resetting a reset signal, acquiring a low-gain reset signal, acquiring a high-gain reset signal, resetting an image signal, acquiring a high-gain image signal and acquiring a low-gain image signal in sequence.
After the reset signal is reset, the reset transistor M1 is reset to a first potential, and low-gain reset signal acquisition, high-gain reset signal acquisition, image signal reset, high-gain image signal acquisition and low-gain image signal acquisition are carried out at the first potential; in the reset signal reset process and the image signal reset process, the potential of the common source follower transistor is the same. Optionally, the potentials of the first potential, the common source follower transistor, are both at or near ground potential. In the reset signal resetting process and the image signal resetting process, the potential of the shared source follower transistor is set at a sufficiently low level, so that the problem that the rear-end source follower transistor cannot be conducted due to the reduction of the FD potential of the floating diffusion point (potential reduction caused by overlong exposure time) is solved, and the low-gain reset signal acquisition, the high-gain reset signal acquisition, the image signal resetting, the high-gain image signal acquisition and the low-gain image signal acquisition can be carried out at the first potential, so that the power consumption is saved; also, due to the design of the gain control transistor M2, the potential of the floating diffusion point FD is less affected by the exposure time.
Specifically, the control method comprises the following steps: in a first high-gain transmission mode, the left plate of the first capacitor stores a high-gain reset voltage signal Vrst hcg, the right plate stores a first power supply voltage signal Vdd, and the voltage difference between the left and right plates of the first capacitor is Vdd-Vrst hcg, so that in a second high-gain transmission mode, when the left plate of the first capacitor stores a high-gain image voltage signal Vsig hcg, the right plate stores a high-gain output voltage signal Vsig hcg + (Vdd-Vrst hcg); in the first low-gain transmission mode, the left plate of the second capacitor stores a low-gain reset voltage signal Vrst lcg, the right plate stores a first power supply voltage signal Vdd, and the voltage difference between the left plate and the right plate of the second capacitor is Vdd-Vrst lcg, so that in the second low-gain transmission mode, when the left plate of the second capacitor stores a low-gain image voltage signal Vsig lcg, the right plate stores and outputs a low-gain voltage signal Vsig lcg + (Vdd-Vrst lcg). It should be noted that the specific control manner can be seen in the first embodiment, and is not described herein again.
More specifically, the readout process of the pixel circuit includes a first phase in which the pixel circuit outputs a voltage signal Vsig + (Vdd-Vrst) and a second phase in which the pixel circuit outputs a first power supply voltage signal Vdd. The voltage difference between the image voltage signal and the reset voltage signal in different gain transmission modes, namely the pixel signal, can be obtained by subtracting the voltage signals output in the first stage and the second stage.
Specifically, the signal output modes of the high-gain reading unit and the low-gain reading unit include serial output or parallel output. In practical applications, the serial output and the parallel output can be selected according to specific requirements, which has no influence on the embodiment, and only the on-timings of the high-gain row selection signal rsH and the low-gain row selection signal rsL need to be adjusted.
EXAMPLE III
The present embodiment provides a CMOS image sensor including: at least one pixel circuit as in embodiment one.
Specifically, the CMOS image sensor includes a plurality of pixels arranged in rows and columns in a pixel array, and the pixels correspond to pixel circuits. In practical application, the pixels correspond to the pixel circuits one to one, namely each pixel is composed of the pixel circuits; of course, a plurality of pixels may share the same reading module 400, which has no influence on the present embodiment.
Specifically, in one example, the CMOS image sensor includes a first semiconductor substrate and a second semiconductor substrate stacked, the photosensitive control module 300 is located in the first semiconductor substrate, and the reading module 400 is located in the second semiconductor substrate. In yet another example, the CMOS image sensor includes a first semiconductor substrate and a second semiconductor substrate stacked, the photosensitive control module 300 and the reading module 400 are located in the first semiconductor substrate, and the CMOS image sensor further includes a logic circuit located in the second semiconductor substrate. In still another example, the CMOS image sensor includes a first semiconductor substrate, a second semiconductor substrate, and a third semiconductor substrate stacked, the light sensing control module 300 is located in the first semiconductor substrate, the reading module 400 is located in the second semiconductor substrate, and the CMOS image sensor further includes a logic circuit, and the logic circuit is located in the third semiconductor substrate. It should be noted that the electrical connection (bonding) between the substrates can be implemented by using the existing technology based on the circuit, for example, the electrical connection between the transistor devices is implemented by using metal pads and interconnect lines or by using TSV vias.
In summary, according to the pixel circuit and the CMOS image sensor of the present invention, the dynamic range of the CMOS image sensor is effectively increased by the design of the gain control module and the reading module and by using the dual conversion gain technology; the high-intensity illumination area is provided with a large capacitor, so that stored charges are improved, the gain is reduced to improve the dynamic range, the low-intensity illumination area is provided with a small capacitor, the gain is improved, and the high sensitivity is realized. Therefore, the utility model effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the utility model. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (11)
1. A pixel circuit, comprising: a reset module, a gain control module, a photosensitive control module and a reading module, wherein,
the reset module comprises a reset transistor, a grid end of the reset transistor is connected with a reset control signal, a first connecting end is connected with power voltage, and a second connecting end is connected to the floating diffusion point;
the gain control module is connected between the second connecting end of the reset transistor and the floating diffusion point, is controlled by a gain control signal, and is used for adjusting the equivalent charge storage capacity of the floating diffusion point according to the gain control signal so as to enable the pixel circuit to work in different gain transmission modes;
the photosensitive control module is connected between the floating diffusion point and a first reference voltage, is controlled by a transmission control signal, and is used for generating exposure charges according to a photoelectric effect and transferring and outputting the exposure charges according to the transmission control signal;
the reading module comprises a high-gain reading unit and a low-gain reading unit which are connected to the floating diffusion point, wherein the high-gain reading unit is used for reading and outputting a voltage signal of the floating diffusion point in a high-gain transmission mode; the low-gain reading unit is used for reading and outputting a voltage signal of the floating diffusion point in a low-gain transmission mode; the high-gain reading unit comprises a first capacitor, the low-gain reading unit comprises a second capacitor, the first capacitor is used for obtaining the voltage difference between an image signal and a reset signal in a high-gain transmission mode, and the second capacitor is used for obtaining the voltage difference between the image signal and the reset signal in a low-gain transmission mode.
2. The pixel circuit of claim 1, wherein the high-gain transmission modes include a first high-gain transmission mode in which a left plate of the first capacitor stores a high-gain reset voltage signal Vrst hcg and a right plate stores a first power supply voltage signal Vdd, and a second high-gain transmission mode in which the left plate of the first capacitor stores a high-gain image voltage signal Vsig hcg and the right plate stores a high-gain output voltage signal Vsig hcg + (Vdd-Vrst hcg); and/or the presence of a gas in the gas,
the low-gain transmission modes include a first low-gain transmission mode in which the left plate of the second capacitor stores a low-gain reset voltage signal Vrst lcg and the right plate stores a first supply voltage signal Vdd, and a second low-gain transmission mode in which the left plate of the second capacitor stores a low-gain image voltage signal Vsig lcg and the right plate stores an output low-gain voltage signal Vsig lcg + (Vdd-Vrst lcg).
3. The pixel circuit according to claim 1, wherein the high-gain reading unit further comprises at least: the first high-gain source following transistor, the first high-gain storage control transistor, the second high-gain source following transistor and the first row selection transistor;
the grid end of the first high-gain source following transistor is connected to the floating diffusion point, the first connecting end is connected to a first variable voltage, and the second connecting end is connected with the first connecting end of the first high-gain storage control transistor; the grid end of the first high-gain storage control transistor is connected with a first high-gain storage control signal, and the second connecting end of the first high-gain storage control transistor is connected with the left pole plate of the first capacitor; the right pole plate of the first capacitor is connected with the second connecting end of the second high-gain storage control transistor and the gate end of the second high-gain source follower transistor; the grid end of the second high-gain storage control transistor is connected with a second high-gain storage control signal, and the first connecting end is connected with a first power supply voltage; the first connection end of the second high-gain source following transistor is connected with a second power supply voltage, and the second connection end of the second high-gain source following transistor is connected with the first connection end of the first row of selection transistors; the grid end of the first row selection transistor is connected with a high-gain row selection signal, and the second connecting end is used as the output end of the high-gain reading unit;
the low-gain reading unit further includes at least: the first low-gain source following transistor, the first low-gain storage control transistor, the second low-gain source following transistor and the second row selecting transistor;
the grid end of the first low-gain source following transistor is connected to the floating diffusion point, the first connecting end is connected to a second variable voltage, and the second connecting end is connected with the first connecting end of the first low-gain storage control transistor; the grid end of the first low-gain storage control transistor is connected with a first low-gain storage control signal, and the second connecting end of the first low-gain storage control transistor is connected with the left pole plate of the second capacitor; the right pole plate of the second capacitor is connected with the second connecting end of the second low-gain storage control transistor and the gate end of the second low-gain source follower transistor; the grid end of the second low-gain storage control transistor is connected with a second low-gain storage control signal, and the first connecting end is connected with a third power supply voltage; the first connecting end of the second low-gain source follower transistor is connected with a fourth power supply voltage, and the second connecting end of the second low-gain source follower transistor is connected with the first connecting end of the second row selection transistor; and the grid end of the second row selection transistor is connected with a low-gain row selection signal, and the second connecting end is used as the output end of the low-gain reading unit.
4. The pixel circuit according to claim 3, wherein the first high-gain source follower transistor and the first low-gain source follower transistor are the same source follower transistor, a gate terminal of the common source follower transistor is connected to the floating diffusion point, a first connection terminal is connected to a variable voltage, and a second connection terminal is respectively connected to a first connection terminal of the first high-gain memory control transistor and a first connection terminal of the first low-gain memory control transistor.
5. The pixel circuit according to claim 3 or 4, wherein the high-gain reading unit comprises a third capacitor connected between the second connection terminal of the first high-gain storage control transistor and a second reference voltage; and/or the low-gain reading unit comprises a fourth capacitor, and the fourth capacitor is connected between the second connecting end of the first low-gain storage control transistor and a third reference voltage.
6. The pixel circuit of claim 1, wherein the gain control module comprises: the gate end of the gain control transistor is connected with the gain control signal, the first connecting end is connected with the second connecting end of the reset transistor and is connected with a fourth reference voltage through the gain adjusting capacitor, and the second connecting end is connected with the floating diffusion point.
7. The pixel circuit according to claim 6, wherein the gain adjustment capacitance is a parasitic capacitance of the reset transistor and the gain control transistor connection point to ground; or, the gain adjusting capacitor is a device capacitor.
8. The pixel circuit according to claim 1, wherein the light sensing control module comprises: the output end of the photoelectric conversion element is connected with the first connecting end of the transmission transistor, and the other end of the photoelectric conversion element is connected with the first reference voltage; and the grid end of the transmission transistor is connected with the transmission control signal, and the second connecting end is connected to the floating diffusion point.
9. The pixel circuit according to claim 1, wherein the high-gain reading unit and the low-gain reading unit correspond to the same or different column lines to achieve serial output or parallel output of signals, respectively.
10. A CMOS image sensor, comprising: a pixel circuit as claimed in any one of claims 1-9.
11. The image sensor of claim 10, wherein the image sensor comprises a first semiconductor substrate and a second semiconductor substrate arranged in a stack, the photosensitive control module is located in the first semiconductor substrate, and the reading module is located in the second semiconductor substrate; or, the image sensor comprises a first semiconductor substrate, a second semiconductor substrate and a third semiconductor substrate which are stacked, the photosensitive control module is located in the first semiconductor substrate, the reading module is located in the second semiconductor substrate, and the image sensor further comprises a logic circuit which is located in the third semiconductor substrate; or, the image sensor includes a first semiconductor substrate and a second semiconductor substrate stacked, the light sensing control module and the reading module are located in the first semiconductor substrate, and the image sensor further includes a logic circuit located in the second semiconductor substrate.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN115633265A (en) * | 2022-09-30 | 2023-01-20 | 维沃移动通信有限公司 | Photosensitive pixel structure, image sensor and electronic device |
| CN116055903A (en) * | 2022-12-30 | 2023-05-02 | 维沃移动通信有限公司 | Control method and device of image processor, electronic equipment and storage medium |
| CN116112814A (en) * | 2022-09-30 | 2023-05-12 | 维沃移动通信有限公司 | Photosensitive pixel structure, image sensor and electronic equipment |
| WO2024254854A1 (en) * | 2023-06-16 | 2024-12-19 | 思特威(上海)电子科技股份有限公司 | Image sensor and reading method therefor, and electronic device |
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| CN115633265A (en) * | 2022-09-30 | 2023-01-20 | 维沃移动通信有限公司 | Photosensitive pixel structure, image sensor and electronic device |
| CN116112814A (en) * | 2022-09-30 | 2023-05-12 | 维沃移动通信有限公司 | Photosensitive pixel structure, image sensor and electronic equipment |
| WO2024067510A1 (en) * | 2022-09-30 | 2024-04-04 | 维沃移动通信有限公司 | Photosensitive pixel structure, image sensor, and electronic device |
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| CN116055903A (en) * | 2022-12-30 | 2023-05-02 | 维沃移动通信有限公司 | Control method and device of image processor, electronic equipment and storage medium |
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