CN216721459U - Image sensor reading circuit, image sensor, and electronic apparatus - Google Patents

Abstract

A kind of image sensor reads out the circuit and image sensor, electronic device, in the field of sensor, the switch selective circuit is connected with pixel circuit of the image sensor, under the first state, insert the slope voltage to the first node, insert reset signal and image signal that the pixel circuit outputs under the high conversion gain to the second node sequentially; in a second state, the coupling signal of the ramp voltage and a reset signal or an image signal output by the pixel circuit under the low conversion gain is connected to the first node, and the reference voltage is connected to the second node; the analog-to-digital conversion circuit respectively quantizes the high-gain reset signal and the high-gain image signal to obtain an effective image signal quantization value under high gain, and respectively quantizes the low-gain reset signal and the low-gain image signal to obtain an effective image signal quantization value under low gain; the high dynamic range of the image sensor is realized, and meanwhile, the cost is reduced and the volume is reduced.

Description

Image sensor reading circuit, image sensor, and electronic apparatus

Technical Field

The application belongs to the field of sensors, and particularly relates to an image sensor reading circuit, an image sensor and electronic equipment.

Background

The dynamic range is a key factor of the imaging quality of the image sensor, the dynamic range is large, scene image information in a wider light intensity range can be output, and richer image details are presented. Typically, the dynamic range of the image sensor output is about 60dB to 70dB, and the dynamic range required in general natural environment applications to capture image information of both highlights and shadows is about 100 dB. In the design of an image sensor, there are several ways to improve the dynamic range, for example, further improving the full-well charge capacity of a pixel circuit, and obtaining a larger dynamic range; or a mode of reading multi-frame images and performing multi-frame synthesis is adopted to realize the high dynamic range of the image sensor.

The Double Conversion Gain (DCG) is applied to the pixel circuit of the image sensor, and the Conversion Gain is improved by a smaller integral capacitor under the condition of low illumination so as to improve the sensitivity; under the condition of high illumination, the storage charge is increased by a larger integration capacitor, and the conversion gain is reduced to improve the dynamic range. The related image sensor reading circuit sequentially reads a low-conversion-gain reset signal, a high-conversion-gain image signal and a low-conversion-gain image signal which are output by the pixel array through a control circuit according to control; the readout circuit comprises a selection switch, a low conversion gain analog-to-digital conversion circuit and a high conversion gain analog-to-digital conversion circuit, wherein the low conversion gain analog-to-digital conversion circuit is used for quantizing a reset signal and an image signal output by the pixel array under the condition of low conversion gain; the high conversion gain analog-to-digital conversion circuit is used for quantizing the reset signal and the image signal output by the pixel array under the high conversion gain. Therefore, two analog-to-digital conversion circuits are needed to process the signal output under low conversion gain and the signal output under high conversion gain respectively, so that the cost is high and the size is large.

SUMMERY OF THE UTILITY MODEL

The present application aims to provide an image sensor readout circuit, an image sensor, and an electronic device, which are intended to solve the disadvantages of the related image sensor readout circuit, such as high cost and large size.

The embodiment of the application provides an image sensor readout circuit, includes:

a switch selection circuit connected to a pixel circuit of the image sensor, the pixel circuit configured to sequentially output a high-gain reset signal, a high-gain image signal, a low-gain image signal, and a low-gain reset signal; the switch selection circuit is configured to connect a ramp voltage to a first node and sequentially connect a reset signal and an image signal output by the pixel circuit under high conversion gain to a second node in a first state; the switch selection circuit is further configured to switch in a second state a coupling signal of the ramp voltage and a reset signal or an image signal output by the pixel circuit at a low conversion gain to the first node, and simultaneously switch in a reference voltage to the second node;

and the analog-to-digital conversion circuit is connected with the first node and the second node and is configured to quantize the high-gain reset signal and the high-gain image signal respectively to obtain an effective image signal quantization value under high gain and quantize the low-gain reset signal and the low-gain image signal respectively to obtain an effective image signal quantization value under low gain.

An embodiment of the present application further provides an image sensor, including:

a pixel circuit configured to sequentially output a high-gain reset signal, a high-gain image signal, a low-gain image signal, and a low-gain reset signal; and

such as the readout circuit of the image sensor described above.

The embodiment of the application also provides an electronic device which comprises the image sensor.

Compared with the prior art, the embodiment of the utility model has the following beneficial effects: because the low-gain image signal and the high-gain image signal are connected with the analog-to-digital conversion circuit in different modes through the switch selection circuit for quantization processing, a single analog-to-digital conversion circuit quantization double-conversion gain mode is realized, the high dynamic range of the image sensor is realized, and meanwhile, the cost is reduced and the size is reduced. Since the output of the pixel circuit does not need to be sampled and held to improve the KT/C noise of the circuit, the noise level of the circuit is lower, and the performance of the image sensor is further improved.

Drawings

In order to more clearly illustrate the technical utility model in the embodiment of the present invention, the drawings used in the description of the embodiment will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a readout circuit of an image sensor according to an embodiment of the present disclosure;

fig. 2 is a schematic diagram illustrating another structure of an analog-to-digital conversion circuit in a readout circuit of an image sensor according to an embodiment of the present disclosure;

FIG. 3 is a diagram of an exemplary circuit configuration of a readout circuit of an image sensor according to an embodiment of the present disclosure;

fig. 4 is a timing diagram of the image sensor readout circuit shown in fig. 3.

Detailed Description

In order to make the technical problems, technical solutions and advantageous effects to be solved by the present application clearer, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

It will be understood that when an element is referred to as being "secured to" or "disposed on" another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element.

It will be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like, refer to an orientation or positional relationship illustrated in the drawings for convenience in describing the present application and to simplify description, and do not indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the present application.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.

Fig. 1 shows a schematic structural diagram of a readout circuit of an image sensor provided in a first embodiment of the present application, and for convenience of description, only the parts related to the present embodiment are shown, which are detailed as follows:

the image sensor readout circuit described above has two states.

The image sensor readout circuit includes a switch selection circuit 12 and an analog-to-digital conversion circuit 13.

The pixel circuit 11 is configured to sequentially output a high-gain image signal and a low-gain image signal.

A switch selection circuit 12 connected to a pixel circuit 11 of the image sensor, the pixel circuit 11 being configured to output a high-gain reset signal, a high-gain image signal, a low-gain image signal, and a low-gain reset signal in this order; the switch selection circuit 12 is configured to switch the ramp voltage to a first node and sequentially switch the reset signal and the image signal output by the pixel circuit 11 at a high conversion gain to a second node in a first state; the switch selection circuit 12 is further configured to, in the second state, switch in the first node a coupling signal of the ramp voltage and a reset signal or an image signal output by the pixel circuit 11 at a low conversion gain, while switching in the second node the reference voltage.

And an analog-to-digital conversion circuit 13 connected to the first node and the second node, and configured to quantize the high-gain reset signal and the high-gain image signal respectively to obtain an effective image signal quantization value at a high gain, and quantize the low-gain reset signal and the low-gain image signal respectively to obtain an effective image signal quantization value at a low gain.

Wherein, the high-gain image signal refers to an image signal under high conversion gain; the low-gain image signal refers to an image signal at a low conversion gain. The high-gain reset signal refers to a reset signal under high conversion gain; the low-gain reset signal refers to a reset signal at a low conversion gain. The effective image signal quantization value under high gain refers to the difference value of the high gain reset signal and the high gain image signal; the effective image signal quantization value at low gain refers to the difference between the low gain reset signal and the low gain image signal.

Wherein the high-gain image signal and the low-gain image signal are acquired by the same exposure.

The high-gain image signal is quantized by combining the high-gain reset signal, and the low-gain image signal is quantized by combining the low-gain reset signal, so that the precision of the image signal quantization result is improved.

Note that, as shown in fig. 2, the analog-to-digital conversion circuit 13 includes a comparison circuit 131, a counter 132, and a memory 133, which are connected in sequence; the comparator circuit 131 includes a comparator having a non-inverting input connected to the first node and an inverting input connected to the second node.

In a specific implementation, when the analog-to-digital conversion circuit 13 quantizes the high-gain reset signal, the comparison circuit 131 is configured to compare the ramp voltage with the high-gain reset signal and output a first comparison signal; the counter 132 is configured to count down when receiving the first comparison signal, and record a first count result when the state of the first comparison signal is inverted (e.g., from high to low, or from low to high). In a specific embodiment, when the first comparison signal is 0, the counter stops counting, and the first counting result is recorded.

In a specific implementation, when the analog-to-digital conversion circuit 13 quantizes the high-gain image signal, the comparison circuit 131 is configured to compare the ramp voltage and the high-gain image signal and output a second comparison signal; the counter 132 is configured to count up from the first count result when the second comparison signal is received, and output a second count result when the state of the second comparison signal is inverted, the second count result being a difference between the quantization results of the high-gain image signal and the high-gain reset signal; the memory 133 is configured to store the second count result as an effective image signal quantization value at a high gain.

In a specific implementation, when the analog-to-digital conversion circuit 13 quantizes the low-gain image signal, the comparison circuit 131 is configured to compare the first composite signal with the reference signal and output a third comparison signal; the counter 132 is configured to count down when receiving the third comparison signal, and record a third counting result when the state of the third comparison signal is reversed; the first composite signal is a coupled signal of the ramp voltage and the low-gain image signal.

In a specific implementation, when the analog-to-digital conversion circuit 13 quantizes the low-gain reset signal, the comparison circuit 131 is configured to compare the second composite signal with the reference signal and output a fourth comparison signal; the counter 132 is configured to count up from the third count result when receiving the fourth comparison signal, and output a fourth count result when the state of the fourth comparison signal is inverted, the fourth count result being a difference value of quantization results of the low-gain image signal and the low-gain reset signal; the memory 133 is configured to store the fourth count result as an effective image signal quantization value at a low gain; the second composite signal is a coupled signal of the ramp voltage and the low-gain reset signal.

Through the comparison circuit 131, the counter 132 and the memory 133 which are connected in sequence, the low-gain image signal and the high-gain image signal are quantized in different modes, a quantization double-conversion gain mode of a single analog-to-digital conversion circuit 13 is realized, and the cost and the volume are reduced while the high dynamic range of the image sensor is realized.

By way of example and not limitation, the reference voltage may be adjustable.

The gain of the circuit in the low conversion gain mode can be further improved by adjusting the reference voltage.

By way of example and not limitation, the slope of the ramp voltage may be adjustable.

In the process of quantizing the output of the pixel circuit 11, the slopes of the low conversion gain down-ramp voltage and the high conversion gain down-ramp voltage thereof may be set to be different, and thus the circuit gain may be further increased, thereby further increasing the dynamic range of the image sensor.

The embodiment of the utility model also provides a working method of the image sensor reading circuit, which comprises the steps 101 to 102.

Step 101: and inputting a first switch control signal to enable the switch selection circuit to access the ramp voltage to a first node, respectively accessing a high-gain reset signal and a high-gain image signal which are sequentially output under the high gain of the pixel circuit to a second node, and enabling the analog-to-digital conversion circuit to respectively quantize the high-gain reset signal and the high-gain image signal so as to obtain an effective image signal quantization value under the high gain.

Step 102: inputting a second switch control signal to enable the switch selection circuit to connect a ramp voltage and the low-gain image signal and the low-gain reset signal which are sequentially output under the low gain of the pixel circuit to a first node, and connect a reference voltage to a second node; and enabling an analog-to-digital conversion circuit to quantize the low-gain image signal and the low-gain reset signal to obtain an effective image signal quantization value under low gain.

When the analog-to-digital conversion circuit includes the comparison circuit, the counter, and the memory, step 100 includes step a1 and step B1.

Step A1: the comparison circuit compares the ramp voltage with the high-gain reset signal and outputs a first comparison signal.

Step B1: and the counter counts down when receiving the first comparison signal, and records a first counting result when the state of the first comparison signal is reversed.

When the analog-to-digital conversion circuit includes the comparison circuit, the counter, and the memory, step 101 includes step a2, step B2, and step C2.

Step A2: the comparison circuit compares the ramp voltage with the high-gain image signal and outputs a second comparison signal.

Step B2: and the counter starts to count up from the first counting result when receiving the second comparison signal, and outputs a second counting result when the state of the second comparison signal is reversed, wherein the second counting result is the difference value of the high-gain reset signal and the high-gain image signal quantization result.

Step C2: the memory is configured to store the second count result as an effective image signal quantization value at the high gain.

When the analog-to-digital conversion circuit includes the comparison circuit, the counter, and the memory, step 102 includes step a3 and step B3.

Step A3: the comparison circuit compares the first composite signal with the reference signal and outputs a third comparison signal.

Step B3: and the counter counts down when receiving the third comparison signal, and records a third counting result when the state of the third comparison signal is reversed.

Wherein the first composite signal is a coupled signal of the ramp voltage and the low-gain image signal.

When the analog-to-digital conversion circuit includes the comparison circuit, the counter, and the memory, step 103 includes step a4, step B4, and step C4.

Step A4: the comparison circuit compares the second composite signal with the reference signal and outputs a fourth comparison signal.

Step B4: the counter is configured to count up from the third count result when the fourth comparison signal is received, and output a fourth count result when the state of the fourth comparison signal is inverted, the fourth count result being a difference between quantization results of the low-gain image signal and the low-gain reset signal.

Step C4: the memory is configured to store the fourth count result and to use the fourth count result as an effective image signal quantization value at the low gain.

Wherein the second composite signal is a coupled signal of the ramp voltage and the low-gain reset signal.

When the analog-to-digital conversion circuit comprises the comparison circuit, the counter and the memory, step 99 is further included before step 100 and between step 101 and step 102.

And 99: and clearing the comparison circuit.

Fig. 3 shows an exemplary circuit structure of a readout circuit of an image sensor provided in an embodiment of the present invention, and for convenience of description, only the parts related to the embodiment of the present invention are shown, and detailed descriptions are as follows:

the pixel circuit 11 includes a reset transistor RST, a dual conversion gain transistor DCG, a transfer transistor TX, a source follower transistor SF, a row selection transistor RS, a photoelectric conversion element PD, and a dual conversion gain capacitance Cdcg.

A drain of the reset transistor RST and a drain of the source follower transistor SF are commonly connected to a first power supply PIXVDD, a source of the reset transistor RST is connected to a first terminal of the dual conversion gain capacitor Cdcg and a drain of the dual conversion gain transistor DCG, a source of the dual conversion gain transistor DCG, a gate of the source follower transistor SF, and a source of the transfer transistor TX are commonly connected to the floating diffusion FD, a drain of the transfer transistor TX is connected to a cathode of the photoelectric conversion element PD, a source of the source follower transistor SF is connected to a drain of the row selection transistor RS, a source of the row selection transistor RS is used as an output terminal of the pixel circuit 11 to output a high-gain image signal, a low-gain image signal, a high-gain reset signal, and a low-gain reset signal, a gate of the reset transistor RST is connected to the reset signal RST, a gate of the dual conversion gain transistor DCG is connected to the conversion gain control signal DCG, the grid of the row selection transistor RS is connected with a row selection signal rowsel, the grid of the transmission transistor TX is connected with a control signal TX, the second end of the double-conversion gain capacitor Cdcg is connected with a second power supply VC, and the anode of the photoelectric conversion element PD is connected with the power supply ground.

The comparison circuit 131 includes a comparator U1, a first clear switch cmp _ az1, and a second clear switch cmp _ az 2;

a non-inverting input terminal Vinp of the comparator U1 and a first terminal of the first clear switch cmp _ az1 are commonly connected to a first node, an inverting input terminal Vinn of the comparator U1 and a first terminal of the second clear switch cmp _ az2 are commonly connected to a second node, a first non-inverting output terminal Vop1 of the comparator U1 is connected to a second terminal of the first clear switch cmp _ az1, a first inverting output terminal Von1 of the comparator U1 is connected to a second terminal of the second clear switch cmp _ az2, and an output terminal Vout of the comparator U1 serves as an output terminal of the comparison circuit 131.

By setting the first clear switch cmp _ az1 and the second clear switch cmp _ az2, the comparator U1 is cleared in time, and the precision of the comparison circuit 131 is improved.

The switch selection circuit 12 includes a first capacitor C1, a second capacitor C2, a third capacitor C3, a first high-gain switch SH1, a first low-gain switch SL1, and a second low-gain switch SL 2;

a first terminal of the first high-gain switch SH1 and a first terminal of the first low-gain switch SL1 are commonly used as a high-gain image signal input terminal of the switch selection circuit 12, a high-gain reset signal input terminal of the switch selection circuit 12, a low-gain image signal input terminal of the switch selection circuit 12, and a low-gain reset signal input terminal of the switch selection circuit 12, a second terminal of the first low-gain switch SL1 is connected to a first terminal of a third capacitor C3, a first terminal of a second capacitor C2 is connected to a ramp voltage, a second terminal of the third capacitor C3 and a second terminal of a second capacitor C2 are commonly connected to a first node, a second terminal of the first high-gain switch SH1 is connected to a first terminal of a first capacitor C1, a first terminal of a second low-gain switch SL2 is connected to a reference voltage, and a second terminal of the first capacitor C1 and a second terminal of a second low-gain switch SL2 are commonly connected to a second node.

The third capacitor C3 and the second capacitor C2 may both be variable capacitors. Adjusting the variable capacitance can further improve the circuit gain.

The switch selection circuit 12 further includes a second high-gain switch SH 2;

the first end of the second high-gain switch SH2 is connected to a ramp voltage, and the second end of the second high-gain switch SH2 is connected to the first end of the third capacitor C3.

The gain of the circuit is further adjusted by coupling a ramp voltage to the first node through a plurality of ports.

The following further description of the operation shown in fig. 3 is provided in conjunction with the working principle:

fig. 4 is a timing diagram of the image sensor readout circuit shown in fig. 3.

At time t0, the row selection signal rowsel is set to high level, the row selection transistor RS is turned on, at this time, the high gain control signal SH is set high, the first high gain switch SH1 and the second high gain switch SH2 are turned on, the low gain control signal SL is set low, the first low gain switch SL1 and the second low gain switch SL2 are turned off, and the output terminal pixout of the pixel circuit 11 and the inverting input terminal Vinn of the comparator U1 are turned on; the ramp voltage vramp and the non-inverting input Vinp of the comparator U1 are turned on.

At time t1, the clear control signal cmp _ az goes high, the first clear switch cmp _ az1 and the second clear switch cmp _ az2 turn on, the non-inverting input terminal Vinp of the comparator U1 and the first-stage non-inverting output terminal Vop1 of the comparator U1 are shorted together, the inverting input terminal Vinn of the comparator U1 and the first-stage inverting output Von1 of the comparator U1 are shorted together, and the comparator U1 starts to clear.

At time t2, reset signal rst is set low and transition gain control signal dcg is set low, resulting in a high gain reset signal.

At time t3, the clear control signal cmp _ az is low and the first clear switch cmp _ az1 and the second clear switch cmp _ az2 are open.

At time t4, the ramp voltage vramp starts to fall, the counter 132 starts to count down, the ramp voltage vramp and the high-gain reset signal pixout are capacitively coupled to the non-inverting input terminal Vinp of the comparator U1 and the inverting input terminal Vinn of the comparator U1, respectively, when the ramp voltage vramp and the high-gain reset signal pixout overlap, the comparator U1 outputs 0, and the counter 132 stops counting, so as to obtain a quantization result (a first count result) of the high-gain reset signal.

At time t5, the high-gain reset signal quantization ends, and the ramp voltage vramp returns to the reference state.

At the time t6 to t7, the control signal TX is set to high level, the transmission transistor TX is turned on, and starts to transmit the image signal, and the output terminal pixout of the pixel circuit 11 is capacitively coupled to the inverting input terminal Vinn of the comparator U1, so as to obtain the high-gain image signal.

At time t8, the ramp voltage vramp starts to fall, the counter 132 starts to count up, the ramp voltage vramp and the high-gain image signal pixout are capacitively coupled to the non-inverting input terminal Vinp of the comparator U1 and the inverting input terminal Vinn of the comparator U1, when the ramp voltage vramp and the high-gain image signal pixout overlap, the comparator outputs 0, and the counter 132 stops counting, so that the difference between the high-gain image signal and the high-gain reset signal, that is, the effective image signal quantization value under high gain is obtained.

At time t9, the high-gain image signal quantization ends, and the ramp voltage vramp starts to return to the reference state.

At time t10, the conversion gain control signal DCG is set to high, the dual conversion gain transistor DCG is turned on, the high gain control signal SH is set low, the first high gain switch SH1 and the second high gain switch SH2 are turned off, the low gain control signal SL is set high, the first low gain switch SL1 and the second low gain switch SL2 are turned on, the image sensor readout circuit is switched to the low conversion gain mode, the ramp voltage vramp and the output terminal pixout of the pixel circuit 11 are capacitively coupled to the non-inverting input terminal Vinp of the comparator U1, and the reference voltage vref is turned on to the inverting input terminal Vinn of the comparator U1.

At time t11, setting the control signal TX to be high level, setting the zero clearing control signal cmp _ az to be high, turning on the transmission transistor TX, and starting to transmit the residual image signal; the first clear switch cmp _ az1 and the second clear switch cmp _ az2 are turned on, the non-inverting input terminal Vinp of the comparator U1 and the first-stage non-inverting output terminal Vop1 of the comparator U1 are shorted together, the inverting input terminal Vinn of the comparator U1 and the first-stage inverting output Von1 of the comparator U1 are shorted together, and the comparator U1 starts to be cleared again.

At time t12, the control signal TX goes low and the pass transistor TX is turned off.

At time t13, the clear control signal cmp _ az is low and the first clear switch cmp _ az1 and the second clear switch cmp _ az2 are open.

At time t13, the ramp voltage vramp starts to fall, the counter 132 starts to count down, the ramp voltage vramp and the low-gain image signal pixout are capacitively coupled to the non-inverting input terminal Vinp of the comparator U1, the ramp voltage (first composite signal) to which the ramp voltage vramp and the low-gain image signal pixout are coupled is generated at the non-inverting input terminal Vinp of the comparator U1, the inverting input terminal Vinn of the comparator U1 is turned on with the reference voltage vref, when the first composite signal and the reference voltage vref overlap, the comparator U1 outputs 0, the counter 132 stops counting, and the quantization result (third counting result) of the low-gain image signal is obtained.

At time t14, the low-gain image signal quantization ends, and the ramp voltage vramp returns to the reference state.

At time t15, the reset signal rst goes high, and the pixel circuit 11 outputs a low-gain reset signal.

At time t16, the ramp voltage vramp starts to fall, the counter 132 starts counting up, the ramp voltage vramp and the low-gain reset signal pixout are capacitively coupled to the non-inverting input terminal Vinp of the comparator U1, the ramp voltage (second composite signal) to which the ramp voltage vramp and the low-gain reset signal pixout are coupled is generated at the non-inverting input terminal Vinp of the comparator U1, the inverting input terminal Vinn of the comparator U1 is turned on with the reference voltage vref, when the second composite signal and the reference voltage vref overlap, the comparator U1 outputs 0, and the counter 132 stops counting, and a difference between the low-gain image signal and the low-gain reset signal, that is, an effective image signal quantization value at low gain is obtained.

At time t17, the high gain reset signal quantization ends and the ramp voltage vramp begins to return to the reference state.

The quantization of the pixel circuit 11 is finished, the effective image signal quantized value at the low gain and the effective image signal quantized value at the high gain are obtained, and then the value of the counter 132 is written in the memory 133.

Wherein, the overlapping means that the two are equal and the overlapping is consistent.

The embodiment of the utility model is connected with a pixel circuit of an image sensor through a switch selection circuit, and the pixel circuit sequentially outputs a high-gain reset signal, a high-gain image signal, a low-gain image signal and a low-gain reset signal; the switch selection circuit accesses the ramp voltage to a first node in a first state, and sequentially accesses the reset signal and the image signal output by the pixel circuit under high conversion gain to a second node; in a second state, the coupling signal of the ramp voltage and a reset signal or an image signal output by the pixel circuit under the low conversion gain is connected to the first node, and the reference voltage is connected to the second node; the analog-to-digital conversion circuit is connected with the first node and the second node, respectively quantizes the high-gain image signals to obtain effective image signal quantized values under high gain, and respectively quantizes the low-gain reset signals and the low-gain image signals to obtain effective image signal quantized values under low gain; because the low-gain image signal and the high-gain image signal are connected with the analog-to-digital conversion circuit in different modes through the switch selection circuit for quantization processing, a single analog-to-digital conversion circuit quantization double-conversion gain mode is realized, the high dynamic range of the image sensor is realized, and meanwhile, the cost is reduced and the size is reduced. Since the output of the pixel circuit does not need to be sampled and held to improve the KT/C noise of the circuit, the noise level of the circuit is lower, and the performance of the image sensor is further improved.

It should be understood that, the sequence numbers of the steps in the foregoing embodiments do not imply an execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.

The above-mentioned embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.

Claims (11)

1. An image sensor readout circuit having two states, comprising:

a switch selection circuit connected to a pixel circuit of the image sensor, the pixel circuit configured to sequentially output a high-gain reset signal, a high-gain image signal, a low-gain image signal, and a low-gain reset signal; the switch selection circuit is configured to connect a ramp voltage to a first node and sequentially connect a reset signal and an image signal output by the pixel circuit under high conversion gain to a second node in a first state; the switch selection circuit is further configured to switch in a second state a coupling signal of the ramp voltage and a reset signal or an image signal output by the pixel circuit at a low conversion gain to the first node, and simultaneously switch in a reference voltage to the second node;

and the analog-to-digital conversion circuit is connected with the first node and the second node and is configured to quantize the high-gain reset signal and the high-gain image signal respectively to obtain an effective image signal quantization value under high gain and quantize the low-gain reset signal and the low-gain image signal respectively to obtain an effective image signal quantization value under low gain.

2. The image sensor readout circuit of claim 1, wherein the analog-to-digital conversion circuit comprises a comparison circuit, a counter, and a memory connected in sequence;

the comparator circuit comprises a comparator, wherein a non-inverting input end of the comparator is connected with the first node, and an inverting input end of the comparator is connected with the second node.

3. The image sensor readout circuit of claim 2, wherein when the analog-to-digital conversion circuit quantizes the high-gain reset signal, the comparison circuit is configured to compare the ramp voltage and the high-gain reset signal and output a first comparison signal; the counter is configured to count down when receiving the first comparison signal, and record a first counting result when the state of the first comparison signal is reversed; when the analog-to-digital conversion circuit quantizes the high-gain image signal, the comparison circuit is configured to compare the ramp voltage and the high-gain image signal and output a second comparison signal; the counter is configured to count up from the first count result when receiving the second comparison signal, and output a second count result when a state of the second comparison signal is inverted, the second count result being a difference value of quantization results of the high-gain image signal and the high-gain reset signal; the memory is configured to store the second count result as an effective image signal quantization value at the high gain;

when the analog-to-digital conversion circuit quantizes the low-gain image signal, the comparison circuit is configured to compare the first composite signal with a reference signal and output a third comparison signal; the counter is configured to count down when receiving the third comparison signal, and record a third counting result when the state of the third comparison signal is reversed; wherein the first composite signal is a coupled signal of the ramp voltage and the low-gain image signal;

when the analog-to-digital conversion circuit quantizes the low-gain reset signal, the comparison circuit is configured to compare a second composite signal with the reference signal and output a fourth comparison signal; the counter is configured to count up from the third counting result when receiving the fourth comparison signal, and output a fourth counting result when the state of the fourth comparison signal is reversed, the fourth counting result being a difference between the quantization results of the low-gain image signal and the low-gain reset signal; the memory is configured to store the fourth count result and to use the fourth count result as an effective image signal quantization value at the low gain; wherein the second composite signal is a coupled signal of the ramp voltage and the low-gain reset signal.

4. The image sensor readout circuit of claim 2, wherein the comparison circuit comprises the comparator, a first clear switch, and a second clear switch;

the positive phase input end of the comparator and the first end of the first zero clearing switch are connected to the first node in a shared mode, the negative phase input end of the comparator and the first end of the second zero clearing switch are connected to the second node in a shared mode, the first positive phase output end of the comparator is connected with the second end of the first zero clearing switch, the first negative phase output end of the comparator is connected with the second end of the second zero clearing switch, and the output end of the comparator serves as the output end of the comparison circuit.

5. The image sensor readout circuit of claim 1, wherein the switch selection circuit comprises a first capacitor, a second capacitor, a third capacitor, a first high gain switch, a first low gain switch, and a second low gain switch;

the first terminal of the first high-gain switch and the first terminal of the first low-gain switch are commonly used as a high-gain image signal input terminal of the switch selection circuit, a high-gain reset signal input terminal of the switch selection circuit, a low-gain image signal input terminal of the switch selection circuit and a low-gain reset signal input terminal of the switch selection circuit, the second end of the first low-gain switch is connected with the first end of the third capacitor, the first end of the second capacitor is connected with the ramp voltage, a second terminal of the third capacitor and a second terminal of the second capacitor are connected to the first node, the second end of the first high-gain switch is connected with the first end of the first capacitor, the first end of the second low-gain switch is connected with the reference voltage, the second end of the first capacitor and the second end of the second low-gain switch are connected to the second node in common.

6. The image sensor readout circuit of claim 5, wherein the second capacitance and the third capacitance are both variable capacitances.

7. The image sensor readout circuit of claim 5, wherein the switch selection circuit further comprises a second high-gain switch;

the first end of the second high-gain switch is connected to the ramp voltage, and the second end of the second high-gain switch is connected with the first end of the third capacitor.

8. The image sensor readout circuit of claim 1, wherein the reference voltage is adjustable.

9. The image sensor readout circuit of claim 1, wherein a slope of the ramp voltage is adjustable.

10. An image sensor, comprising:

a pixel circuit configured to sequentially output a high-gain reset signal, a high-gain image signal, a low-gain image signal, and a low-gain reset signal; and

a readout circuit of an image sensor according to any of claims 1 to 9.

11. An electronic device characterized by comprising the image sensor of claim 10.

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