CN1153289C - Low leakage current electrostatic discharge protection circuit - Google Patents

Abstract

The invention provides an electrostatic discharge protection circuit, which is suitable for being used between a high power line and a low power line. The ESD protection circuit includes a diode string circuit. The diode serial circuit is formed by at least one Schottky diode in forward serial connection, and comprises an anode and a cathode which are respectively coupled with the high power line and the low power line during an electrostatic discharge event. The electrostatic discharge protection circuit can reduce the leakage current in normal operation and can save the consumption area of the chip.

Description

The electrostatic storage deflection (ESD) protection circuit of low-leakage current

Technical field

The invention relates to static discharge between a kind of power line (electrostaticdischarge, ESD) protective circuit, refer to especially a kind of when the integrated circuit operate as normal, the low-down esd protection circuit of leakage current.

Background technology

Along with the progress of CMOS processing procedure, in the CMOS integrated circuit, ESD has been a very serious problem on the reliability.Especially enter the epoch of deep-submicron when processing procedure, no matter be that to wait comparatively advanced processing procedure all be ability to bear at reduction ESD for thin gate oxide (thinner gate oxide), short channel length (shorterchannel 1ength), more shallow junction depth (shallow junction depth) and self-aligning metallization silicon method (salicide).Therefore, just must design esd protection circuit especially on each input port (inputport) and output port (output port)., just all at last input port and all appropriate protection of output port are found to also that some electronic building brick can be subjected to the ESD infringement in the internal circuit in esd event.

Because the static that integrated circuit suffered from is unknowable, may be that positive electricity also may be negative electricity, and, static can enter from the I/O port of which integrated circuit on earth and flow out from the I/O port of which integrated circuit, and these all are unknown, so, just must be one group with the I/O port of per two integrated circuits in theory, carry out the ESD test, all tested, we can say that just this integrated circuit meets the demand of ESD by ESD up to all possible combination.See also Fig. 1, when Fig. 1 is a kind of esd event, to the reason of internal circuit damage, and, add the schematic diagram of the protection philosophy behind the esd protection circuit between power line.When the ESD of positive voltage electric current enters and will see through an output port 14 and flow out the time from an input port 12, it is as the first discharge path I among Fig. 1 that a kind of possible discharge path is arranged, strangulation diode 16 to high power line (relatively-high power rail) VDD18 in the electric current elder generation input port 12 of flowing through forward of ESD, then seek assembly fragile in the internal circuit 20 and destroyed and flow to low power line (relatively-low power rail) VSS22, the PN junction of nMOS24 is to the earth point of output port 14 in the last output port 14 of flowing through forward, thereby emits the ESD electric current.That is to say that even if all output ports and input port are all carried out the esd protection measure, internal circuit 20 still might cause the ESD infringement through the discharge process as first discharge path.Therefore; if in high power line VDD18 and low power line VSS22, add esd protection circuit 26; and just conducting automatically of esd protection circuit 26 when the voltage on the high power line VDD18 is not high enough to destroy internal circuit 20 as yet; make the ESD electric current from high power line VDD18 process esd protection circuit 26 and to low power line VSS22; as the second discharge path II among Fig. 1, just then internal circuit 20 is damaged by ESD can.So the esd protection circuit between power line is very important.

Esd protection circuit is to be coupled in two power lines with a diode sequential circuit 30 purely to be constituted between a kind of existing power line, shown in Fig. 2 A and shown in Fig. 2 B.Diode sequential circuit 30 only with a plurality of diodes 32 forward be connected in series constituted, when blocking voltage (block voltage) that the pressure reduction of two power supplys forms greater than more than one diode 32, diode sequential circuit 30 is with regard to conducting.Generally speaking, diode 32 is p type doped region (p-type-doped region) the 36 formed PN junction diodes with n type trap (n-well) 34 and Qi Nei, shown in Fig. 2 B.Just, the pnp transistor that often has a parasitism can be formed by p type substrate in the semiconductor chip 38, a n type trap 34 and a p type doped region 36.Because p type substrate 38 mostly is to be coupled in low power line VSS22, is a kind of Darlington (Darlington) circuit of multilayer level so esd protection circuit can be seen, shown in Fig. 2 C.Some formula of having delivered on paper arrangements are as follows:

V _string(I)＝mV _D(I)-nV _T×[m(m-1)/2]×ln(β+1)------(1)

V _D(I)＝nV _T×ln[I/AI _S] ------(2)

$I_D=A{I}_S[e^{V/n{V}_T}-1]---\left(3\right)$

$V_D\left(T_1\right)=n{E}_{g0}+\left(\frac{T_1}{T_0}\right)\×(V_D\left(T_0\right)-\frac{n{E}_{g0}}{q})---\left(4\right)$

Wherein

V _StringTotal cross-pressure of=diode sequential circuit;

V _DThe forward bias of=one PN junction diode;

I _DThe forward current of=one PN junction diode;

V _T=KT/q is called thermal voltage (thermal voltage);

N=desirability figure;

The transistorized current gain of the pnp of β=parasitism;

I _SThe saturation current of the PN junction diode of=unit are;

The area of A=one a PN junction diode;

The number of the PN junction diode of m=serial connection; And

E _G0=when 0 ° of K, the extrapolation band gap width=1.206eV of silicon

By in Fig. 2 B and the 1st formula as can be known, very approaching zero as β, electric current can flow to p type substrate 38 hardly, so the electric current that each PN junction diode is flowed through is about equally, so each PN junction diode can provide an about identical pressure drop.And can increase the PN junction number of diodes of serial connection along with the demand of design, the blocking voltage (block voltage) between high power line VDD18 and low power line VSS22 is increased.But along with the progress of processing procedure, n type trap 34 is more and more shallow, so β is increasing.And equal 1 even when bigger as β, and a large amount of electric currents can be flowed through p type substrate 38 to low power line VSS22, causes the electric current that obtains the closer to the PN junction diode of low power line VSS22 just more little, and therefore, the pressure drop that provides is just relative just little.This means that when β becomes big the number of PN junction diode must increase the blocking voltage (block voltage) that just can reach identical.And, the problem of leaking electricity when the greatest problem of diode sequential circuit 30 is operate as normal.In case it is big that β becomes, can provide a high power line VDD18 leakage path just be connected on first parasitic pnp transistor of high power line VDD18, shown in Fig. 2 B to low power line VSS22.And when the cross-pressure between high power line VDD18 and the low power line VSS22 increased, leakage current was to increase along with cross-pressure changes and is index, shown in the 3rd formula.This just means must be connected in series the loss of just bigger chip area, the leakage current in the time of could lowering operate as normal with more PN junction diode.

Leakage current when the problem of another diode sequential circuit 30 is operate as normal can increase along with the rising of temperature, and such temperature effect can be found out from the 4th formula.In the 4th formula, V _DTemperature coefficient bear because nE _G0/ q (=1.206V) greater than the V under the room temperature state _D(when forward current is 1 ~ 10 μ A, be approximately 0.55 ~ 0.65V).So when high temperature, more PN junction diode serial connection must be arranged just, just can reach identical blocking voltage.

There have been many kinds to solve the method for the leakage problem of diode sequential circuit 30, list three kinds of prior aries at this, be called clad type diode sequential circuit (cladded diodestring) 40, elect formula diode sequential circuit (boosted diode string) 42 and cantilever type diode sequential circuit (cantilever diode string) 44, shown in Fig. 3 A to Fig. 3 C.

Blocking voltage is not with the reason that the number of the PN junction diode that is connected in series is directly proportional that the electric current received the closer to the PN junction diode of low power line VSS 22 is more little, so the bias voltage that provides also just and then diminishes.Therefore, the PN junction diode that electric current directly is directed to close low power line VSS22 just can improve blocking voltage, and clad type diode sequential circuit 40 as shown in Figure 3A, is a kind of embodiment of this idea.M1 and M2 are the pMOS transistors of two series connection, are used as the resistance of two series connection, directly are directed near the PN junction diode that hangs down power line VSS22 in order to the electric current with high power line VDD18.The grid of M1 and M2 all arrives low power line VSS22 with the nMOS diode-coupled of a M3, guarantees that M1 and M2 can both be operated in three polar regions (triode region) and be used as resistance.

Shown in Fig. 3 B, elect formula diode sequential circuit 42 and also be to use the notion the same with clad type diode sequential circuit 40.Election formula diode sequential circuit 42 directly is directed to the electric current of high power line VDD18 the PN junction diode of close low power line VSS22 with the nMOS transistor of a M3.The grid of M3 then is the pMOS diode with two series connection, M1 and M2, and formed dividing potential drop is as bias voltage.During normal temperature, M3 is biased in closing state, when high temperature, the source voltage of M3 can descend because the bias voltage of PN junction diode reduces, so M3 understands the unlatching of a little, the PN junction diode of the electric current that guides high power line VDD18 to the source electrode of M3 used the bias voltage that improves the PN junction diode.So the blocking voltage of the formula of election diode sequential circuit 42 can be comparatively stable.

Cantilever type diode sequential circuit 44 shown in Fig. 3 C, has also used and clad type diode sequential circuit 40 about identical notions.But cantilever type diode sequential circuit 44 mainly is to have added a M1 who constitutes with the pMOS transistor as switch, and M1 only just opens when esd event takes place, and then closes when operate as normal.So during operate as normal, no matter how many operating ambient temperatures is, the PN junction diode is disconnected to the path of low power line VSS22.And in order to distinguish esd event and normal operative condition, the grid voltage that the RC circuit then provides M1 that formed that the M2 that constitutes with a pMOS is connected in series with a capacitor C, when esd event takes place in high power line VDD18, the higher power line VDD18 that the grid voltage of M1 rises is slow, so triggered M1 and opened the path of PN junction diode to low power line VSS22.

Yet, the circuit among Fig. 2 B, 3A, 3B and Fig. 3 C all be framework at the formed PN junction diode of the p type doped region of a n type trap and Qi Nei, therefore, all be difficult to avoid the parasitic too big problem of the transistorized currentgain value of pnp.As long as the parasitic transistorized currentgain value of pnp is too big, just there are many again auxiliary circuits that electric current is directed to than near low power line VSS22 at last, of no avail.

Summary of the invention

In view of this, purpose of the present invention is to provide a kind of ESD protection circuit of low-leakage current.The present invention is the transistorized currentgain of the reduction parasitism of good fortune greatly, so can significantly reduce leakage current.

Purpose of the present invention can reach by following measure:

A kind of electrostatic storage deflection (ESD) protection circuit of low-leakage current is applicable to that this electrostatic storage deflection (ESD) protection circuit includes between a high power line and the low power line:

One diode sequential circuit, with a plurality of diodes that comprise at least one Schottky diode forward be connected in series constituted, it includes an anodal and negative pole, be coupled in respectively this high power line with should low power line.

A kind of electrostatic storage deflection (ESD) protection circuit of low-leakage current is applicable to that this electrostatic storage deflection (ESD) protection circuit includes between a high power line and the low power line:

One first conduction type substrate;

The second most conductive type of trap is located at the surface of this first conduction type substrate, includes the Schottky diode that a metal and the formed knot of this second conductive type of trap are constituted in each second conductive type of trap; And

Most connecting circuits, with so that Schottky diode that should majority forward be connected in series to form a diode sequential circuit that contains an anodal and negative pole;

Wherein, this positive pole and this negative pole are to be coupled in this high power supply respectively and should to hang down power line.

The present invention has following advantage compared to existing technology:

According to above-mentioned purpose, the present invention proposes a kind of electrostatic storage deflection (ESD) protection circuit, is applicable between a high power line (relatively-high power rail) and the low power line (relatively-low power rail).This electrostatic storage deflection (ESD) protection circuit includes diode serial connection (diode string) circuit.This diode serial connection (diode string) circuit with several diodes that comprise at least one Schottky (schottky diode) diode forward be connected in series constituted, it includes an anodal and negative pole, is coupled in this high power line respectively and should hangs down power line.

The present invention provides a kind of electrostatic storage deflection (ESD) protection circuit in addition, be applicable to that this electrostatic storage deflection (ESD) protection circuit includes one first conduction type substrate, a plurality of second conductive type of trap and a plurality of connecting circuits between a high power line (relatively-high power rail) and the low power line (relatively-lowpower rail).These a plurality of second conductive type of trap are located at the surface of this first conduction type substrate, include the Schottky diode that a metal and the formed knot of this second conductive type of trap are constituted in each second conductive type of trap.A plurality of connecting circuit with so that this a plurality of Schottky diode forward be connected in series to form a diode sequential circuit that contains a positive pole and a negative pole.Wherein, this positive pole and this negative pole are to be coupled in this high power supply respectively and should to hang down power line.

When the invention has the advantages that operate as normal, the leakage current of ESD protection circuit of the present invention is very little.Because the diode in the ESD protection circuit of the present invention is constituted with Schottky diode, and the currentgain of the bipolar transistor of Schottky diode and the formed parasitism of the first conduction type substrate can be very little, therefore, current ratio more can not flowed through the first conduction type substrate and be arrived low power line, so the leakage current of ESD protection circuit of the present invention is very little.

Description of drawings

For above-mentioned purpose of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. are described in detail below:

When Fig. 1 is a kind of esd event, to the reason of internal circuit damage, and, add the schematic diagram of the protection philosophy behind the esd protection circuit between power line;

Fig. 2 A and Fig. 2 B are respectively the circuit diagram and the chip profile figure of existing a kind of esd protection circuit that purely constitutes with a diode sequential circuit;

Fig. 2 C is the equivalent circuit diagram of Fig. 2 B;

Fig. 3 A, Fig. 3 B and Fig. 3 C are respectively existing clad type diode sequential circuit, elect the circuit diagram of formula diode sequential circuit and cantilever type diode sequential circuit;

Fig. 4 A is the circuit diagram of ESD protection circuit of the present invention;

Fig. 4 B is the chip profile schematic diagram of the circuit of enforcement Fig. 4 A;

Fig. 5 A is that a pnp is transistorized in penetrating the every electric current component-part diagram of base knot forward bias forward bias when collecting base knot reverse biased;

Fig. 5 B is transistorized in penetrating the every electric current component-part diagram of base knot forward bias when collecting base knot reverse biased for Al-n-p among the present invention; And

Fig. 6 A to Fig. 6 C applies to the circuit diagram of clad type diode sequential circuit, election formula diode sequential circuit and cantilever type diode sequential circuit for the present invention.

Symbol description

50 electrostatic storage deflection (ESD) protection circuit, 52 high power line VDD

54 low power line VSS 56 positive poles

The 60 p type substrates of 58 negative poles

62 n type traps, 66 metals

10 ESD voltage sources, 12 input ports

14 output ports, 16 clamp diodes

20 internal circuits, 24 NMOS

More than 32 diode of 30 diode series circuits

36 P type doped regions, 40 clad type diode sequential circuits

42 elect formula diode sequential circuit 44 cantilever type diode sequential circuits

The P1 first discharge path P2 second discharge path

I1 ESD electric current I leakage current

M1?PMOS M2?PMOS

M3?NMOS M4?PMOS

M5?NMOS

68 n type doped regions

Embodiment

See also Fig. 4 A, Fig. 4 A is the circuit diagram of ESD protection circuit of the present invention.The invention provides a kind of electrostatic storage deflection (ESD) protection circuit 50, be applicable between a high power line VDD52 and a low power line VSS54.Electrostatic storage deflection (ESD) protection circuit 50 includes diode serial connection (diode string) circuit, and with at least one Schottky (schottky diode) diode, as the D1 to Dn among Fig. 4 A, forward serial connection constitutes.The diode sequential circuit includes anodal 56 and one negative pole 58, when electrostatic discharge event, is coupled in high power line VDD52 and low power line VSS54 respectively.

See also Fig. 4 B, Fig. 4 B is the chip profile schematic diagram of the circuit of enforcement Fig. 4 A.In order can be made on the semiconductor chip, the electrostatic discharge protective circuit that is made on the semiconductor chip that the present invention provides in addition is shown in 4B.Electrostatic storage deflection (ESD) protection circuit includes a p type substrate 60, a plurality of n type trap 62 and a plurality of connecting circuits 64.A plurality of n type traps 62 is located at the surface of p type substrate 60, includes the Schottky diode (D1 to Dn) that a metal 66 and n type trap 62 formed knots are constituted in each n type trap 62.Also comprised a n type doped region (n-type-doped region) 68 in each n type trap 62, with electrical connection as each n type trap 62.A plurality of connecting circuit 64 usefulness so that a plurality of Schottky diodes (D1 to Dn) forward be connected in series to form a diode sequential circuit that contains anodal 56 and one negative pole 58.Wherein, when an electrostatic discharge event, positive pole 56 is to be coupled in high power line VDD52 and low power line VSS54 respectively with negative pole 58.

Metal 66 can be made of the metal of numerous species.Yet the most general material is exactly an aluminium.Silicon and aluminium can form an aluminium silicon and connect face, because the difference of work function (work function) forms ohmic contact or Schottky contacts as long as the impurity concentration of mixing in the control silicon just can make sial connect face.Generally speaking, aluminium and lightly doped (light1y-doped) n type silicon, n type trap for example, the formed face that connects can form Schottky contacts, has rectified action, so be called Schottky diode again.As for, aluminium and lightly doped p type silicon, lightly doped n type silicon or the formed face that connects of heavily doped n type silicon all can form ohmic contact.

Compared to existing ESD protection circuit, existing ESD protection circuit will produce a pnp transistor by a p type doped region 36, a n type trap 34 and a p type substrate 38 formed parasitisms, shown in Fig. 2 B.And relative, ESD protection circuit of the present invention will produce an Al-n-p transistor by a metal 66, a n type trap 62 and a p type substrate 60 formed parasitisms, shown in Fig. 4 B.When operate as normal, high power line VDD52 connects a high potential, and low power line VSS54 ground connection.So,, penetrate that Ji Jiejun presents forward bias and collection base knot all presents reverse biased no matter be the pnp transistor or the Al-n-p transistor of the present invention of prior art.See also Fig. 5 A, Fig. 5 A is that a pnp is transistorized in penetrating the every electric current component-part diagram of base knot forward bias when collecting base knot reverse biased.By learning in the basic electronics, the conducting of general pn knot is to utilize the diffusion of minority carrier (minority carrier) to reach.Therefore, when the pnp transistor presented bias voltage as Fig. 5 A, a large amount of holes in emitter-base bandgap grading (emitter) can be diffused into base stage (base), as the I on the figure _HEBElectric current shown in.If I _HEBIn the hole not by give compound (recombined) of base stage, then can be collected by the collection utmost point (collector), as the I on the figure _HBCElectric current shown in.And I _HBExpression is by the compound electric current that the hole produced, I _EEBWith I _EBCThen represent electronics by base stage under bias voltage respectively to emitter-base bandgap grading and the collection electric current that the utmost point produced.Under normal working bias voltage, I _EEBWith I _EBCCan ignore, and I _HBVery little.And the transistorized currentgain pnp of pnp is defined as follows

βpnp≡Ic/IB～I _hBC/I _hB --------(5)

By among Fig. 5 A as can be known, if base stage (the n type trap among Fig. 2 B just) is thin more, then β pnp will be increasing, even greater than 1.See also Fig. 5 B again, Fig. 5 B is transistorized in penetrating the every electric current component-part diagram of base knot forward bias when collecting base knot reverse biased for Al-n-p among the present invention.By in the basic electronics as can be known do not have because intrametallic hole almost be we can say, so the conducting of schottky junction is to utilize flowing of majority carrier (majority carrier) to reach.By among Fig. 5 B as can be known, the electric current I that is caused is moved in the hole _HEB, I _HBCAnd I _HBSuitable little in capital, and under the reverse bias base stage to the electronic current I of the collection utmost point _EBCAlso can be very little, have the electronic current I of base stage under the forward bias only to emitter-base bandgap grading _EEBCan be very big.So transistorized currentgain of Al-n-p _Al-n-pBe expressed as follows:

β _Al-n-p≡Ic/IB

＝(-I _hBC+I _eBC)/(-I _hB-I _eEB-I _eBC)

～(I _hBC-I _eBC)/I _eEB -------(6)

By formula (6) as can be known, β _Al-n-pBe to produce divided by a very big forward current, so β by two very little electric currents _Al-n-pWill be very approaching zero, that is to say that the Al-n-p transistor does not almost have current gain.Same proof, also can be by A.Y.C.Yu and E.H.Snow, " Minority Carrier Injection of Metal Silicon Contacts, " Solid State Electron, learn in 12 155 (1969), transistorized by the Al-n-p that aluminium/n type trap/substrate of p type is constituted | I _c/ I _E| maximum be about 10 ^-5Yet general pnp is transistorized | I _c/ I _E| maximum be about 1.Can significantly reduce currentgain so can find the present invention with the pn diode that Schottky diode has replaced prior art.Therefore, can not flow through p type substrate and to low power line Vss of electric current has caused very little very little that the leakage current of ESD protection circuit of the present invention under normal operating state can become.And; the starting voltage of Schottky diode also than pn diode come big; so; reach identical blocking voltage (block voltage); the quantity of the Schottky diode of series connection can the quantity more required than the pn diode be lacked; therefore, can save the chip area that electrostatic discharge protective circuit consumes again.That is to say that the present invention has two benefits, the little and saving area of leakage current.

Spirit of the present invention is to replace pn diode in existing diode serial connection (diodestring) circuit with Schottky diode.No matter and be pure diode sequential circuit, clad type diode sequential circuit, elect formula diode sequential circuit or cantilever type diode sequential circuit etc. and can use method of the present invention to be improved, shown in Fig. 6 A to Fig. 6 C.

Though the present invention discloses as above with a preferred embodiment; right its is not in order to limiting the present invention, anyly has the knack of this skill person, without departing from the spirit and scope of the present invention; when the change that can do a little and retouching, so protection scope of the present invention is as the criterion when looking appended claim protection range.

Claims (8)

1. the electrostatic storage deflection (ESD) protection circuit of a low-leakage current is characterized in that: be applicable to that this electrostatic storage deflection (ESD) protection circuit includes between a high power line and the low power line:

One diode sequential circuit, with a plurality of diodes that comprise at least one Schottky diode forward be connected in series constituted, it includes an anodal and negative pole, be coupled in respectively this high power line with should low power line.

2. the electrostatic storage deflection (ESD) protection circuit of low-leakage current as claimed in claim 1 is characterized in that: wherein each Schottky diode is constituted with aluminium silicon knot.

3. the electrostatic storage deflection (ESD) protection circuit of low-leakage current as claimed in claim 1, it is characterized in that: wherein each Schottky diode is constituted with aluminium and the formed knot of n type trap.

4. the electrostatic storage deflection (ESD) protection circuit of a low-leakage current is characterized in that: be applicable to that this electrostatic storage deflection (ESD) protection circuit includes between a high power line and the low power line:

One first conduction type substrate;

The second most conductive type of trap is located at the surface of this first conduction type substrate, includes the Schottky diode that a metal and the formed knot of this second conductive type of trap are constituted in each second conductive type of trap; And

Most connecting circuits, with so that Schottky diode that should majority forward be connected in series to form a diode sequential circuit that contains an anodal and negative pole;

Wherein, this positive pole and this negative pole are to be coupled in this high power supply respectively and should to hang down power line.

5. the electrostatic storage deflection (ESD) protection circuit of low-leakage current as claimed in claim 4, it is characterized in that: wherein, this first conduction type substrate is to be a P type substrate.

6. the electrostatic storage deflection (ESD) protection circuit of low-leakage current as claimed in claim 4, it is characterized in that: wherein, each second conductive type of trap is to be a n type trap.

7. the electrostatic storage deflection (ESD) protection circuit of low-leakage current as claimed in claim 4, it is characterized in that: wherein, each second conductive type of trap includes one second conduction type doped region in addition, with the electrical connection as each second conductive type of trap;

8. the electrostatic storage deflection (ESD) protection circuit of low-leakage current as claimed in claim 4, it is characterized in that: wherein, this metal is constituted with aluminium.

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