CN115328250A - A Low-Power CMOS Voltage Reference Source Based on DIBL Effect Compensation - Google Patents

Abstract

The invention discloses a low power consumption CMOS voltage reference source based on DIBL effect compensation, comprising a start-up circuit and a core branch, wherein the output end of the start-up circuit is connected with the input end of the core branch, and the core branch The output terminal of the circuit outputs a reference voltage, and in the core branch, a picoamp level current flows through a diode-connected active load to generate a reference voltage. The present invention does not require additional resistors, triodes, intrinsic transistors and other devices, the bias current is independently generated by the core branch and biased to other branches, the transistor adopts a smaller size, reduces the manufacturing cost and chip area, and the self-regulating circuit It can compensate for the DIBL effect of short-channel transistors, reduce the equivalent impedance of the output voltage to ground, achieve lower linear sensitivity, and achieve picowatt-level power consumption, which is very suitable for the application background of the Internet of Things.

Description

A Low Power CMOS Voltage Reference Source Based on DIBL Effect Compensation

technical field

The present invention relates to the technical field of voltage reference sources, in particular to a low-power CMOS voltage reference source based on DIBL effect compensation.

Background technique

Consuming very low energy in operation is critical. However, traditional bandgap voltage references are difficult to work with low power supply voltage and low power consumption, and it is difficult to integrate into smaller systems such as wearable smart devices. It is difficult to design a small-area sub-threshold voltage reference must do. The classic architecture of the sub-threshold CMOS voltage reference source generates a reference voltage for the picoampere-level current to flow through the active load, and the threshold voltage of CMOS has a negative temperature coefficient characteristic to effectively compensate the temperature coefficient. It is worth noting that in a typical energy harvesting system, the input power fluctuates greatly in different environments, and the output voltage of a micro system such as a sensor or an interface circuit will have a large deviation. The voltage reference chip of the above system needs to be able to cope with a relatively large Wide supply voltage range. Compared with conventional subthreshold voltage reference sources, a voltage reference source that can resist power supply voltage changes is more attractive for the above-mentioned emerging applications, and has become a research hotspot in academia and industry at home and abroad.

An academic paper titled "A 48pW, 0.34V, 0.019%/V LineSensitivity Self-Biased Subthreshold Voltage Reference With DIBL Effect Compensation" was published in the prior art, which was published in IEEE TCAS I (Journal of Circuits and Systems) in 2020. Its circuit structure is shown in Fig. 1.

The circuit structure proposed in Fig. 1 is composed of a voltage self-bias current generation circuit, a self-cascaded transistor output reference circuit and a DIBL effect compensation circuit. It uses two types of MOS transistors: the transistors with thicker gate lines are 5V transistors with high threshold voltage, and the ones with thinner gate lines are 1.8V transistors with low threshold NMOS and PMOS. Its working principle is: after V _DD rises, M5 generates current, and the leakage current biased to M6 is injected into the self-cascaded active loads M2 and M3 to form a reference voltage and then self-bias M1, and M1 generates the total circuit The required current, the reference voltage eventually tends to a stable value. The three transistors M10-M12, as a circuit based on DIBL effect compensation, absorb the current that is also positively related to the power supply change from the output branch, thereby eliminating the DIBL effect and improving linearity sensitivity. (Working in the power supply voltage range of 0.6V~1.8V and the temperature range of 0°C~100°C, the generated reference voltage V _REF is about 147.9mV, the linear sensitivity is 0.019%/V, and the area is 0.0332mm ² ).

In the above solution, the current source generation tube and the MOS tube of the core output branch need to be larger in size and occupy a larger chip area; to improve the linear adjustment rate, the use of additional op amps will increase the power consumption of the circuit, and the cascaded current The mirror structure is effective but will increase the minimum power supply voltage, which is not conducive to the application scenario of the Internet of Things; when eliminating the DIBL effect of short-channel transistors, it is necessary to increase the channel length of the transistor, or to improve the accuracy of DIBL effect compensation.

Contents of the invention

The invention provides a low power consumption CMOS voltage reference source based on DIBL effect compensation, which reduces the size of transistors and realizes lower chip area.

In order to solve the problems of the technologies described above, the technical solution of the present invention is as follows:

A low-power CMOS voltage reference source based on DIBL effect compensation, comprising a start-up circuit and a core branch, wherein the output of the start-up circuit is connected to the input of the core branch, and the output of the core branch The terminal outputs a reference voltage, and in the core branch, a picoamp level current flows through a diode-connected active load to generate a reference voltage.

Preferably, the startup circuit includes a MOS transistor M10, a MOS transistor M11, a MOS transistor M12, a MOS transistor M13, a MOS transistor M14, a MOS transistor M15, and a MOS transistor M16, wherein:

The source of the MOS transistor M10 is electrically connected to the gate of the MOS transistor M11 and the drain of the MOS transistor M12 respectively, and the gate of the MOS transistor M10 is electrically connected to the gate of the MOS transistor M12 and the output end of the core branch respectively, Both the drain of the MOS transistor M10 and the drain of the MOS transistor M11 are grounded;

The source of the MOS transistor M12 is electrically connected to the drain of the MOS transistor M13 and the gate of the MOS transistor M13 respectively, the source of the MOS transistor M13 is electrically connected to the drain of the MOS transistor M14 and the gate of the MOS transistor M14 respectively, and the MOS transistor The source of M14 is electrically connected to the drain of MOS transistor M15 and the gate of MOS transistor M15 respectively, the source of MOS transistor M15 is electrically connected to the drain of MOS transistor M16 and the gate of MOS transistor M16 respectively, and the gate of MOS transistor M16 The source is electrically connected to the input end of the core branch.

Preferably, the MOS transistor M10 and the MOS transistor M11 are NMOS transistors, and the MOS transistor M12 , the MOS transistor M13 , the MOS transistor M14 , the MOS transistor M15 and the MOS transistor M16 are all PMOS transistors.

Preferably, the core branch includes an active load, a current generator, a MOS transistor M3, a MOS transistor M4, a MOS transistor M5, a MOS transistor M6, and a MOS transistor Mc, wherein:

The output terminals of the start-up circuit are electrically connected to the source of the MOS transistor M5 and the source of the MOS transistor M6 respectively, the gate of the MOS transistor M5 is electrically connected to the gate of the source of the MOS transistor M6, and the drain of the MOS transistor M5 It is electrically connected to the source of the MOS transistor Mc, and the gate of the MOS transistor Mc is respectively electrically connected to the drain of the MOS transistor M6, the source of the MOS transistor M4, the gate of the MOS transistor M4, and the gate of the MOS transistor M3. The drain of Mc is electrically connected to the first port of the current generator, the second port of the current generator is respectively electrically connected to the drain of the MOS transistor M4, and the source of the MOS transistor M3, and the third port of the current generator is connected to the active The input terminal of the load is electrically connected, the output terminal of the active load and the drain of the MOS transistor M3 are both grounded, and the third port of the current generator serves as the output terminal of the core branch to output the reference voltage.

Preferably, the current generator is a MOS transistor M2, wherein the source of the MOS transistor M2 is electrically connected to the drain of the MOS transistor Mc as the first port of the current generator, and the gate of the MOS transistor M2 is used as the first port of the current generator. The second port is electrically connected to the drain of the MOS transistor M4 and the source of the MOS transistor M3, and the drain of the MOS transistor M2 is used as a third port of the current generator to be electrically connected to the input end of the active load.

Preferably, the active load is a MOS transistor M1, wherein the source of the MOS transistor M1 is electrically connected to the third port of the current generator and the gate of the MOS transistor M1 as an input terminal of the active load, and the gate of the MOS transistor M1 The drain is grounded as the output of the active load.

Preferably, the MOS transistor M1 , the MOS transistor M2 , the MOS transistor Mc, the MOS transistor M3 , the MOS transistor M4 and the MOS transistor M6 are all NMOS transistors, and the MOS transistor M5 is a PMOS transistor.

Preferably, a self-regulating branch is further included, the self-regulating branch is electrically connected to the core branch, and the self-regulating branch is used to weaken the DIBL effect of the MOS transistor M2.

Preferably, the self-regulating branch includes a MOS transistor M7, a MOS transistor M8 and a MOS transistor M9, wherein:

The source of the MOS transistor M7 is electrically connected to the source of the MOS transistor M5, the gate of the MOS transistor M7 is electrically connected to the source of the MOS transistor Mc and the gate of the MOS transistor M5, and the drain of the MOS transistor M7 is respectively connected to the MOS transistor M5. The source of M8, the gate of MOS transistor M8, and the gate of MOS transistor M9 are electrically connected, the drain of MOS transistor M8 and the drain of MOS transistor M9 are grounded, and the source of MOS transistor M9 is connected to the source of MOS transistor M1. electrical connection.

Preferably, the MOS transistor M7 is a PMOS transistor, and the MOS transistor M8 and the MOS transistor M9 are NMOS transistors.

Compared with the prior art, the beneficial effects of the technical solution of the present invention are:

The present invention does not require additional resistors, triodes, intrinsic tubes and other devices, the bias current is independently generated by the core branch and biased to other branches, the transistor adopts a smaller size, reduces manufacturing cost and chip area, and the self-regulating circuit It can compensate the DIBL effect of short-channel transistors, reduce the equivalent impedance of the output voltage to ground, achieve lower linear sensitivity, and achieve petawatt-level power consumption, which is well suited to the application background of the Internet of Things.

Description of drawings

FIG. 1 is a schematic structural diagram of a voltage reference circuit provided by the prior art.

FIG. 2 is a schematic structural diagram of a voltage reference circuit provided by Embodiment 1. FIG.

FIG. 3 is a schematic structural diagram of a voltage reference circuit provided by Embodiment 4. FIG.

Fig. 4 is a schematic diagram of the influence of the self-regulating branch on the current change rate.

FIG. 5 is a schematic diagram showing the influence of V _REF on temperature under different process angles.

FIG. 6 is a schematic diagram of the influence of V _REF by the power supply voltage under different process angles.

Detailed ways

The accompanying drawings are for illustrative purposes only and cannot be construed as limiting the patent;

In order to better illustrate this embodiment, some parts in the drawings will be omitted, enlarged or reduced, and do not represent the size of the actual product;

For those skilled in the art, it is understandable that some well-known structures and descriptions thereof may be omitted in the drawings.

The technical solutions of the present invention will be further described below in conjunction with the accompanying drawings and embodiments.

Example 1

A low-power CMOS voltage reference source based on DIBL effect compensation, as shown in Figure 2, includes a startup circuit and a core branch, wherein the output of the startup circuit is connected to the input of the core branch, so The output end of the core branch outputs a reference voltage, and in the core branch, a picoamp level current flows through a diode-connected active load to generate a reference voltage.

Example 2

On the basis of Embodiment 1, this embodiment continues to disclose the following content:

The startup circuit includes a MOS transistor M10, a MOS transistor M11, a MOS transistor M12, a MOS transistor M13, a MOS transistor M14, a MOS transistor M15 and a MOS transistor M16, wherein:

The source of the MOS transistor M10 is electrically connected to the gate of the MOS transistor M11 and the drain of the MOS transistor M12 respectively, and the gate of the MOS transistor M10 is electrically connected to the gate of the MOS transistor M12 and the output end of the core branch respectively, Both the drain of the MOS transistor M10 and the drain of the MOS transistor M11 are grounded;

The source of the MOS transistor M12 is electrically connected to the drain of the MOS transistor M13 and the gate of the MOS transistor M13 respectively, the source of the MOS transistor M13 is electrically connected to the drain of the MOS transistor M14 and the gate of the MOS transistor M14 respectively, and the MOS transistor The source of M14 is electrically connected to the drain of MOS transistor M15 and the gate of MOS transistor M15 respectively, the source of MOS transistor M15 is electrically connected to the drain of MOS transistor M16 and the gate of MOS transistor M16 respectively, and the gate of MOS transistor M16 The source is electrically connected to the input end of the core branch.

The MOS transistor M10 and the MOS transistor M11 are 1.8V NMOS transistors, and the MOS transistor M12 , MOS transistor M13 , MOS transistor M14 , MOS transistor M15 and MOS transistor M16 are all 1.8V PMOS transistors.

Example 3

On the basis of embodiment 1 and embodiment 2, this embodiment continues to disclose the following content:

The core branch includes an active load, a current generator, a MOS transistor M3, a MOS transistor M4, a MOS transistor M5, a MOS transistor M6 and a MOS transistor Mc, wherein:

The output terminals of the start-up circuit are electrically connected to the source of the MOS transistor M5 and the source of the MOS transistor M6 respectively, the gate of the MOS transistor M5 is electrically connected to the gate of the source of the MOS transistor M6, and the drain of the MOS transistor M5 It is electrically connected to the source of the MOS transistor Mc, and the gate of the MOS transistor Mc is respectively electrically connected to the drain of the MOS transistor M6, the source of the MOS transistor M4, the gate of the MOS transistor M4, and the gate of the MOS transistor M3. The drain of Mc is electrically connected to the first port of the current generator, the second port of the current generator is respectively electrically connected to the drain of the MOS transistor M4, and the source of the MOS transistor M3, and the third port of the current generator is connected to the active The input terminal of the load is electrically connected, the output terminal of the active load and the drain of the MOS transistor M3 are both grounded, and the third port of the current generator serves as the output terminal of the core branch to output the reference voltage.

The current generator is a MOS transistor M2, wherein the source of the MOS transistor M2 is electrically connected to the drain of the MOS transistor Mc as the first port of the current generator, and the gate of the MOS transistor M2 is used as the second port of the current generator It is electrically connected to the drain of the MOS transistor M4 and the source of the MOS transistor M3, and the drain of the MOS transistor M2 serves as the third port of the current generator and is electrically connected to the input end of the active load.

The active load is a MOS transistor M1, wherein the source of the MOS transistor M1 is electrically connected to the third port of the current generator and the gate of the MOS transistor M1 as an input terminal of the active load, and the drain of the MOS transistor M1 is used as an input terminal of the active load. The output of the active load is grounded.

The MOS transistor M1, MOS transistor M2, MOS transistor Mc and MOS transistor M4 are all 1.8V NMOS transistors, the MOS transistor M3 is a 5V NMOS transistor, and the MOS transistor M5 and MOS transistor M6 are 1.8V PMOS transistors.

Example 4

On the basis of embodiment 1, embodiment 2 and embodiment 3, this embodiment continues to disclose the following content:

As shown in FIG. 3 , a self-regulating branch is also included, the self-regulating branch is electrically connected to the core branch, and the self-regulating branch is used to weaken the DIBL effect of the MOS transistor M2.

The self-regulating branch includes a MOS transistor M7, a MOS transistor M8 and a MOS transistor M9, wherein:

The source of the MOS transistor M7 is electrically connected to the source of the MOS transistor M5, the gate of the MOS transistor M7 is electrically connected to the source of the MOS transistor Mc and the gate of the MOS transistor M5, and the drain of the MOS transistor M7 is respectively connected to the MOS transistor M5. The source of M8, the gate of MOS transistor M8, and the gate of MOS transistor M9 are electrically connected, the drain of MOS transistor M8 and the drain of MOS transistor M9 are grounded, and the source of MOS transistor M9 is connected to the source of MOS transistor M1. electrical connection.

The MOS transistor M7 is a 1.8V PMOS transistor, and the MOS transistor M8 and the MOS transistor M9 are 1.8V NMOS transistors.

In a specific embodiment, the voltage reference source provided in this embodiment can work at a power supply voltage of 600mV to 1.8V and a temperature range of -20°C to 125°C to generate a reference voltage of 147mV. The derivation process is as follows:

(1) Determination of current I and voltage reference REF:

Since all MOS transistors work in the subthreshold region, the subthreshold formula of the current is:

From (1) can get

As shown in Figure 3, MOS transistors M5 and M7 are current mirrors, M8 and M9 are current mirrors, and I _B is shunted into I _A and I _C , then the current can be expressed as:

_VB is obtained from the difference in threshold voltages of the self-biased cascade of M3 and M4:

Considering the body effect of the threshold voltages of M2 and M4, the body effect formula is as follows:

Assuming that the transistor sub-threshold factor n ₁ ≈n ₂ ≈n ₃ ≈n ₄ in the process, and the mobility of the NMOS transistors are equal, and combining (2)(4)(5), the voltage reference can be obtained:

(2) The working principle of the circuit proposed in the embodiment is: after the power supply is turned on, M5 is pulled down and turned on, and M2 is a current generator, which determines the current of the core branch and generates current self-bias for the other branches. The drain of M3 provides a bias voltage V _B slightly higher than the reference voltage, V _B biases M2 and gradually stabilizes, the picoamp level current I _B determined by M2 flows through the active load M1, and the gate-source voltage of M1 is the output reference voltage V _REF , eventually stabilizes.

In formulas (1)-(6), K ₌ W/L is the width-to-length ratio of the MOS transistor; α is the ratio of the current mirror; V _GS is the gate-source voltage of the MOS transistor; Current; V _TH is the threshold voltage of the MOS transistor; n is the _subthreshold slope factor; V _T is the thermal voltage; μ is the carrier mobility; C _OX is the gate oxide capacitance; Threshold; γ is the body effect coefficient, and β is the simplified body effect factor for the convenience of calculation; V _SB is the source lining potential difference;

In the above scheme, the following measures are adopted to improve the linear sensitivity:

(1) Mc in the circuit is a cascaded transistor, which protects the current source tube M2 from the interference of VDD.

(2) The self-regulating circuit is composed of two pairs of current mirrors, MP5 and MP7, MN8 and MN9. The purpose is to weaken the DIBL effect of the M2 tube, so that the current flowing through the active load M1 is not affected by VDD. The DIBL effect is that as the VDD rises, the drain-source voltage of the short-channel transistor in the subthreshold region will increase, and the current will increase with a positive coefficient. The current IB of the M2 tube under the influence of the DIBL effect can be expressed as:

I _B,DIBL ≈(1+m _PV ΔV _DD )·I _B,int (7)

Combining (2)(7), it can be obtained that I _A under the influence of the reference DIBL effect:

Recalling the linear sensitivity definition formula LS=ΔV _REF /(V _REF ·ΔV _DD ), reducing the linear sensitivity will reduce ΔV _REF , from (1):

In the formula (9), m _PV is the positive voltage coefficient; I _int is the original current not affected by the DIBL effect, combined with the analysis of the formula (9), if the current change rate R _chg = I If _max /I _min is close to 1, ΔV _REF of the expression (9) can be made close to 0, and better linear sensitivity can be achieved. Combined with formula (8), the current I _B with positive voltage coefficient generated by the current generator M2 is self-biased to another branch to have the same positive voltage coefficient I _C , so that the current I _A flowing through the active load tends to more stable. From (8), it can be concluded that the self-regulating circuit to be designed can satisfy [(K ₅ ·K ₈ -K ₇ ·K ₉ )· _mpv ·ΔV _DD ]/(K ₅ ·K ₈ )] the closer to 0, Adjust the width-to-length ratio of the current mirror to improve the accuracy of current replication, making the current change rate closer to 1, as shown in Figure 4.

The simulation results are as follows:

The current self-biased picowatt-level self-regulating CMOS voltage reference source has a minimum operating voltage of 0.6V, a power consumption of 353pW, a linear sensitivity as low as 0.014%/V, and an area of only 0.0019mm2. Under the simulation, the simulation results show that the linear sensitivity, power consumption, area and other aspects have been greatly improved.

(1) The influence of temperature changes on the reference voltage VREF, the simulation results are shown in Figure 5:

Figure 5 shows: under different process angles, when the temperature changes from -20°C to 125°C, the maximum variation range of VREF voltage is 2.7mV, and the minimum variation range is 1mV. It shows that the reference voltage is almost independent of temperature in every process corner.

(2) The influence of the power supply voltage on the reference voltage VREF, the simulation results are shown in Figure 6:

Figure 6 shows that under different process angles, when the power supply voltage is 0.6V-1.8V, the linear sensitivity is 0.014%/V, the maximum variation range of VREF voltage is 0.03mV, and the minimum variation range is 0.006mV. It shows that the reference voltage has a good ability to resist power supply voltage variation under each process angle.

The same or similar reference numerals correspond to the same or similar components;

The terms describing the positional relationship in the drawings are only for illustrative purposes and cannot be interpreted as limitations on this patent;

Apparently, the above-mentioned embodiments of the present invention are only examples for clearly illustrating the present invention, rather than limiting the implementation of the present invention. For those of ordinary skill in the art, other changes or changes in different forms can be made on the basis of the above description. It is not necessary and impossible to exhaustively list all the implementation manners here. All modifications, equivalent replacements and improvements made within the spirit and principles of the present invention shall be included within the protection scope of the claims of the present invention.

Claims (10)

1. a kind of low power consumption CMOS voltage reference source based on DIBL effect compensation, it is characterized in that, comprise start-up circuit and core branch, wherein, the output end of described start-up circuit is connected with the input end of described core branch, so The output end of the core branch outputs a reference voltage, and in the core branch, a picoamp level current flows through a diode-connected active load to generate a reference voltage. 2. The low-power CMOS voltage reference source based on DIBL effect compensation according to claim 1, wherein the start-up circuit comprises a MOS transistor M10, a MOS transistor M11, a MOS transistor M12, a MOS transistor M13, and a MOS transistor M14 , MOS tube M15 and MOS tube M16, wherein: The source of the MOS transistor M10 is electrically connected to the gate of the MOS transistor M11 and the drain of the MOS transistor M12 respectively, and the gate of the MOS transistor M10 is electrically connected to the gate of the MOS transistor M12 and the output end of the core branch respectively, Both the drain of the MOS transistor M10 and the drain of the MOS transistor M11 are grounded; The source of the MOS transistor M12 is electrically connected to the drain of the MOS transistor M13 and the gate of the MOS transistor M13 respectively, the source of the MOS transistor M13 is electrically connected to the drain of the MOS transistor M14 and the gate of the MOS transistor M14 respectively, and the MOS transistor The source of M14 is electrically connected to the drain of MOS transistor M15 and the gate of MOS transistor M15 respectively, the source of MOS transistor M15 is electrically connected to the drain of MOS transistor M16 and the gate of MOS transistor M16 respectively, and the gate of MOS transistor M16 The source is electrically connected to the input end of the core branch. 3. The low-power CMOS voltage reference source based on DIBL effect compensation according to claim 2, wherein the MOS transistor M10 and the MOS transistor M11 are NMOS transistors, the MOS transistor M12, the MOS transistor M13, the MOS transistor M14, and the MOS transistor M14. Both the tube M15 and the MOS tube M16 are PMOS tubes. 4. The low-power CMOS voltage reference source based on DIBL effect compensation according to claim 1, wherein the core branch includes an active load, a current generator, a MOS transistor M3, a MOS transistor M4, and a MOS transistor M5, MOS tube M6 and MOS tube Mc, wherein: The output terminals of the start-up circuit are electrically connected to the source of the MOS transistor M5 and the source of the MOS transistor M6 respectively, the gate of the MOS transistor M5 is electrically connected to the gate of the source of the MOS transistor M6, and the drain of the MOS transistor M5 It is electrically connected to the source of the MOS transistor Mc, and the gate of the MOS transistor Mc is respectively electrically connected to the drain of the MOS transistor M6, the source of the MOS transistor M4, the gate of the MOS transistor M4, and the gate of the MOS transistor M3. The drain of Mc is electrically connected to the first port of the current generator, the second port of the current generator is respectively electrically connected to the drain of the MOS transistor M4, and the source of the MOS transistor M3, and the third port of the current generator is connected to the active The input terminal of the load is electrically connected, the output terminal of the active load and the drain of the MOS transistor M3 are both grounded, and the third port of the current generator serves as the output terminal of the core branch to output the reference voltage. 5. The low-power CMOS voltage reference source based on DIBL effect compensation according to claim 4, wherein the current generator is a MOS transistor M2, wherein the source of the MOS transistor M2 is used as the first source of the current generator One port is electrically connected to the drain of MOS transistor Mc, the gate of MOS transistor M2 is used as a current generator, the second port is electrically connected to the drain of MOS transistor M4 and the source of MOS transistor M3, and the drain of MOS transistor M2 is used as The third port of the current generator is electrically connected with the input end of the active load. 6. The low-power CMOS voltage reference source based on DIBL effect compensation according to claim 5, wherein the active load is a MOS transistor M1, wherein the source of the MOS transistor M1 is used as the input of the active load The terminal is electrically connected with the third port of the current generator and the gate of the MOS transistor M1, and the drain of the MOS transistor M1 is grounded as the output end of the active load. 7. The low-power CMOS voltage reference source based on DIBL effect compensation according to claim 6, wherein the MOS transistor M1, the MOS transistor M2, the MOS transistor Mc, the MOS transistor M3, the MOS transistor M4 and the MOS transistor M6 is an NMOS transistor, and the MOS transistor M5 is a PMOS transistor. 8. The low-power CMOS voltage reference source based on DIBL effect compensation according to claim 7, further comprising a self-regulating branch, the self-regulating branch being electrically connected to the core branch, the The self-regulating branch is used to weaken the DIBL effect of the MOS transistor M2. 9. The low-power CMOS voltage reference source based on DIBL effect compensation according to claim 8, wherein the self-regulating branch includes a MOS transistor M7, a MOS transistor M8 and a MOS transistor M9, wherein: The source of the MOS transistor M7 is electrically connected to the source of the MOS transistor M5, the gate of the MOS transistor M7 is electrically connected to the source of the MOS transistor Mc and the gate of the MOS transistor M5, and the drain of the MOS transistor M7 is respectively connected to the MOS transistor M5. The source of M8, the gate of MOS transistor M8, and the gate of MOS transistor M9 are electrically connected, the drain of MOS transistor M8 and the drain of MOS transistor M9 are grounded, and the source of MOS transistor M9 is connected to the source of MOS transistor M1. electrical connection. 10. The low-power CMOS voltage reference source based on DIBL effect compensation according to claim 9, wherein the MOS transistor M7 is a PMOS transistor, and the MOS transistor M8 and MOS transistor M9 are NMOS transistors.

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