CN109375688B - A sub-threshold reference voltage generation circuit with ultra-low power consumption and low voltage and low temperature drift - Google Patents

Abstract

The invention provides a sub-threshold reference voltage generating circuit with ultra-low power consumption and low voltage and low temperature drift, which belongs to the technical field of power management. Including start-up circuit, current reference circuit, V _PTAT circuit, V _CTAT circuit. The function of the start-up circuit is to prevent zero current transmission. After the circuit works normally, first of all, use the core structure of the current reference, including the high-threshold MOS tube and the low-threshold MOS tube, to generate a nanoamp level reference current, using The current mirror provides bias for the V _PTAT circuit and the V _CTAT circuit. The voltage with a negative temperature coefficient is generated by using the gate-source voltage difference of MOS transistors with different threshold voltages, and at the same time, a voltage with a positive temperature coefficient is generated by using an unbalanced differential pair. Two voltages with different temperature coefficients are superimposed and compensated to generate a reference voltage. On the premise of realizing ultra-low power consumption and reducing the layout area, the present invention can complete the design indexes of low-voltage output and low-temperature drift.

Description

A sub-threshold reference voltage generation circuit with ultra-low power consumption and low voltage and low temperature drift

technical field

The invention belongs to the technical field of voltage management. Specifically, it relates to the design of a sub-threshold reference voltage generating circuit with ultra-low power consumption and low voltage and low temperature drift.

Background technique

With the development of artificial intelligence technology, wearable devices and implantable medical products have received widespread attention from consumers. Due to the limited size and capacity of batteries in wearable and implantable devices, how to reduce the power consumption of power management chips becomes very important. Among them, as one of the important modules in the chip, the main function of the voltage reference circuit is to provide an accurate voltage reference for subsequent circuits. Therefore, it is particularly critical to design a voltage reference with good performance. With the continuous advancement of integrated circuit manufacturing technology, the process feature size becomes smaller and smaller. This makes the research on chip power consumption pay more attention to the conduction characteristics of the sub-threshold region of the MOS transistor. Therefore, the voltage reference working in the subthreshold region has become a research hotspot in recent years.

The traditional sub-threshold reference voltage generation circuit is mainly realized by a single MOS tube. Due to the limitation of process deviation and self-compensation, it is not easy to achieve low temperature drift, especially under the constraints of power consumption, output voltage and power supply voltage. Subthreshold voltage references are difficult to meet all requirements. Therefore, how to complete the voltage reference with low output voltage, low temperature drift and ultra-low power consumption becomes the research focus of the present invention.

As shown in Figure 1, it is a typical sub-threshold reference voltage generation circuit in the prior art. In order to ensure that the MOS tube works in the sub-threshold region, generally speaking, the bias current I must be at the nanoamp level. First of all, it is necessary to understand the MOS tube. characteristics of working in the subthreshold region,

Among them, _ID represents the drain current of the MOS tube. μ=μ ₀ (T ₀ /T) ^m represents the electron mobility of the MOS transistor, T ₀ is the reference temperature, μ ₀ is the electron mobility at the reference temperature T ₀ , T represents the absolute temperature, m is the temperature index, C _OX =ε _OX /t _OX , which represents the gate oxide capacitance per unit area, ε _OX represents the oxide dielectric constant, t _OX is the thickness of the oxide layer, η is the slope factor of the sub-threshold region, which is related to the process, Under the standard sub-micron process, it is about 1.5. W and L represent the channel width and length respectively, K=W/L represents the width-to-length ratio of the MOS tube, V _T =k _B T/q represents the thermal voltage, where k _B is Boltzmann constant, q is the electron charge. V _GS is the gate-source voltage of the MOS transistor, V _th is the threshold voltage, and V _DS is the drain-source voltage of the MOS transistor. The characteristic current is I ₀ =μC _OX (η-1)V _T ² . In the actual circuit, the value of the drain-source voltage V _DS is greater than the value of the thermal voltage V _T , when V _DS ≥ 3V _T , the simplified current expression can be obtained:

Simplifying (2), we can get,

The traditional sub-threshold reference voltage uses a nanoampere bias current to make the tube work in the sub-threshold region. At the same time, the gate and drain of the tube are connected together to generate the reference voltage through the gate-source voltage, so:

_VREF = _VGS (4)

Due to the gate-source voltage expression, the first term of the threshold voltage has a negative temperature coefficient, and the second term has a positive temperature coefficient. The reference voltage is generated by voltage compensation with positive and negative temperature coefficients. However, although it is easier to obtain the reference voltage by this method, the threshold voltage values operating in the sub-threshold region are relatively large, resulting in a relatively large final output voltage. At the same time, the negative temperature coefficient can only be compensated by adjusting the current and K. However, it requires a large L value. If the size ratio is too large, the problem of mismatch is easy to occur. Moreover, this compensation method is not accurate, and is greatly affected by process and temperature.

As practical projects have higher and higher requirements for low voltage and precision, how to complete a simple and high-performance circuit architecture is particularly critical.

SUMMARY OF THE INVENTION

The purpose of the present invention is to overcome the problems of large output voltage and insufficient temperature characteristics in the existing sub-threshold voltage reference technology, and to provide a sub-threshold reference voltage generating circuit with ultra-low power consumption and low voltage and low temperature drift.

The technical scheme of the present invention is:

A sub-threshold reference voltage generating circuit with ultra-low power consumption, low voltage and low temperature drift, including a start-up circuit, a current reference circuit and two compensation circuits, one of the compensation circuits is a V _PTAT generator, and the other is a V _CTAT generator ; The output end of the start-up circuit is connected to the control end of the current reference circuit.

The current reference circuit includes a first PMOS transistor (MP1), a second PMOS transistor (MP2), a third PMOS transistor (MP3), a first NMOS transistor (MN1), a second NMOS transistor (MN2), and a third NMOS transistor (MN3) and the fourth NMOS transistor (MN4);

The drain of the first NMOS transistor (MN1) is connected to the gate and drain of the first PMOS transistor (MP1) and the gates of the second PMOS transistor (MP2) and the third PMOS transistor (MP3) as the current reference circuit. the control terminal, the gate of the first NMOS transistor is connected to the drain of the third PMOS transistor (MP3) and the drain of the third NMOS transistor (MN3);

The gate-drain of the second NMOS transistor (MN2) is shorted and connected to the drain of the second PMOS transistor (MP2) and the gate of the third NMOS transistor (MN3), and the source of the second NMOS transistor is connected to the gate-drain shorted The drain of the fourth NMOS transistor (MN4) and the source of the first NMOS transistor (MN1), the drain of the third NMOS transistor (MN3) is connected to the drain of the third PMOS transistor (MP3) and used as the current reference The circuit generates the output terminal of the reference current;

The sources of the third NMOS transistor (MN3) and the fourth NMOS transistor (MN4) are grounded, and the sources of the first PMOS transistor (MP1), the second PMOS transistor (MP2) and the third PMOS transistor (MP3) are connected to the power supply voltage;

The V _PTAT generator and the V _CTAT generator include a fourth PMOS transistor (MP4), a fifth PMOS transistor (MP5), a sixth PMOS transistor (MP6), a seventh PMOS transistor (MP7) and a fifth NMOS transistor (MN5) ), the sixth NMOS transistor (MN6), the seventh NMOS transistor (MN7) and the eighth NMOS transistor (MN8);

The gate-drain of the fifth NMOS transistor (MN5) is shorted and connected to the gate of the sixth NMOS transistor (MN6) and the drain of the fourth PMOS transistor (MP4), and the source of the fifth NMOS transistor is connected to the sixth NMOS transistor (MN6). ) of the drain and as the output end of the V _CTAT generator is connected to the input end of the V _PTAT generator, that is, the gate of the sixth PMOS tube (MP6);

The gate of the sixth PMOS transistor (MP6) is connected to the output end of the V _CTAT generator as the input terminal of the V _PTAT generator, and the source of the sixth PMOS transistor is connected to the drain of the fifth PMOS transistor (MP5) and the seventh Source of PMOS tube (MP7);

The gate-drain short circuit of the seventh PMOS transistor (MP7) is simultaneously connected to the drain of the eighth NMOS transistor (MN8) and serves as the reference voltage output terminal of the sub-threshold reference voltage generating circuit;

The gate-drain short circuit of the seventh NMOS transistor (MN7) is simultaneously connected to the gate of the eighth NMOS transistor (MN8), and the drain of the seventh NMOS transistor is connected to the drain of the sixth PMOS transistor (MP6);

The sources of the sixth NMOS transistor (MN6), the seventh NMOS transistor (MN7) and the eighth NMOS transistor (MN8) are grounded, and the sources of the fourth PMOS transistor (MP4) and the fifth PMOS transistor (MP5) are connected to the power supply voltage.

The startup circuit includes a ninth NMOS transistor (MS2), a tenth NMOS transistor (MS3), an eleventh NMOS transistor (MS4), a twelfth NMOS transistor (MC1) and an eighth PMOS transistor (MS1);

The gate of the eleventh NMOS transistor (MS4) is connected to the drain of the tenth NMOS transistor (MS3) and the gate of the twelfth NMOS transistor (MC1), and the drain of the eleventh NMOS transistor is connected to the eighth PMOS transistor The gate of (MS1) and the gate of the first PMOS transistor (MP1) whose gate-drain is short-circuited are used as the output end of the start-up circuit;

The gate-drain of the ninth NMOS transistor (MS2) is short-circuited and connected to the gate of the tenth NMOS transistor (MS3), and the drain of the ninth NMOS transistor is connected to the drain of the eighth PMOS transistor (MS1);

The sources of the ninth NMOS transistor (MS2), the tenth NMOS transistor (MS3) and the eleventh NMOS transistor (MS4) are grounded, the source and drain of the twelfth NMOS transistor (MC1) and the eighth PMOS transistor (MS1) ) source is connected to the power supply voltage.

The first PMOS tube (MP1), the second PMOS tube (MP2), the third PMOS tube (MP3), the fourth PMOS tube (MP4) and the fifth PMOS tube (MP5) have the same width to length ratio, and the fifth The width to length ratio of the NMOS transistor (MN5) and the sixth NMOS transistor (MN6) is 1:1, the width to length ratio of the sixth PMOS transistor (MP6) and the seventh PMOS transistor (MP7) is 1:2, and the seventh NMOS transistor (MN7) and the eighth NMOS transistor (MN8) have a width-to-length ratio of 4:3.

The third NMOS transistor (MN3) and the sixth NMOS transistor (MN6) are NMOS transistors with a standard voltage of 5.0V, and the standard voltage of all other MOS transistors is 1.8V.

All the tubes described work in the subthreshold region.

Advantages and beneficial effects of the present invention: all MOS transistors are used to work in the sub-threshold region, so that the present invention has a small output reference voltage value and small temperature drift under the premise of realizing ultra-low power consumption and low power supply voltage.

Description of drawings

FIG. 1 is a typical sub-threshold voltage generating circuit in the prior art.

FIG. 2 is a sub-threshold reference voltage generating circuit proposed by the present invention.

FIG. 3 is a sub-threshold reference voltage curve of low temperature drift finally obtained by the present invention.

Detailed ways:

The present invention will be further elaborated below in conjunction with the accompanying drawings.

The present invention proposes a novel sub-threshold reference voltage generating circuit that can be completed in a CMOS process, as shown in FIG. 2 . Including 4 parts, start-up circuit, current reference circuit and two compensation circuits, one is V _PTAT generator, the other is V _CTAT generator.

The startup circuit includes a ninth NMOS transistor MS2, a tenth NMOS transistor MS3, an eleventh NMOS transistor MS4, a twelfth NMOS transistor MC1 and an eighth PMOS transistor MS1 (see the description of the content of the invention for the specific connection relationship of the startup circuit). The twelfth NMOS transistor MC1 is used as a startup capacitor, and the eleventh NMOS transistor MS4 is used as a switch transistor. When the system is powered on, the initial voltage of the twelfth NMOS transistor MC1 as a startup capacitor is the power supply voltage, making the switch transistor tenth The gate potential of the first NMOS transistor MS4 is pulled up, the eleventh NMOS transistor MS4 is turned on, and the gate potential of the first PMOS transistor (MP1) is pulled down to make the circuit work normally. The mirror image of the PMOS transistor MS1 and the functions of the ninth NMOS transistor MS2 and the tenth NMOS transistor MS3 of the current mirror pull down the gate potential of the switching transistor, and the startup circuit is separated from the entire circuit.

As shown in FIG. 2, the current reference circuit includes: a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3 and a fourth NMOS transistor Pipe MN4 (for the specific connection relationship of the circuit, please refer to the description in the content of the invention). The first PMOS transistor MP1, the second PMOS transistor MP2 and the third PMOS transistor MP3 have the same aspect ratio, and the core circuit includes the second NMOS transistor MN2 and the fourth NMOS transistor MN4 with a standard voltage of 1.8V and a standard voltage of 5.0V The third NMOS transistor (MN3), its gate-source voltage has the following expression:

V _GS,MN3 =V _GS,MN2 +V _GS,MN4 (5)

Since the width-to-length ratio of the current mirror is the same, assuming that the flowing current is I _B , we can get:

C＝C_OX(η-1)，

得到的基准电流通过第三PMOS管MP3镜像给有源负载电路亦即补偿电路，该电路主要包括两个，一个是V_PTAT发生器，另一个是V_CTAT发生器。V_CTAT发生器包括第四PMOS管MP4、第五NMOS管MN5和第六NMOS管MN6，第五NMOS管MN5的栅漏短接并连接第六NMOS管MN6的栅极和第四PMOS管MP4的漏极，其源极连接第六NMOS管MN6的漏极并作为V_CTAT发生器的输出端连接V_PTAT发生器的输入端。Among them, the meaning of each letter is

C=C _OX (n-1),

The obtained reference current is mirrored to the active load circuit, that is, the compensation circuit, through the third PMOS transistor MP3. The circuit mainly includes two, one is a V _PTAT generator, and the other is a V _CTAT generator. The V _CTAT generator includes a fourth PMOS transistor MP4, a fifth NMOS transistor MN5 and a sixth NMOS transistor MN6. The gate-drain of the fifth NMOS transistor MN5 is short-circuited and connected to the gate of the sixth NMOS transistor MN6 and the fourth PMOS transistor MP4. The drain, the source of which is connected to the drain of the sixth NMOS transistor MN6, and the output terminal of the V _CTAT generator is connected to the input terminal of the V _PTAT generator.

The V _PTAT generator includes a fifth PMOS transistor MP5, a sixth PMOS transistor MP6 and a seventh PMOS transistor MP7, and a seventh NMOS transistor MN7 and an eighth NMOS transistor MN8. The gate of the sixth PMOS transistor MP6 is connected to the output terminal of the V _CTAT generator as the input terminal of the V _PTAT generator, and its source is connected to the drain of the fifth PMOS transistor MP5 and the source of the seventh PMOS transistor MP7.

The gate-drain short circuit of the seventh PMOS transistor MP7 is simultaneously connected to the drain of the eighth NMOS transistor MN8 and serves as the reference voltage output end of the sub-threshold reference voltage generating circuit. The sixth PMOS transistor MP6 and the seventh PMOS transistor MP7 form a For the unbalanced differential pair, the source stages are connected to each other and can generate a current with a positive temperature coefficient. The seventh NMOS transistor MN7 and the eighth NMOS transistor MN8 form a current mirror.

The specific implementation method is as follows: first, the current reference circuit generates a reference current. Since the first PMOS transistor MP1, the second PMOS transistor MP2, and the third PMOS transistor MP3 use the same aspect ratio, the current flowing through is _IB and provide bias current for both generators. The fifth NMOS transistor MN5 and the sixth NMOS transistor MN6 have different threshold voltages, the currents flowing through them are all I _B , and the same aspect ratio is selected to obtain the following expression:

where m=ηln(C _OX1 /C _OX2 ). The threshold voltage difference has a negative temperature coefficient, and although V _T has a positive temperature coefficient, it is still ultimately a negative temperature coefficient. The first term in this expression represents the threshold voltage difference between the sixth NMOS transistor MN6 and the fifth NMOS transistor MN5. Considering the benefit of the body effect of the fifth NMOS transistor MN5 is that it can reduce the voltage value of ΔV _TH , and at the same time, m is a negative value, and finally use the threshold voltage difference, consider the body effect, and use m to reduce the output of the negative temperature coefficient voltage. size. Then, as the input voltage of the positive temperature coefficient voltage generating module, in the V _PTAT generator, the ratio of the current flowing through the sixth PMOS transistor MP6 and the seventh PMOS transistor MP7 is the current mirror of the seventh NMOS transistor MN7 and the eighth NMOS transistor MN8 mirror ratio. The expression for the positive temperature coefficient can be obtained as

where n=ηln(K _MP7 K _MN7 /K _MP6 K _MN8 ). V _T has a positive temperature coefficient, and you end up with a voltage with a positive temperature coefficient. The positive and negative temperatures are compensated for each other to obtain the final reference voltage expression as follows:

V _REF =ΔV _TH +mV _T +nV _T (9)

The first term ΔV _TH of this expression is the threshold voltage difference with a negative temperature coefficient, and through the second term mV _T , not only the negative temperature coefficient voltage is compensated, but the output reference voltage is also reduced. The negative temperature coefficient voltage is compensated by adjusting the number of four tubes in the third term nV _T.

All MOS transistors in the present invention work in the sub-threshold region. Compared with the traditional sub-threshold voltage reference, while achieving ultra-low power consumption, as shown in Figure 3, a reference with low output voltage and low temperature drift is finally obtained. Voltage.

Claims (3)

1. The sub-threshold reference voltage generation circuit is characterized by comprising a starting circuit, a current reference circuit and two compensation circuits, wherein one compensation circuit is V_PTATGenerator, the other is V_CTATA generator; the output end of the starting circuit is connected with the control end of the current reference circuit;

the starting circuit comprises a ninth NMOS transistor (MS2), a tenth NMOS transistor (MS3), an eleventh NMOS transistor (MS4), a twelfth NMOS transistor (MC1) and an eighth PMOS transistor (MS 1);

the grid electrode of an eleventh NMOS tube (MS4) is connected to the drain electrode of the tenth NMOS tube (MS3) and the grid electrode of the twelfth NMOS tube (MC1), the drain electrode of the eleventh NMOS tube is connected to the grid electrode of the eighth PMOS tube (MS1) and the grid electrode of the first PMOS tube (MP1) with short-circuited grid electrode and drain electrodes and serves as the output end of the starting circuit;

the gate and the drain of the ninth NMOS transistor (MS2) are shorted and connected to the gate of the tenth NMOS transistor (MS3), and the drain of the ninth NMOS transistor is connected to the drain of the eighth PMOS transistor (MS 1);

the source electrodes of the ninth NMOS transistor (MS2), the tenth NMOS transistor (MS3) and the eleventh NMOS transistor (MS4) are grounded, and the source electrode and the drain electrode of the twelfth NMOS transistor (MC1) and the source electrode of the eighth PMOS transistor (MS1) are connected with the power supply voltage;

the current reference circuit comprises a first PMOS (P-channel metal oxide semiconductor) tube (MP1), a second PMOS tube (MP2), a third PMOS tube (MP3), a first NMOS tube (MN1), a second NMOS tube (MN2), a third NMOS tube (MN3) and a fourth NMOS tube (MN 4);

the drain electrode of the first NMOS transistor (MN1) is connected with the grid electrode and the drain electrode of the first PMOS transistor (MP1) and the grid electrodes of the second PMOS transistor (MP2) and the third PMOS transistor (MP3) to serve as the control end of the current reference circuit, and the grid electrode of the first NMOS transistor is connected with the drain electrode of the third PMOS transistor (MP3) and the drain electrode of the third NMOS transistor (MN 3);

the grid-drain short circuit of the second NMOS tube (MN2) is connected with the drain electrode of the second PMOS tube (MP2) and the grid electrode of the third NMOS tube (MN3), the source electrode of the second NMOS tube is connected with the drain electrode of the fourth NMOS tube (MN4) with the grid-drain short circuit and the source electrode of the first NMOS tube (MN1), and the drain electrode of the third NMOS tube (MN3) is connected with the drain electrode of the third PMOS tube (MP3) and serves as the output end of the current reference circuit for generating the reference current;

the source electrodes of the third NMOS transistor (MN3) and the fourth NMOS transistor (MN4) are grounded, and the source electrodes of the first PMOS transistor (MP1), the second PMOS transistor (MP2) and the third PMOS transistor (MP3) are connected with power supply voltage;

the V is_PTATGenerator and V_CTATThe generator comprises a fourth PMOS tube (MP4), a fifth PMOS tube (MP5), a sixth PMOS tube (MP6), a seventh PMOS tube (MP7), a fifth NMOS tube (MN5), a sixth NMOS tube (MN6), a seventh NMOS tube (MN7) and an eighth NMOS tube (MN 8);

the grid drain of the fifth NMOS transistor (MN5) is in short circuit and is connected with the grid of the sixth NMOS transistor (MN6) and the drain of the fourth PMOS transistor (MP4), and the source of the fifth NMOS transistor is connected with the drain of the sixth NMOS transistor (MN6) and is used as the V_CTATThe output end of the generator is connected with V_PTATThe input end of the generator is the grid electrode of a sixth PMOS tube (MP 6);

the grid electrode of the sixth PMOS tube (MP6) is taken as V_PTATThe input of the generator is connected to V_CTATThe source electrode of the sixth PMOS tube is connected to the drain electrode of the fifth PMOS tube (MP5) and the source electrode of the seventh PMOS tube (MP 7);

the gate-drain short circuit of the seventh PMOS tube (MP7) is simultaneously connected to the drain electrode of the eighth NMOS tube (MN8) and serves as the reference voltage output end of the sub-threshold reference voltage generation circuit;

the grid-drain short circuit of the seventh NMOS transistor (MN7) is connected to the grid electrode of the eighth NMOS transistor (MN8), and the drain electrode of the seventh NMOS transistor is connected to the drain electrode of the sixth PMOS transistor (MP 6);

the source electrodes of the sixth NMOS transistor (MN6), the seventh NMOS transistor (MN7) and the eighth NMOS transistor (MN8) are grounded, and the source electrodes of the fourth PMOS transistor (MP4) and the fifth PMOS transistor (MP5) are connected with power supply voltage;

all the MOS tubes work in a subthreshold region.

2. The sub-threshold voltage generation circuit of claim 1, wherein the width-to-length ratios of the first PMOS transistor (MP1), the second PMOS transistor (MP2), the third PMOS transistor (MP3), the fourth PMOS transistor (MP4) and the fifth PMOS transistor (MP5) are the same, and the width-to-length ratios of the fifth NMOS transistor (MN5) and the sixth NMOS transistor (MN6) are 1: 1, the width-length ratio of the sixth PMOS tube (MP6) to the seventh PMOS tube (MP7) is 1: 2, the width-to-length ratio of the seventh NMOS transistor (MN7) to the eighth NMOS transistor (MN8) is 4: 3.

3. the sub-threshold voltage generation circuit of any of claims 1 to 2, wherein the third NMOS transistor (MN3) and the sixth NMOS transistor (MN6) are NMOS transistors with a standard voltage of 5.0V, and the standard voltage of all the other MOS transistors is 1.8V.

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