CN206573970U - A kind of high PSRR whole CMOS reference voltage source - Google Patents

Abstract

The utility model discloses a full CMOS reference voltage source with high power supply rejection ratio, comprising a reference voltage source, the reference voltage source includes a start-up circuit, a current source circuit and a temperature compensation circuit; the output end of the start-up circuit is connected to the input end of the current source circuit, The output terminal of the current source circuit is connected to the input terminal of the temperature compensation circuit, and the output terminal of the temperature compensation circuit forms the output terminal of the whole reference voltage source. The utility model utilizes the working characteristic of the MOS tube working in the sub-threshold region to generate a reference current of nanoampere level, and adopts a cascode current mirror to suppress power supply noise. In addition, the utility model not only has the advantages of small chip area, low power consumption, which is only in the order of nanowatts; but also has the advantages of high power supply rejection ratio, low temperature drift coefficient and low power supply voltage adjustment rate, and does not use resistors, diodes and triodes, Compatible with the standard CMOS process, effectively reducing the layout area and reducing the production cost.

Description

A Full CMOS Reference Voltage Source with High Power Supply Rejection Ratio

technical field

The utility model relates to the technical field of integrated circuits, in particular to a full CMOS reference voltage source with high power supply rejection ratio.

Background technique

The reference voltage source is an important module in digital-analog hybrid circuits and analog hybrid circuits, and is often used in voltage management chips, digital-to-analog converters (DAC), analog-to-digital converters (ADC) and phase-locked loops (PLL), In circuits such as low-dropout linear regulators (LDOs), the voltage reference provides a DC reference voltage for the system. A high-precision, high-stability reference voltage source is a necessary unit for high-performance analog integrated circuits. In view of the advantages of low temperature coefficient, high power supply rejection ratio, and compatibility with standard CMOS processes, the CMOS reference voltage source circuit has been widely studied and applied. It provides a system that is affected by power supply voltage, process parameters and temperature changes. The performance of the DC voltage or current with little influence directly affects the accuracy and stability of the system.

With the further complexity of the integrated circuit system, higher precision and speed requirements are put forward for the basic modules of analog integrated circuits, such as ADC, DAC, LDO and other circuits, which makes the CMOS reference voltage source integrated on the chip more demanding. high demands. In addition, CMOS reference voltage sources need to meet different requirements such as low power supply voltage, high precision, low power consumption, high power supply rejection ratio (PSRR) and low voltage regulation ratio (LS) according to different applications. Therefore, it is of practical significance and practical value to study and design CMOS reference voltage sources with different circuit structures that meet different performance requirements.

Utility model content

The technical problem to be solved by the utility model is that the existing reference voltage source has large layout area, high power consumption, and relatively low power supply rejection, and provides a high power supply rejection ratio full CMOS reference voltage source.

In order to solve the above problems, the utility model is achieved through the following technical solutions:

A full CMOS reference voltage source with high power supply rejection ratio, including a reference voltage source, the reference voltage source includes a start-up circuit, a current source circuit and a temperature compensation circuit; the output end of the start-up circuit is connected to the input end of the current source circuit, and the The output terminal is connected to the input terminal of the temperature compensation circuit, and the output terminal of the temperature compensation circuit forms the output terminal of the entire reference voltage source;

Start the circuit to help the reference source get rid of the degeneracy bias point and enter the normal working state;

The current source circuit uses the working characteristics of the MOS tube in the sub-threshold area to generate a reference current of the nanoampere level; uses a cascode current mirror to suppress power supply noise; uses a MOS tube that works in the linear area to replace the traditional reference voltage source The resistor provides current bias for the reference voltage generating circuit;

The temperature compensation circuit uses different MOS transistors to form a gate-source voltage difference, and through mutual adjustment, a reference voltage independent of temperature is obtained.

In the above solution, the MOS transistors forming the gate-source voltage difference are 1.8V MOS transistors and 3.3V MOS transistors.

In the above solution, the start-up circuit includes PMOS transistors M ₁ , M ₂ , M ₃ , NMOS transistors M ₄ , M ₅ , and capacitor C ₁ ; the sources of PMOS transistors M ₁ and M ₃ are connected to the power supply VDD; the capacitor C _{1 The} lower plate and the sources of NMOS transistors M4 and _M5 are connected to ground GND; the gate and drain of PMOS transistor M1 are connected to the source of PMOS transistor _{M2 ;} the gate and drain of PMOS transistor _M2 , the gate of PMOS transistor M3, the gate _of NMOS transistor M4 are connected to the upper plate of capacitor _{C2 ;} the drains _of NMOS transistors M3 and M4 are connected to the gate of _{M5 ;} the gate of NMOS transistor _M5 The drain forms the output of the startup circuit and is connected to the input of the current source circuit.

In the above scheme, the current source circuit includes PMOS transistors M ₆ , M ₇ , M ₁₁ , M ₁₂ , M ₁₅ , M ₁₆ , and NMOS transistors M ₈ , M ₉ , M ₁₀ , M ₁₃ , M ₁₄ , M ₁₇ , M ₁₈ ; the sources of the PMOS transistors M ₆ , M ₁₁ and M ₁₅ are connected to the power supply VDD; the sources of the NMOS transistors M ₁₀ , M ₁₄ , and M ₁₈ are connected to the ground GND; the gate and drain of the PMOS transistor M ₆ , PMOS _The source electrode of the tube _M7 and the gates of the PMOS tubes M11 and _M15 are connected to form the first output end of the current source circuit and connected to the first input end of the temperature compensation circuit; the gate electrode of the PMOS tube _M7 and _The drain is connected to the drain of the NMOS transistor _M8 and the gates of the PMOS transistors M12 and _M16 to form the second output end of the current source circuit and is connected to the second input end of the temperature compensation circuit; the NMOS transistor _M8 The gate of the PMOS transistor M12 is connected to the drain _of the NMOS transistor _M13 , and the gate and drain of the NMOS transistor M13 are connected to form the input end of the current source circuit and connected to the output end of the start-up circuit; the source of the NMOS transistor _M8 is connected to the The drain of the NMOS transistor _M9 is connected; the grid of the NMOS transistor _M9 , the grid and the drain of the NMOS transistor _M14 are connected to the source of the NMOS transistor _M13 ; the source of the NMOS transistor _M9 is connected to the NMOS transistor M ₁₀ ; the gates of NMOS transistors M ₁₀ , M ₁₇ and M ₁₈ and the drain of NMOS transistor M ₁₇ are connected to the drain of PMOS transistor M ₁₆ ; the drain of PMOS transistor M ₁₁ is connected to the drain of PMOS transistor M _{12 The} source of the PMOS transistor _M15 is connected to the source of the PMOS transistor _M16 ; the source of the NMOS transistor M17 is connected to the drain of the NMOS transistor _M18 .

In the above solution, the temperature compensation circuit includes PMOS transistors M ₁₉ , M ₂₀ , NMOS transistors M ₂₁ , M ₂₂ , and capacitor C ₂ ; the source of the PMOS transistor M ₁₉ is connected to the power supply VDD; the source of the NMOS transistor M ₂₂ and the capacitor The lower plate of C ₂ is connected to ground GND; the gate of PMOS transistor M ₁₉ forms the first input end of the temperature compensation circuit and is connected with the first output end of the current source circuit; the drain of PMOS transistor M ₁₉ is connected to the PMOS transistor _The source of the M20 is connected; _the gate of the PMOS transistor M20 forms the second input end of the temperature compensation circuit and is connected with the second output end of the current source circuit; _the drain of the PMOS transistor M20 is connected to the NMOS transistor _M21 The drain is connected to the gate and the gate of the NMOS transistor _M22 ; the source of the NMOS transistor _M21 and the drain of the NMOS transistor _M22 are connected to the upper plate of the capacitor _C2 to form the output of the entire reference voltage source terminal V _ref .

Compared with the prior art, the utility model utilizes the working characteristic of the MOS transistor working in the sub-threshold region to generate a reference current of the nanoampere level, and uses a cascode current mirror to suppress power supply noise. In addition, the utility model not only has the advantages of small chip area, low power consumption, which is only in the order of nanowatts; but also has the advantages of high power supply rejection ratio, low temperature drift coefficient and low power supply voltage adjustment rate, and does not use resistors, diodes and triodes, Compatible with the standard CMOS process, effectively reducing the layout area and reducing the production cost.

Description of drawings

Figure 1 is a schematic diagram of a high power supply rejection ratio full CMOS reference voltage source.

detailed description

Below in conjunction with accompanying drawing and embodiment, describe the technical scheme of the utility model in detail:

A high power supply rejection ratio full CMOS reference voltage source, as shown in Figure 1, includes a start-up circuit, a current source and a temperature compensation circuit. The output terminal of the starting circuit is connected to the input terminal of the current source circuit, the output terminal of the current source circuit is connected to the input terminal of the temperature compensation circuit, and the output terminal of the temperature compensation circuit forms the output terminal V _ref of the entire reference voltage source.

The start-up circuit provides current when the reference voltage source is turned on, so that the reference voltage source gets rid of the degenerate bias point and enters a normal working state. In a preferred embodiment of the present invention, the start-up circuit includes PMOS transistors M ₁ , M ₂ , M ₃ , NMOS transistors M ₄ , M ₅ and capacitor C ₁ . Among them, the sources of M ₁ and M ₃ are connected to the power supply VDD; the lower plate of capacitor C ₁ and the sources of M ₄ and M ₅ are connected to the ground GND; the gate and drain of M ₁ are connected to the source of M _{2 The} gate and drain _{of M2} , the gates _of M3 and M4 are connected to the upper plate of capacitor C2 _; the drains of M3 and M4 are connected to the gate of _{M5 ; M5 The} drain _of M1 is connected to the gates of M8 and _M13 in the current source circuit, and the drains of M12 and _M13 .

The current source circuit utilizes the operating characteristics of the MOS tube operating in the sub-threshold region to generate current. A cascode current mirror is used to suppress power supply noise; a MOS tube operating in the linear region is used to replace the resistor in the traditional reference voltage source to provide current bias for the reference voltage generation circuit; in a preferred embodiment of the present invention, the nano The current source circuit includes PMOS transistors M ₆ , M ₇ , M ₁₁ , M ₁₂ , M ₁₅ , and M ₁₆ , and NMOS transistors M ₈ , M ₉ , M ₁₀ , M ₁₃ , M ₁₄ , M ₁₇ , and M ₁₈ . The sources of M ₆ , M ₁₁ , and M ₁₅ are connected to the power supply VDD; the sources of M ₁₀ , M ₁₄ , and M ₁₈ are connected to the ground GND; the gate and drain of M ₆ are connected to the source of M ₇ and M ₁₁ , the gate of M ₁₅ are connected, and connected to the gate of M ₁₉ in the temperature compensation circuit; the gate and drain of M ₇ are connected to the drain of M ₈ , the gates of M ₁₂ and M ₁₆ , and connected to To the gate of M ₂₀ in the temperature compensation circuit; the gate of M ₈ is connected to the drain of M ₁₂ , the gate and drain of M ₁₃ , and connected to the drain of M ₅ in the startup circuit; the source of M ₈ The pole is connected to the drain of M ₉ ; the gate of M ₉ , the gate and drain of M ₁₄ are connected to the source of M ₁₃ ; the source of M ₉ is connected to the drain of M ₁₀ ; M ₁₀ , The gates of M ₁₇ and M ₁₈ and the drain of M ₁₇ are connected to the drain of M ₁₆ ; the drain of M ₁₁ is connected to the source of M ₁₂ ; the drain of M ₁₅ is connected to the source of M ₁₆ ; The source of M ₁₇ is connected to the drain of M ₁₈ .

The temperature compensation circuit adopts the gate-source voltage difference of 1.8VMOS tube and 3.3VMOS tube, and through mutual adjustment, a reference voltage independent of temperature is obtained. In a preferred embodiment of the present invention, the temperature compensation circuit includes PMOS transistors M ₁₉ , M ₂₀ , NMOS transistors M ₂₁ , M ₂₂ and capacitor C ₂ . Among them, the source of M ₁₉ is connected to the power supply _{VDD ;} the source of M ₂₂ and the lower plate of capacitor C ₂ are connected to _the ground _GND ; The gate, the drain of _M6 , and the source of M7 are connected; _the drain of M19 is connected with _the source of M20 _{; the} gate _of M20 is connected with _M7 , M12, and _M16 in the current source circuit The gate of M ₇ and the drain of M ₈ are connected; the drain of M ₂₀ is connected with the drain and gate of M ₂₁ and the gate of M ₂₂ ; the source of M ₂₁ and the drain of M ₂₂ are connected with The upper plates of the capacitor C ₂ are connected together and connected to the output terminal V _ref .

The working principle of the utility model is:

In the start-up circuit, when the power supply voltage VDD starts to rise from zero, because the gates of M ₁ and M ₂ are at low level, and their sources are at the power supply voltage VDD, so M ₁ and M ₂ are turned on. At this time, C1 is charged, and M _3. M ₄ forms an inverter, the gate of M ₅ is at high level, M ₅ is turned on, and a starting current is given to the current source circuit, forcing the circuit to break away from the degeneracy point; until VDD rises to V _TH , the gate of inverter M ₅ Extremely low level, finally M5 _cuts off, the start-up circuit and the core circuit are separated, and the entire start-up process is completed. After that, _M5 is always in the cut-off state, with no static current and no power consumption.

The current source circuit is composed of MOS tubes M ₆ , M ₇ , M ₈ , M ₉ , M ₁₀ , M ₁₁ , M ₁₂ , M ₁₃ , M ₁₄ , M ₁₅ , M ₁₆ , M ₁₇ and M ₁₈ , where M ₆ , M ₇ , M ₁₁ , M ₁₂ , M ₁₅ and M ₁₆ constitute three pairs of cascode current mirrors, which function as mirror currents; they are the power supply rejection ratio of the reference voltage source, and adopt a cascode structure; they work in the subthreshold region The IV characteristics of the MOS tube can be expressed as:

In the formula, I _D is the drain current of the MOS tube; K=W/I is the width-to-length ratio of the MOS tube; I ₀ is the characteristic current, μ=μ ₀ (T ₀ /T) ^m is the electron mobility of the MOS tube, T ₀ is the reference temperature, μ ₀ is the electron mobility at the reference temperature T ₀ , T is the absolute temperature, m is the temperature index, C _OX = ε _OX /t _OX is the capacitance of the gate oxide layer, where ε _OX is the dielectric constant of the oxide, t _OX is the thickness of the oxide layer, η is the slope factor of the subthreshold region, V _GS is the gate-source voltage of the MOS transistor, and V _T =k _B T/q is the thermal voltage, k _B is the Boltzmann constant, q is the electronic charge, V _TH represents the threshold voltage of the MOS tube, and V _DS represents the drain-source voltage of the MOS tube.

When V _DS >3V _T , the influence of V _DS on I _D can be ignored, so the simplified expression is:

Further get the gate-source voltage of the MOS transistor:

η depends on the capacitance of the gate oxide layer and the loss layer, and now η is assumed to be a constant.

V _GSi is the gate-source voltage of the MOS transistor _Mi , V _DSi is the drain-source voltage of the MOS transistor Mi, V _THi is the threshold voltage of the MOS transistor _{Mi, and K i is the} width-to-length ratio of the MOS transistor _Mi.

Both M ₉ and M ₁₄ work in the sub-threshold region, and the gates of the two MOS transistors are connected together with the same potential, but the source potentials are not equal, so the potential difference between the sources of M ₉ and M ₁₄ is equal to the drain-source of M ₁₀ voltage V _DS10 , so the drain-source voltage V _DS10 of M ₁₀ is expressed as:

M ₁₀ works in the linear region, and the IV characteristic curve of M ₁₀ can be expressed as:

neglect The effect of , again expressed as:

I _P ＝I _D10 ＝β[(V _A -V _TH )V _DS10 ] (6)

In the formula, I _P is the output current of the current source circuit, β=μC _OX K ₁₀ , μ(μ=μ ₀ (T ₀ /T) ^m ) is the electron mobility, m is the temperature index, and C _OX is the gate oxide layer Capacitance, K ₁₀ is the width-to-length ratio of M ₁₀ , ID10 is the drain current of M ₁₀ , V _TH is the threshold voltage, V _TH = V _{TH0 -κT} , V _TH0 represents the threshold voltage value when the absolute temperature is 0K, κ is the temperature coefficient of _VTH . The temperature coefficient of current I _P It can be expressed as:

In the circuit, the bias voltage V _A =V _GS18 ; M ₁₀ works in the saturation region, so V _GS18 can be expressed as:

I _D18 = QIP ₌ I _D10 (9)

In the formula, Q is the ratio of the leakage current of M ₁₈ and M ₁₀ in the circuit. According to formulas (7) and (8), TC _I in the current source circuit can finally be expressed as:

Since the value of the temperature index m is about 1.5 and the value of TC _I is very small, the output current IP of the current _source shows good temperature characteristics, which can provide a stable bias current for the temperature compensation circuit and drive it to work normally .

Referring to Fig. 1, the temperature compensation circuit is composed of MOS transistors M ₁₉ -M ₂₂ working in the sub-threshold region. M ₁₉ , M ₂₀ and M ₁₅ , M ₁₆ in the current source circuit form a cascode current mirror structure, which can mirror the current from the current source circuit; use the gates of 1.8VMOS transistors and 3.3VMOS transistors working in the subthreshold region Source voltage difference, to obtain a reference voltage with zero temperature drift; M ₂₁ and M ₂₂ tubes are the core circuits of temperature compensation, both of which work in the sub-threshold region; referring to Figure 1, the expression of the output reference voltage V _ref can be obtained as:

V _ref =V _GS22 -V _GS21 (11)

Using the IV characteristics of the MOS transistor working in the subthreshold region, the expression of the output voltage V _ref can be obtained:

In the formula, t _OX,i represents the thickness of the gate oxide layer of the MOS transistor M _i , and △V _TH represents the difference between the threshold voltages of the MOS transistors M ₂₂ and M ₂₁ ; the expression of the threshold voltage is:

V _TH =V _TH0 -κT (13)

Therefore, △V _TH has a negative temperature coefficient; and by adjusting V _ref with a positive temperature coefficient and △V _TH with a negative temperature coefficient, a temperature-independent output reference voltage V _ref can be obtained, and the threshold voltage V _TH can further It can be expressed as:

In the formula, ε _si represents the relative dielectric constant of the silicon substrate; N _A is the substrate doping concentration; n _i is the intrinsic carrier concentration; E _g is the band gap; ψ _B is the Fermi level potential energy and intrinsic The difference in energy level potential energy;

In the formula, N _C is the effective state density of the conduction band, N _ν is the effective state density of the valence band, ignoring the bulk effect, the temperature coefficient TC _V of the reference voltage can be obtained:

Let the temperature coefficient of the reference voltage be zero, then the width-to-length ratio of the MOS tube can be determined:

It can be seen from this formula that by adjusting K ₂₁ /K ₂₂ , a reference voltage with a temperature coefficient of zero can be obtained. _The purpose of capacitor C2 is to improve the supply voltage rejection ratio.

Under the SMIC0.18-μmCMOS process standard, use the CadenceSpectre simulator for simulation. The simulation results show that under the power supply voltage of 1.8V, the power supply voltage rejection ratio of the reference voltage source is -85.62dB at low frequency and -42dB at high frequency; it has 34.43ppm/ ℃ temperature coefficient; in the range of 1.0V-3.4V power supply voltage, it has a power supply voltage adjustment rate of 0.06%, and its power consumption is 206nW. These simulation results verify the effectiveness of the above measures.

Claims (5)

1. A full CMOS reference voltage source with a high power supply rejection ratio, comprising a reference voltage source, is characterized in that: the reference voltage source includes a starting circuit, a current source circuit and a temperature compensation circuit; the output terminal of the starting circuit is connected to the input of the current source circuit terminal, the output terminal of the current source circuit is connected to the input terminal of the temperature compensation circuit, and the output terminal of the temperature compensation circuit forms the output terminal of the entire reference voltage source; Start the circuit to help the reference source get rid of the degeneracy bias point and enter the normal working state; The current source circuit uses the working characteristics of the MOS tube in the sub-threshold area to generate a reference current of the nanoampere level; uses a cascode current mirror to suppress power supply noise; uses a MOS tube that works in the linear area to replace the traditional reference voltage source The resistor provides current bias for the reference voltage generating circuit; The temperature compensation circuit uses different MOS transistors to form a gate-source voltage difference, and through mutual adjustment, a reference voltage independent of temperature is obtained. 2. A high power supply rejection ratio full CMOS reference voltage source according to claim 1, characterized in that: the MOS transistors forming the gate-source voltage difference are 1.8V MOS transistors and 3.3V MOS transistors. 3. A high power supply rejection ratio full CMOS reference voltage source according to claim 1, characterized in that: the start-up circuit includes PMOS transistors M ₁ , M ₂ , M ₃ , NMOS transistors M ₄ , M ₅ , and capacitor C ₁ ; _The sources of the PMOS transistors M1 and M3 are connected to the power supply VDD _; the lower plate of the capacitor _C1 and the sources of the NMOS transistors M4 and _M5 are connected to the ground GND _; the gate and drain _of the PMOS transistor M1 are connected to the PMOS The source of the transistor _M2 is connected; the gate and drain of the PMOS transistor _M2 , the gate _of the PMOS transistor M3, and the gate of the NMOS transistor M4 are connected to the upper plate _of the capacitor _{C2 ;} the NMOS transistor M3 And the drain of M4 is connected with the gate of _{M5 ;} the drain of NMOS transistor _M5 forms the output end of the start-up circuit, and is connected with the input end of the current source circuit. 4. A full CMOS reference voltage source with high power supply rejection ratio according to claim 1, characterized in that: the current source circuit comprises PMOS transistors M ₆ , M ₇ , M ₁₁ , M ₁₂ , M ₁₅ , M ₁₆ , and NMOS tubes M ₈ , M ₉ , M ₁₀ , M ₁₃ , M ₁₄ , M ₁₇ , M ₁₈ ; The sources of the PMOS transistors M ₆ , M ₁₁ and M ₁₅ are connected to the power supply VDD; the sources of the NMOS transistors M ₁₀ , M ₁₄ and M ₁₈ are connected to the ground GND; the gate and drain of the PMOS transistor M ₆ and the PMOS transistor M ₇ , the gate of PMOS transistor _M11 and _M15 are connected to form the first output end of the current source circuit and connected to the first input end of the temperature compensation circuit _; the gate and drain of PMOS transistor M7 It is connected with the drain of the NMOS transistor _M8 and the gates of the PMOS transistors _M12 and _M16 to form the second output end of the current source circuit, and is connected to the second input end of the temperature compensation circuit; the gate of the NMOS transistor _M8 The pole is connected with the drain _of the PMOS transistor M12, the gate and the drain of the NMOS transistor _M13 to form the input end of the current source circuit, and is connected with the output end of the start-up circuit; the source electrode of the NMOS transistor _M8 is connected to the NMOS transistor M8 _The drain of M9 is connected; the gate of NMOS transistor _M9 , the gate and drain of NMOS transistor _M14 are connected with the source of NMOS transistor _M13 ; the source of NMOS transistor _M9 is connected with the source of NMOS transistor _M10 The drains are connected; the gates of the NMOS transistors M ₁₀ , M ₁₇ and M ₁₈ and the drain of the NMOS transistor M ₁₇ are connected to the drain of the PMOS transistor M ₁₆ ; the drain of the PMOS transistor M ₁₁ is connected to the source of the PMOS transistor M ₁₂ The drain of the PMOS transistor _M15 is connected to the source of the PMOS transistor _M16 ; the source of the NMOS transistor _M17 is connected to the drain of the NMOS transistor _M18 . 5. A high power supply rejection ratio full CMOS reference voltage source according to claim 1, characterized in that: the temperature compensation circuit includes PMOS transistors M ₁₉ , M ₂₀ , NMOS transistors M ₂₁ , M ₂₂ , and capacitor C ₂ ; The source of the PMOS transistor _M19 is connected to the power supply VDD; the source of the NMOS transistor _M22 and the lower plate of the capacitor _C2 are connected to the ground GND; the gate of the PMOS transistor _M19 forms the first input end of the temperature compensation circuit, and It is connected with the first output end of the current source circuit; _the drain of the PMOS transistor M19 is connected with _the source electrode of the PMOS transistor M20; _the gate of the PMOS transistor M20 forms the second input end of the temperature compensation circuit, and is connected with the current source The second output end of the circuit is connected; the drain of the PMOS transistor M20 is connected to _the drain and gate of the NMOS transistor _M21 , and the gate of the NMOS transistor _M22 ; the source of the NMOS transistor _M21 , the gate of the NMOS transistor _M22 The drain is connected to the upper plate of the capacitor C ₂ and forms the output terminal V _ref of the entire reference voltage source.