CN114444426A - Chip design method, device, storage medium and electronic equipment - Google Patents

Abstract

The application discloses a chip design method and device, a storage medium and electronic equipment. The method can be applied to an electronic device, and comprises the following steps: determining a key time sequence path in the layout and wiring of the chip; arranging a dummy metal barrier layer on the critical time sequence path; and arranging the dummy metal at the position outside the range of the dummy metal barrier layer, wherein the layout wiring density is less than a preset density threshold value. The method and the device can save the time of chip design.

Description

Chip design method, device, storage medium and electronic device

technical field

The present application belongs to the technical field of electronic equipment, and in particular relates to a chip design method, device, storage medium and electronic equipment.

Background technique

In the manufacturing process of chips (ie integrated circuits), in order to ensure the manufacturability, the metal layer (Metal Layer) needs to meet the minimum density requirements. The density of metal layers used for interconnection is usually lower, and additional dummy metal needs to be added. In advanced processes, adding dummy metal will introduce parasitic capacitance and affect the critical timing path (Critical Timing Path), resulting in lower chip frequency. For this problem, there are generally two solutions in the related art, and the chip design time of the two solutions is relatively long.

SUMMARY OF THE INVENTION

Embodiments of the present application provide a chip design method, device, storage medium, and electronic device, which can save chip design time.

In a first aspect, an embodiment of the present application provides a chip design method, which is applied to an electronic device, including:

Determine the critical timing path in the layout and routing of the chip;

setting a dummy metal block layer on the critical timing path;

A dummy metal is arranged outside the range of the dummy metal barrier layer where the layout and wiring density is less than a preset density threshold.

In a second aspect, an embodiment of the present application provides a chip design device, which is applied to electronic equipment, including:

Determine the module to determine the critical timing path in the layout and routing of the chip;

a first setting module, configured to set a dummy metal barrier layer on the critical timing path;

The second setting module is configured to set dummy metal at a position outside the range of the dummy metal barrier layer where the layout and wiring density is less than a preset density threshold.

In a third aspect, an embodiment of the present application provides a storage medium on which a computer program is stored, and when the computer program is executed on a computer, the computer is made to execute the chip design method provided by the embodiment of the present application.

In a fourth aspect, an embodiment of the present application further provides an electronic device, including a memory and a processor, where the processor is configured to execute the chip design method provided by the embodiment of the present application by invoking a computer program stored in the memory.

In this embodiment of the present application, the electronic device can determine a critical timing path in the layout and wiring of the chip, and set a dummy metal barrier layer on the critical timing path, and the purpose of setting the dummy metal barrier layer is to mark on the dummy metal barrier layer. No dummy metal is arranged in the area, and dummy metal is arranged outside the range of the dummy metal barrier layer where the layout and wiring density is less than a preset density threshold. Since no dummy metal is provided in the area marked by the dummy metal barrier layer, mutual capacitance between the critical timing path in the marked area and the dummy metal can be prevented, that is, the generation between the critical timing path and the dummy metal in the marked area can be prevented. The parasitic capacitance can prevent the timing deterioration of the critical timing path, thereby reducing the timing modification time. At the same time, it also saves the time for setting dummy metal in the area marked by the dummy metal barrier layer, which can greatly save the chip design process. Set the time for the dummy metal. In addition, the dummy metal is set outside the range of the dummy metal barrier layer where the layout and wiring density is less than the preset density threshold, so as to meet the minimum density rule requirement of the metal layer. Therefore, in the embodiment of the present application, for the method of setting the dummy metal barrier layer for the critical timing path, the dummy metal is not provided in the area marked by the metal barrier layer, and the wiring density outside the area marked by the metal barrier layer is less than the preset density threshold. Dummy metal is set at the position, which can save the time of chip design.

Description of drawings

The technical solutions of the present application and the beneficial effects thereof will be apparent through the detailed description of the specific embodiments of the present application in conjunction with the accompanying drawings.

FIG. 1 is a schematic flowchart of a first solution in the related art.

FIG. 2 is a schematic flowchart of the second solution in the related art.

FIG. 3 is a schematic flowchart of a chip design method provided by an embodiment of the present application.

FIG. 4 is a schematic diagram of a wiring including a critical timing path provided by an embodiment of the present application.

FIG. 5 is a schematic diagram of wiring after the dummy metal barrier layer is provided according to an embodiment of the present application.

FIG. 6 is another schematic diagram of wiring provided by an embodiment of the present application after the dummy metal barrier layer is provided.

FIG. 7 is a schematic diagram of wiring after a dummy metal barrier layer is provided on a critical timing path according to an embodiment of the present application.

FIG. 8 is another schematic diagram of wiring after a dummy metal barrier layer is provided on a critical timing path according to an embodiment of the present application.

FIG. 9 is a schematic diagram of wiring without protection of critical timing paths according to an embodiment of the present application.

FIG. 10 is another schematic diagram of wiring without protection of critical timing paths according to an embodiment of the present application.

FIG. 11 is a schematic plan view of introducing a dummy metal parasitic capacitance of the same layer into an M6 metal layer according to an embodiment of the present application.

FIG. 12 is a schematic three-dimensional schematic diagram of introducing a dummy metal parasitic capacitance of the same layer into an M6 metal layer according to an embodiment of the present application.

13 is a schematic cross-sectional view of introducing dummy parasitic capacitances of upper and lower layers into an M6 metal layer according to an embodiment of the present application.

FIG. 14 is a schematic three-dimensional schematic diagram of introducing dummy parasitic capacitances of upper and lower layers into the M6 metal layer provided by the embodiment of the present application.

FIG. 15 is a schematic diagram of setting a dummy metal after protecting a critical timing path according to an embodiment of the present application.

FIG. 16 is another schematic diagram of setting a dummy metal after protecting a critical timing path according to an embodiment of the present application.

FIG. 17 is a schematic plan view of eliminating parasitic capacitance of dummy metal in the same layer according to an embodiment of the present application.

FIG. 18 is a schematic three-dimensional schematic diagram of eliminating parasitic capacitance of dummy metal in the same layer according to an embodiment of the present application.

FIG. 19 is a schematic cross-sectional view of eliminating parasitic capacitance of upper and lower dummy metals according to an embodiment of the present application.

FIG. 20 is a schematic three-dimensional schematic diagram of eliminating parasitic capacitance of upper and lower dummy metals according to an embodiment of the present application.

FIG. 21 is another schematic flowchart of a chip design method provided by an embodiment of the present application.

FIG. 22 is a schematic structural diagram of a chip design apparatus provided by an embodiment of the present application.

FIG. 23 is a schematic structural diagram of an electronic device provided by an embodiment of the present application.

FIG. 24 is another schematic structural diagram of an electronic device provided by an embodiment of the present application.

Detailed ways

Please refer to the drawings, wherein the same component symbols represent the same components, and the principles of the present application are exemplified by being implemented in a suitable computing environment. The following description is based on illustrated specific embodiments of the present application and should not be construed as limiting other specific embodiments of the present application not detailed herein.

In the manufacturing process of a chip (ie, an integrated circuit), in order to ensure manufacturability and prevent etching failure of the chip due to excessive or insufficient exposure during the manufacturing process, the metal layer needs to meet the minimum density requirements. Metal layer refers to the layer used to represent metal interconnect lines in integrated circuit layout design. The density of metal layers used for interconnection is usually lower, and additional dummy metal needs to be set.

In an advanced process, setting the dummy metal will introduce parasitic capacitance and affect the timing of the critical timing path (Critical Timing Path), which will deteriorate the timing of the critical timing path and reduce the chip frequency. For this problem, there are generally two solutions in the related art, and the chip design time of the two solutions is relatively long.

Please refer to FIG. 1 , which is a schematic flowchart of a first solution in the related art. The first solution uses a PR tool for chip placement and routing (PR); the data of the placement and routing is exported into a file in GDS (Graphic Design System) format, and the GDS can also be a graphic design system, which is a A binary database file format used for the interaction of integrated circuit layout data. Then, set a dummy metal in the corresponding position of the layout of the GDS format file. The dummy metal refers to the area with low metal connection density on the integrated circuit layout in order to meet the requirements of the minimum density rule of the metal layer in the layout design of the integrated circuit. Inserted metal graphics. After that, when the static timing analysis (Static Timing Analysis, STA) is passed, the layout and routing design flow of the chip is ended, and when the static timing analysis fails, the engineering modification is used to repair the timing.

In the first solution, dummy metal is added first, static timing analysis checks timing violation paths, and then engineering change order (ECO) is used to repair timing. The first solution is to fix the timing in the final stage of the design. Timing closure is more complex and the design time is too long.

Please refer to FIG. 2 , which is a schematic flowchart of the second solution in the related art. In the second solution, the PR tool is used for chip layout and wiring; according to the layout and wiring data, a Design Rule Check (DRC) rule file is manually written, and what are specified in the design rule check rule file Dummy metals need to be added to the positions, and dummy metals cannot be added to which positions. Dummy metals are placed in the corresponding locations according to the design rule check rule file. In this case, static timing analysis is generally performed. But because the design rule check rules file is too large, it takes up too much disk space, and it takes too long to set up the dummy metal.

In order to solve the above-mentioned problems, in the embodiment of the present application, a dummy metal barrier layer is set in the PR tool for the critical timing path, and the dummy metal barrier layer is used as a barrier layer to prevent the dummy metal generation tool from generating a dummy metal pattern at the place covered by the dummy metal barrier layer. . The embodiments of the present application can not only save the chip design time, but also maintain good timing. A detailed description will be given below.

It can be understood that, the execution body of the embodiment of the present application may be an electronic device such as a smart phone, a tablet computer, a notebook computer, or a desktop computer.

Please refer to FIG. 3 , which is a schematic flowchart of a chip design method provided by an embodiment of the present application. The chip design method can be applied to electronic equipment. The flow of the chip design method may include:

101. Determine a critical timing path in the layout and routing of the chip.

For example, when the chip is placed and routed, special placement and routing software is generally used, for example, a PR tool is used to perform the chip placement and routing. Specifically, a PR tool can be installed on an electronic device. The PR tool is a placement and routing tool, that is, a software tool for chip placement and routing. The PR tool can be used to perform chip placement and routing. When the layout and wiring of the chip is completed, the data of the layout and wiring of the chip will be obtained.

Then, according to the layout and routing data, the critical timing paths in the layout and routing of the chip can be determined. For example, please refer to FIG. 4 , which is a schematic diagram of a wiring including a critical timing path provided by an embodiment of the present application. The path with filling points in Figure 4 is the Critical Timing Path, and the unfilled path is the Normal Timing Path.

102. Set a dummy metal barrier layer on the critical timing path.

For example, a PR tool is used to set a dummy metal barrier layer on the critical timing path, and the dummy metal barrier layer can prevent the dummy metal generation tool from generating dummy metal patterns where it covers. The dummy metal barrier layer is virtual, not a physical layer, and can be regarded as a marker. The marker is set by the PR tool, and the marker can mark the area around the critical timing path, that is, the dummy metal barrier layer is only is a protective marker, not an entity. The purpose of disposing the dummy metal barrier layer is not to dispose dummy metal in the area marked by the dummy metal barrier layer, but to dispose dummy metal in other areas outside the area marked by the dummy metal barrier layer.

It can be understood that since no dummy metal is provided in the area marked by the dummy metal barrier layer, it can not only prevent mutual capacitance between the critical timing path and the dummy metal in the area marked by the dummy metal barrier layer, but also prevent the critical The parasitic capacitance is generated between the timing path and the dummy metal, so that the timing of the critical timing path can be protected, and the timing of the critical timing path can be prevented from deteriorating, thereby reducing the modification time of the timing. The time for setting the dummy metal in the area can greatly save the time for setting the dummy metal in the chip design process. The purpose of setting the dummy metal in other areas outside the area marked by the dummy metal barrier layer is to meet the requirements of the minimum density rule of the metal layer.

Please refer to FIG. 5 . FIG. 5 is a schematic diagram of wiring after the dummy metal barrier layer is provided according to an embodiment of the present application. M5 and M6 in Figure 5 represent timing paths on two different metal layers. The M6 metal layer is located on the upper layer of the M5 metal layer. The two timing paths on the M5 metal layer are parallel to each other in the horizontal direction. The three timing paths on the M6 metal layer (including one critical timing path and two normal The timing paths are parallel to each other in the vertical direction. The timing paths on the M5 metal layer and the timing paths on the M6 metal layer intersect vertically in the vertical projection direction, forming a criss-cross wiring. It can reduce unnecessary interlayer crosstalk, ensure the DC Drop (IR-Drop) performance of the chip, and play a positive role in improving the performance of the chip.

Please refer to FIG. 6 . FIG. 6 is another schematic diagram of wiring after the dummy metal barrier layer is provided according to an embodiment of the present application. M6 and M7 in Figure 6 represent timing paths on two different metal layers. The M7 metal layer is on top of the M6 metal layer. The two timing paths on the M7 metal layer are parallel to each other in the horizontal direction. The timing path on the M7 metal layer and the timing path on the M6 metal layer are vertically intersected in the vertical projection direction, forming a criss-cross wiring. The wiring in this way can reduce unnecessary crosstalk between layers, ensure the DC voltage drop performance of the chip, and play a positive role in improving the performance of the chip.

It is understandable that M5, M6 and M7 represent the timing paths on three different metal layers, namely the timing paths on the M5 metal layer, the timing paths on the M6 metal layer and the timing paths on the M7 metal layer. path. Among them, the M7 metal layer is on the top layer, the M6 metal layer is on the middle layer, and the M5 metal layer is on the bottom layer. In other words, the M7 metal layer, the M6 metal layer, and the M5 metal layer are sequentially stacked from top to bottom. The M6 metal layer is located between the M7 metal layer and the M5 metal layer.

For example, taking the M6 metal layer as an example, please refer to FIG. 7 and FIG. 8 . FIG. 7 is a schematic diagram of wiring after a dummy metal barrier layer is provided on a critical timing path according to an embodiment of the present application. FIG. 8 is another schematic diagram of wiring after a dummy metal barrier layer is provided on a critical timing path according to an embodiment of the present application. In Fig. 7 and Fig. 8, the dummy metal barrier layers M5-7Dummy MetalBlock Layer are set around and above and below the critical timing path on the M6 metal layer, because the area marked by the dummy metal barrier layer M5-7Dummy Metal Block Layer covers All of the critical timing path Critical Timing Path M6 is included, and no dummy metal is set in the area marked by the dummy metal barrier layer M5 to 7 Dummy MetalBlock Layer, that is, no dummy metal is set within the range covered by the marked area, which can not only prevent critical timing Parasitic capacitance is generated between the path Critical Timing Path M6 and the dummy metal, so it can ensure that the timing of the critical timing path Critical Timing Path M6 will not be deteriorated, preventing the frequency of the chip from being reduced, thereby reducing the timing modification time, and also because it saves The time for setting the dummy metal in the range covered by the marked area can greatly save the time for setting the dummy metal in the chip design process. Since the dummy metal blocking layers M5 to 7 are virtual, the dotted lines are drawn in FIG. 7 and FIG. 8 .

103. Set a dummy metal at a position outside the range of the dummy metal barrier layer where the layout and wiring density is less than a preset density threshold.

For example, please refer to FIG. 9. FIG. 9 is a schematic diagram of wiring without protection of critical timing paths according to an embodiment of the present application. Among them, M5 Dummy is the dummy metal set on the M5 metal layer, and M6 Dummy is the dummy metal set on the M6 metal layer. The dummy metal M5 Dummy set on the M5 metal layer and the timing paths on the M5 metal layer are parallel to each other. Specifically, the dummy metal M5 Dummy set on the M5 metal layer and the timing path on the M5 metal layer are horizontal The directions are parallel to each other to prevent intersections between timing paths, which can improve the performance of the chip. The dummy metal is a physical entity, not a virtual one. The outer frame of the dummy metal M5 Dummy set on the M5 metal layer shown in Figure 9 is a dotted line, which is only to distinguish the dummy metal on the M5 metal layer, not to indicate is virtual.

The dummy metal M6 Dummy set on the M6 metal layer and the timing paths on the M6 metal layer are parallel to each other. Specifically, the dummy metal M6 Dummy set on the M6 metal layer and the timing paths on the M6 metal layer are parallel to each other in the vertical direction to prevent intersection between the timing paths, which can improve the performance of the chip. The dummy metal is a physical entity, not a virtual one. The outer frame of the dummy metal M6 Dummy set on the M6 metal layer shown in Figure 9 is a dotted line, just to distinguish it as a dummy metal on the M6 metal layer, not to indicate is virtual.

FIG. 10 is another schematic diagram of wiring without protection of critical timing paths according to an embodiment of the present application. M7Dummy is the dummy metal set on the M7 metal layer. The dummy metal M7 Dummy set on the M7 metal layer and the timing paths on the M7 metal layer are parallel to each other. Specifically, the dummy metal M7 Dummy set on the M7 metal layer and the timing paths on the M7 metal layer are parallel to each other in the horizontal direction to prevent intersection between the timing paths, which can improve the performance of the chip. The dummy metal is a physical entity, not a virtual one. The outer frame of the dummy metal M7 Dummy set on the M7 metal layer shown in Figure 10 is a dotted line, just to distinguish it as a dummy metal on the M7 metal layer, not to indicate is virtual.

If the timing critical path is not protected and dummy metal is set directly, two kinds of parasitic capacitances will be introduced, one of which is the dummy metal parasitic capacitance Cap on the same layer. Please refer to FIG. 11 and FIG. 12 . Figure 12 is a schematic plan view of introducing dummy metal parasitic capacitances of the same layer into the M6 metal layer; FIG. 12 is a three-dimensional schematic diagram of introducing dummy parasitic capacitances of upper and lower layers into the M6 metal layer according to an embodiment of the present application.

The other is the dummy parasitic capacitance Cap of the upper and lower layers. Please refer to FIG. 13 and FIG. 14 . FIG. 13 is a schematic cross-sectional view of introducing dummy parasitic capacitances of the upper and lower layers into the M6 metal layer according to an embodiment of the present application. FIG. 14 is a schematic three-dimensional schematic diagram of introducing dummy parasitic capacitances of upper and lower layers into the M6 metal layer provided by the embodiment of the present application. These parasitic capacitances will cause the timing of the Critical Timing Path M6 to deteriorate, thereby reducing the frequency of the chip.

For example, in one embodiment, after the dummy metal barrier layers M5-7Dummy Metal Block Layer are set on the Critical Timing Path M6, no dummy metal is set in the area marked by the dummy metal barrier layers M5-7Dummy MetalBlock Layer , so it can prevent the mutual capacitance between the critical timing path M6 and the dummy metal in the marked area, that is, it can prevent the parasitic capacitance between the critical timing path M6 and the dummy metal. Since there is no parasitic capacitance, it can be It ensures that the timing of the critical timing path M6 will not deteriorate, preventing the frequency of the chip from being reduced, thereby reducing the modification time of the timing, and at the same time, it also eliminates the need to set the area marked by the dummy metal barrier layer M5 to 7Dummy Metal Block Layer. Therefore, the time for setting the dummy metal in the chip design process can be greatly saved.

In addition, a dummy metal is set outside the range of the dummy metal barrier layers M5 to 7 Dummy Metal Block Layer where the layout and wiring density is less than the preset density threshold, so as to meet the minimum density rule requirement of the metal layer. The preset density threshold may be the minimum density of the metal layer. It should be noted that when setting the dummy metal, you can use the dummy metal generation tool to set the dummy metal. For example, use the Calibre tool to set the dummy metal. Of course, you can also select a suitable dummy metal generation tool according to specific needs to set the preset metal, etc. Wait.

For example, in one embodiment, when dummy metal barrier layers M5-7 Dummy Metal Block Layers are used to protect the critical timing path M6, please refer to FIG. 15 and FIG. 16, and FIG. 15 is the protection critical timing provided by the embodiment of the present application. Schematic of setting the dummy metal after the path. FIG. 16 is another schematic diagram of setting a dummy metal after protecting a critical timing path according to an embodiment of the present application. In the case of protecting the critical timing path Critical Timing Path M6, the dummy metal generation tool will detect the positions of the dummy metal barrier layers M5-7Dummy Metal Block Layer. A dummy metal is set at the position where the layout and wiring density outside this position is less than the preset density threshold, so as to meet the requirements of the minimum density rule of the metal layer.

Since no dummy metal is set in the area marked by the metal barrier layers M5~7Dummy Metal Block Layer, the metal layer and the dummy metal where the critical timing path M6 is located have no parasitic capacitance between the same layer and between the upper and lower layers. Since there is no parasitic capacitance, it can ensure that the timing of the critical timing path M6 will not deteriorate, preventing the frequency of the chip from being reduced, thereby reducing the modification time of the timing, and also because the metal barrier layer M5 ~ 7 Dummy Metal Block The time for setting the dummy metal in the area marked by the Layer can greatly save the time for setting the dummy metal in the chip design process. Please refer to FIG. 17 and FIG. 18 . FIG. 17 is a schematic plan view of eliminating parasitic capacitance of dummy metal in the same layer according to an embodiment of the present application. FIG. 18 is a schematic three-dimensional schematic diagram of eliminating parasitic capacitance of dummy metal in the same layer according to an embodiment of the present application. Please refer to FIG. 19 and FIG. 20 . FIG. 19 is a schematic cross-sectional view of eliminating parasitic capacitance of upper and lower dummy metals according to an embodiment of the present application. FIG. 20 is a schematic three-dimensional schematic diagram of eliminating parasitic capacitance of upper and lower dummy metals according to an embodiment of the present application.

For example, after the dummy metal is set in the above process 103, the data of the layout and wiring after the dummy metal is set can be verified by static timing analysis. Static timing analysis is a workflow for calculating and predicting timing, and the workflow does not require simulation through input excitation. Static timing analysis examines individual paths in a circuit for issues such as glitches, delay paths, and clock skew. After the above process is performed, in the embodiment of the present application, the general static timing analysis can be passed. If the data of the placement and routing after setting the dummy metal passes the verification of the static timing analysis, the placement and routing process of the current chip ends. If the static timing analysis is not passed, the timing modification needs to continue until it passes the verification of the static timing analysis.

It can be understood that, in the embodiment of the present application, the electronic device can determine the critical timing path Critical Timing Path M6 in the layout and wiring of the chip, and set the dummy metal barrier layers M5 to 7 Dummy Metal Block for the critical timing path Critical Timing Path M6. Layer, the purpose of setting the dummy metal blocking layer M5-7Dummy MetalBlock Layer is to not set dummy metal in the area marked by the dummy metal blocking layer M5-7Dummy Metal Block Layer, but in the dummy metal blocking layer M5-7Dummy Metal Block Layer Dummy metals are set at locations where the placement and routing density outside the range is less than the preset density threshold. Since no dummy metal is set in the area marked by the dummy metal barrier layers M5-7 DummyMetal Block Layer, the mutual capacitance between the Critical Timing Path M6 and the dummy metal in the marked area can be prevented, that is, it can be prevented in the marked area. The parasitic capacitance is generated between the critical timing path Critical Timing Path M6 and the dummy metal, which can prevent the timing deterioration of the critical timing path Critical Timing Path M6, thereby reducing the timing modification time, and eliminating the need for the metal barrier layer M5~ The time for setting dummy metals in the area marked by the 7Dummy Metal Block Layer can greatly save the time for setting dummy metals in the chip design process.

In addition, a dummy metal is set outside the range of the dummy metal barrier layers M5 to 7 Dummy Metal Block Layer where the layout and wiring density is less than the preset density threshold, so as to meet the minimum density rule requirement of the metal layer. Therefore, in the embodiment of the present application, the dummy metal barrier layer is set for the critical timing path M6, by not arranging dummy metal in the area marked by the metal barrier layers M5-7 Dummy Metal Block Layer, and the metal barrier layers M5-7Dummy A dummy metal is set outside the area marked by the Metal Block Layer where the wiring density is less than the preset density threshold, which can save chip design time. The embodiment of the present application innovatively proposes to save design time and protect the critical timing path Critical TimingPath M6 in the process of setting the dummy metal by setting dummy metal barrier layers M5 to 7 Dummy Metal BlockLayer on the critical timing path Critical Timing Path M6 in the PR tool. .

Please refer to FIG. 21 , FIG. 21 is another schematic flowchart of a chip design method provided by an embodiment of the present application. The chip design method can be applied to electronic equipment. The flow of the chip design method may include:

201. Perform chip layout and wiring.

For example, when the chip is placed and routed, special placement and routing software is generally used, for example, a PR tool is used for chip placement and routing. Specifically, a PR tool can be installed on an electronic device. The PR tool is a placement and routing tool, that is, a software tool for chip placement and routing. The PR tool can be used to perform chip placement and routing. When the layout and wiring of the chip is completed, the data of the layout and wiring of the chip will be obtained.

202. Generate a timing report according to the layout and routing data.

For example, in chip design, performance, power consumption and area are the three factors that measure chip metrics. Among them, the performance directly depends on the timing parameters. It can be seen that the timing design plays a pivotal role in the back-end design because it directly determines the performance of the chip.

After the placement and routing of the chip is completed in the PR tool and the placement and routing data is obtained, the PR tool will generate a timing report according to the placement and routing data. The timing report can summarize the results of timing analysis, mainly to report the paths that violate timing constraints found by timing analysis after synthesis. There are two ways of violation, one is SetupTimeViolation and the other is Hold Time Violation.

For example, when a compiler tool performs static timing analysis, it must first have a gate-level circuit netlist after synthesis/route. Then, starting from the input port and the output port of the register, the delay and total delay of each logic gate are calculated step by step according to the connection sequence until the input port or output port of the register is reached. Of these timing paths, the longest timing path delays longer than the specified duration and will report a setup violation error. A hold time violation is reported if the timing path delay is less than the specified minimum delay in all timing paths.

203. Acquire a critical timing path according to the timing report.

For example, after the PR tool generates a timing report according to the layout and routing data, it can obtain the critical timing path according to the timing report. Generally, the critical timing path can be directly obtained through the timing report.

Specifically, timing analysis tools can find and analyze all timing paths in a design. Each timing path has a start point and an end point. The starting point is the point in the design when the data is loaded by the clock edge, and the end point is the point when the data is loaded by another time edge through the combinational logic.

Specifically, the starting point is the location in the design where data is triggered by a clock edge. Data propagates through combinational logic in the timing path and is then captured at the endpoint by another clock edge. The starting point of a timing path is the clock pin of a sequential element or the input port of the design. The clock edge triggers the data at the start point. An input port can also be considered a starting point because the input port is triggered by an external source.

The clock edge captures the data at the endpoint. An output port can also be considered a destination because the data at the output port can be captured by an external source.

For example, each path in the design has a corresponding timing slack. slack is a time value that can be positive, 0 or negative.

It should be noted that the slack value displayed in the timing report is the time required for the data minus the data arrival time. When the slack value is a very small positive value or 0, it means that the timing constraints are just met. When the slack value is negative, the frequency of the chip will drop. The greater the absolute value of the negative number, the more the frequency of the chip will drop. If the slack value is negative, the design needs to be changed to fix the violation, whereas if the slack value is quite large, there are still many opportunities for optimization in this timing path. If all timing paths have no timing violations, the slack value is positive.

For example, in an implementation manner, the acquiring the critical timing path according to the timing report may include:

A path whose slack value is less than a preset threshold is obtained from the timing report, and used as the critical timing path.

In this embodiment of the present application, a preset threshold is set, and a path whose slack value is less than the preset threshold is regarded as a critical timing path. For example, if the slack value is recorded in the timing report, the path with the slack value less than the preset threshold can be found in the timing report, and the path is regarded as the critical timing path Critical Timing Path M6. For example, the general preset threshold is 0, the path with the slack value less than 0 is found in the timing report, and the path with the slack value less than 0 is regarded as the critical timing path Critical Timing Path M6. Of course, the preset threshold can also be a small positive number. For example, the preset threshold is 0.3. Find the path with a slack value of less than 0.3 in the timing report, and use the path with a slack value of less than 0.3 as the critical timing path. M6. For another example, the preset threshold is 0.5, a path with a slack value less than 0.5 is found in the timing report, and the path with a slack value less than 0.5 is used as the critical timing path Critical Timing Path M6. For another example, if the preset threshold is 1, a path with a slack value less than 1 is found in the timing report, and the path with a slack value less than 1 is used as the critical timing path Critical Timing Path M6, and so on.

It is understandable that when the slack value of only one path in the timing report is less than the preset threshold, there is only one critical timing path. When the slack value of multiple paths in the timing report is less than the preset threshold, there are multiple critical timing paths. timing path. See the critical timing path in Figure 4.

204. Set a dummy metal barrier layer around the critical timing path.

For example, in one embodiment, after a path with a slack value less than 0 is found and used as the critical timing path Critical Timing Path M6, a dummy metal barrier layer M5~ is set around the critical timing path Critical Timing Path M6. 7Dummy Metal Block Layer, that is, the area marked by the dummy metal barrier layers M5 to 7Dummy Metal Block Layer around the Critical Timing Path M6. Please refer to FIG. 18 and FIG. 20. The shapes of the dummy metal barrier layers M5-7 Dummy Metal Block Layer and the critical timing path Critical Timing Path M6 can be the same or different. The critical timing path Critical TimingPath M6 is in the dummy metal barrier layer M5- Within the area marked by the 7Dummy Metal Block Layer.

For example, in another embodiment, after finding a path with a slack value less than 0.3 and using it as the critical timing path Critical Timing Path M6, a dummy metal barrier layer M5~ 7Dummy Metal Block Layer, that is, the area marked by the dummy metal barrier layers M5 to 7Dummy Metal Block Layer around the Critical Timing Path M6. Please refer to FIG. 18 and FIG. 20. The shapes of the dummy metal barrier layers M5-7 Dummy Metal Block Layer and the critical timing path Critical Timing Path M6 can be the same or different. Within the area marked by the 7Dummy Metal Block Layer.

For example, in other embodiments, after a path with a slack value less than 0.5 is found and used as the critical timing path Critical Timing Path M6, dummy metal barrier layers M5 to 7 Dummy Metal are set around the critical timing path Critical Timing Path M6 Block Layer, that is, the area marked by the dummy metal barrier layers M5 to 7 Dummy Metal Block Layer around the Critical Timing Path M6. Please refer to FIG. 18 and FIG. 20. The shapes of the dummy metal barrier layers M5-7 Dummy Metal Block Layer and the critical timing path Critical Timing Path M6 can be the same or different. The critical timing path Critical TimingPath M6 is in the dummy metal barrier layer M5- Within the area marked by the 7Dummy Metal Block Layer.

For example, in one embodiment, the disposing the dummy metal barrier layer around the critical timing path may include:

The dummy metal barrier layer is disposed around and above the critical timing path.

It can be understood that by setting dummy metal barrier layers around and above and below the critical timing path, for example, setting dummy metal barrier layers M5 to 7DummyMetal Block Layer around and above and below the critical timing path Critical Timing Path M6, this can expand the dummy metal. The coverage of the area marked by the barrier layer is convenient for the area marked by the dummy metal barrier layer M5 to 7 Dummy Metal Block Layer to completely cover the critical timing path Critical TimingPath M6, so as to prevent the critical timing path Critical Timing Path M6 from not being fully covered. There is a problem of parasitic capacitance between the covered position and the preset metal. Therefore, by covering all the marked areas on the critical timing path Critical Timing Path M6, it can further prevent parasitic generation between the critical timing path and the dummy metal. Therefore, the timing of the critical timing path M6 can be prevented from deteriorating, and the frequency of the chip can be prevented from being reduced, thereby reducing the modification time of the timing.

For example, in one embodiment, the shape of the critical timing path M6 and the shapes of the dummy metal barrier layers M5 - 7 Dummy Metal Block Layer may both be rectangular parallelepiped shapes. The critical timing path M6 is inside the rectangular parallelepiped shape marked by the dummy metal barrier layers M5 to 7 Dummy Metal Block Layer. Similar to a large cuboid with a small cuboid inside. By setting the shape of the area marked by the dummy metal barrier layers M5 to 7 Dummy Metal Block Layer as a regular graphic shape, it can not only reduce the space volume of the area marked by the dummy metal barrier layers M5 to 7 Dummy Metal Block Layer, but also simplify the dummy metal The setting process of the barrier layer is to simplify the process of laying the dummy metal barrier layer.

For example, in one embodiment, if the area marked by the dummy metal barrier layers M5 to 7 Dummy Metal Block Layer is to completely cover the critical timing path M6, the following conditions must generally be met: the dummy metal barrier layers M5 to 7 Dummy Metal Block Layer The length of Layer is greater than the length of the critical timing path CriticalTiming Path M6, the width of the dummy metal barrier layer M5-7Dummy Metal Block Layer is greater than the width of the critical timing path Critical Timing Path M6, and the height of the dummy metal barrier layer M5-7Dummy Metal BlockLayer is the critical timing The metal layer M6 where the path Critical Timing Path M6 is located, the metal layer M7 located on the upper layer of the metal layer where the Critical Timing Path M6 is located, and the metal map on the next layer of the metal layer where the Critical Timing Path M6 is located The sum of the heights of layer M5.

The design of the length and width of the dummy metal barrier layers M5-7Dummy Metal Block Layer is to ensure that the area marked by the dummy metal barrier layers M5-7Dummy Metal Block Layer can completely cover the critical timing path in the length and width directions. M6, in addition, the height design can not only ensure that the area marked by the dummy metal barrier layer M5~7 Dummy Metal Block Layer can completely cover the critical timing path M6 in the height direction, but also can reduce the dummy metal barrier layer M5~ The volume of the 7Dummy MetalBlock Layer saves design costs.

In FIG. 7 and FIG. 8 , the dummy metal barrier layers M5 to 7Dummy Metal Block Layer are arranged around and above and below the critical timing path Critical Timing Path M6 on the M6 metal layer. By setting the dummy metal barrier layers M5 to 7Dummy Metal Block Layer, No dummy metal is set in the area marked by the dummy metal barrier layers M5-7 Dummy Metal Block Layer, which can prevent the timing deterioration of the critical timing path M6 on the M6 metal layer. The time for setting the dummy metal in the area marked by M5~7Dummy Metal Block Layer can greatly save the time for setting the dummy metal in the chip design process.

It can be understood that the size of the dummy metal barrier layers M5~7Dummy Metal Block Layer is larger than the size of the critical timing path M6 in the same direction, so as to ensure that the area marked by the dummy metal barrier layers M5~7Dummy Metal Block Layer is critical. The timing path is surrounded by Critical Timing Path M6. The height of the dummy metal barrier layers M5～7Dummy Metal Block Layer is the height from the bottom surface of the M5 metal layer to the upper surface of the M7 metal layer, which can not only ensure that the area marked by the dummy metal barrier layers M5～7Dummy Metal Block Layer is in the height direction It can completely cover the critical timing path M6, and can also reduce the space volume of the area marked by the dummy metal barrier layers M5 to 7 Dummy Metal Block Layer, saving design costs.

The parts of the M5 metal layer and the M7 metal layer that intersect with the dummy metal barrier layers M5 to 7 Dummy Metal Block Layer in the vertical projection direction are the areas covered by the areas marked by the dummy metal barrier layers M5 to 7 Dummy Metal Block Layer. Areas also do not have dummy metals set. It can be seen that the regions marked by the dummy metal barrier layers M5-7 Dummy Metal Block Layer cover the corresponding regions in the three metal layers. It can prevent parasitic capacitance between the position covered by the area marked by the dummy metal barrier layer M5~7 Dummy Metal Block Layer and the dummy metal, prevent the timing of the critical timing path of the covered position from deteriorating, and prevent the frequency of the chip from being reduced, thereby reducing the timing. At the same time, since the time for setting dummy metals in the area marked by the metal barrier layers M5-7 Dummy Metal Block Layer is omitted, the time for setting dummy metals in the chip design process can be greatly saved.

205. Export the layout and wiring data after the dummy metal barrier layer is set as a file in a preset format.

For example, after setting the dummy metal barrier layers M5 to 7Dummy Metal Block Layer around the Critical Timing Path M6, export the layout and routing data after setting the dummy metal barrier layers M5 to 7Dummy Metal Block Layer as a file in a preset format , to facilitate subsequent operations on the preset format file.

For example, the preset format may be the GDS format. After setting the dummy metal barrier layers M5 to 7Dummy Metal Block Layer around the Critical Timing Path M6, the layout and wiring after the dummy metal barrier layers M5 to 7Dummy Metal Block Layer will be arranged. The data is exported to a file in GDS format to facilitate subsequent operations on the file in GDS format.

206. Detect the position of the dummy metal barrier layer in the file in the preset format.

For example, the positions of the dummy metal barrier layers M5-7Dummy Metal Block Layer in the file of the preset format are detected by the dummy metal generation tool, for example, the positions of the dummy metal barrier layers M5-7Dummy Metal Block Layer in the file of GDS format are detected by the Calibre tool. Location. The purpose of detecting the positions of the dummy metal barrier layers M5~7DummyMetal Block Layer is to not set dummy metal in the area marked by this position, so as to prevent the critical timing path Critical Timing Path M6 and the dummy metal from generating parasitic capacitance, and ensure the critical timing path Critical Timing Path M6. The timing will not deteriorate, preventing the frequency of the chip from being reduced, thereby reducing the modification time of the timing. At the same time, since the time for setting dummy metal in the area marked by the metal barrier layer M5~7 Dummy Metal Block Layer is omitted, it can greatly save the chip. Time to set up the dummy metal during the design process.

207. Except for the dummy metal barrier layer in the metal layer where the critical timing path is located, the metal layer located at the upper layer of the metal layer where the critical timing path is located, and the metal layer located at the next layer of the metal layer where the critical timing path is located; One or more dummy metals are set at the positions where the layout and wiring density is less than the preset density threshold.

For example, the metal layer M6 where the critical timing path Critical Timing Path M6 is located, the metal layer above the metal layer M6 where the critical timing path Critical Timing Path M6 is located, and the metal layer where the critical timing path Critical Timing Path M6 is located. One or more dummy metals are set at positions where the layout and wiring density is less than the preset density threshold except for the dummy metal barrier layers M5 to 7 Dummy Metal Block Layer in the next metal layer M5 of M6.

For example, in one embodiment, each dummy metal and its timing paths on the same metal layer are parallel to each other, which can prevent the wirings on the same metal layer from crossing and improve the performance of the chip. For example, the dummy metal on the M5 metal layer and the two timing paths on the M5 metal layer are parallel to each other, which can prevent the wiring on the M5 metal layer from crossing and improve the performance of the chip. Specifically, the dummy metal on the M5 metal layer and the timing paths on the M5 metal layer are parallel to each other in the horizontal direction, and the dummy metals on the M5 metal layer are arranged in a row in the horizontal direction.

The dummy metal on the M6 metal layer is parallel to the critical timing path and the two timing paths on the M6 metal layer respectively, which can prevent the wirings on the M6 metal layer from crossing and improve the performance of the chip. Specifically, the dummy metal on the M6 metal layer is respectively parallel to the critical timing path and the two timing paths on the M6 metal layer in the vertical direction. The plurality of dummy metals on the M6 metal layer can be arranged in a row in the vertical direction, and four rows are set on the M6 metal layer, and each row is formed by a plurality of dummy metals arranged in the vertical direction.

The dummy metal row on the M7 metal layer and the two timing paths on the M7 metal layer are parallel to each other, which can prevent the wirings on the M7 metal layer from crossing and improve the performance of the chip. Specifically, the dummy metal on the M7 metal layer and the two timing paths on the M7 metal layer are parallel to each other in the horizontal direction. Multiple strips of dummy metal on the M7 metal layer are lined up horizontally, and so on. By setting a dummy metal, the density of the metal layer can be increased to meet the minimum density requirement.

After the dummy metal is set in the above process 207, the data of the layout and wiring after the dummy metal is set can be verified by static timing analysis. Static timing analysis is a workflow for calculating and predicting timing, and the workflow does not require input excitation to simulate. Static timing analysis examines individual paths in a circuit for issues such as glitches, delay paths, and clock skew. After the above process is performed, in the embodiment of the present application, the general static timing analysis can be passed. If the data of the placement and routing after setting the dummy metal passes the verification of the static timing analysis, the placement and routing process of the current chip ends. If the static timing analysis is not passed, the timing modification needs to continue until it passes the verification of the static timing analysis.

It can be understood that, first, the embodiment of the present application innovatively proposes to set dummy metal barrier layers M5 to 7 Dummy Metal Block Layers for the critical timing path Critical Timing Path M6 in the PR tool. Path M6 sets the dummy metal barrier layer M5~7 Dummy MetalBlock Layer operation in the PR tool. When setting the dummy metal in the later stage, you can directly use the dummy metal generation tool to set the dummy metal, and in the area covered by the dummy metal barrier layer does not Setting the dummy metal can not only save the design time of the chip during the process of setting the dummy metal, but also ensure that the timing of the critical timing path CriticalTiming Path M6 will not deteriorate, so as to maintain a good frequency of the chip.

In addition, the solutions provided by the embodiments of the present application may be effective for different process nodes, and the more advanced the process, the greater the benefits, and is not limited to the above-mentioned situation.

Please refer to FIG. 22 , which is a schematic structural diagram of a chip design apparatus provided by an embodiment of the present application. The chip design device can be applied to electronic equipment. The chip design apparatus 300 may include: a determination module 301 , a first setting module 302 , and a second setting module 303 .

A determination module 301 is used to determine a critical timing path in the layout and wiring of the chip;

a first setting module 302, configured to set a dummy metal barrier layer on the critical timing path;

The second setting module 303 is configured to set dummy metal at a position outside the range of the dummy metal barrier layer where the layout and wiring density is less than a preset density threshold.

In one embodiment, the determining module 301 may also be used to:

Perform chip layout and wiring;

generating a timing report according to the placement and routing data;

Obtain the critical timing path according to the timing report.

In one embodiment, the determining module 301 may also be used to:

Find a path with a slack value less than a preset threshold in the timing report, and use it as the critical timing path.

In one embodiment, the first setting module 302 can also be used to:

The dummy metal barrier layer is disposed around the critical timing path.

In one embodiment, the first setting module 302 can also be used to:

The dummy metal barrier layer is disposed around and above the critical timing path.

For example, in one embodiment, the length of the dummy metal barrier layer is greater than the length of the critical timing path, the width of the dummy metal barrier layer is greater than the width of the critical timing path, and the width of the dummy metal barrier layer is greater than that of the critical timing path. The height is the difference between the heights of the metal layer where the critical timing path is located, the metal layer located at the upper layer of the metal layer where the critical timing path is located, and the metal layer located at the next layer of the metal layer where the critical timing path is located. and.

For example, in one embodiment, the shape of the critical timing path and the shape of the dummy metal barrier layer are both rectangular parallelepiped shapes.

In one embodiment, the first setting module 302 can also be used to:

The data of the layout and wiring after the dummy metal barrier layer is set is exported as a file in a preset format.

In one embodiment, the second setting module 303 can also be used to:

detecting the position of the dummy metal barrier layer in the file of the preset format;

In the metal layer where the critical timing path is located, the metal layer located at the upper layer of the metal layer where the critical timing path is located, and the metal layer located at the next layer of the metal layer where the critical timing path is located One or more dummy metals are arranged at positions outside the dummy metal barrier layer where the layout and wiring density is less than a preset density threshold.

For example, in one embodiment, each dummy metal and its timing paths on the same metal layer are parallel to each other.

Embodiments of the present application provide a computer-readable storage medium on which a computer program is stored, and when the computer program is executed on a computer, causes the computer to execute the process in the chip design method provided by this embodiment.

An embodiment of the present application further provides an electronic device, including a memory and a processor, and the processor is configured to execute the process in the chip design method provided by the present embodiment by invoking a computer program stored in the memory.

For example, the above electronic device may be a mobile terminal such as a tablet computer or a smart phone, or a terminal device such as a notebook computer or a desktop computer. Please refer to FIG. 23 , which is a schematic structural diagram of an electronic device provided by an embodiment of the present application.

The electronic device 400 may include components such as a memory 401, a processor 402, and the like. Those skilled in the art can understand that the structure of the electronic device shown in FIG. 23 does not constitute a limitation on the electronic device, and may include more or less components than the one shown, or combine some components, or arrange different components.

Memory 401 may be used to store applications and data. The application program stored in the memory 401 includes executable code. Applications can be composed of various functional modules. The processor 402 executes various functional applications and data processing by executing the application program stored in the memory 401 .

The processor 402 is the control center of the electronic device, uses various interfaces and lines to connect various parts of the entire electronic device, and executes the electronic device by running or executing the application program stored in the memory 401 and calling the data stored in the memory 401. The various functions and processing data of the device are used to monitor the electronic equipment as a whole.

In this embodiment, the processor 402 in the electronic device loads the executable code corresponding to the process of one or more application programs into the memory 401 according to the following instructions, and the processor 402 executes the execution and stores it in the memory 401 the application, thus executing:

Determine the critical timing path in the layout and routing of the chip;

setting a dummy metal barrier layer on the critical timing path;

A dummy metal is arranged outside the range of the dummy metal barrier layer where the layout and wiring density is less than a preset density threshold.

Referring to FIG. 24 , the electronic device 400 may include components such as a memory 401 , a processor 402 , a display screen 403 , a power supply module 404 , a microphone 405 , and a speaker 406 .

Memory 401 may be used to store applications and data. The application program stored in the memory 401 includes executable code. Applications can be composed of various functional modules. The processor 402 executes various functional applications and data processing by executing the application program stored in the memory 401 .

The processor 402 is the control center of the electronic device, uses various interfaces and lines to connect various parts of the entire electronic device, and executes the electronic device by running or executing the application program stored in the memory 401 and calling the data stored in the memory 401. The various functions and processing data of the device are used to monitor the electronic equipment as a whole.

The display screen 403 can be used to display information such as text and images, and can also be used to receive a user's touch operation when it is a touch display screen.

The power supply module 404 can be used to provide power support for each component of the electronic device, so as to ensure the normal operation of each component.

The microphone 405 can be used to receive sound signals in the surrounding environment, for example, can be used to receive the voice uttered by the user.

Speaker 406 may be used to play sound signals.

In this embodiment, the processor 402 in the electronic device loads the executable code corresponding to the process of one or more application programs into the memory 401 according to the following instructions, and the processor 402 executes the execution and stores it in the memory 401 the application, thus executing:

Determine the critical timing path in the layout and routing of the chip;

setting a dummy metal barrier layer on the critical timing path;

A dummy metal is arranged outside the range of the dummy metal barrier layer where the layout and wiring density is less than a preset density threshold.

In one embodiment, when the processor 402 executes the determining of the critical timing paths in the layout and routing of the chip, the processor 402 may execute: perform layout and routing of the chip; generate a timing report according to the layout and routing data; The timing report obtains the critical timing path.

In an implementation manner, when the processor 402 executes obtaining the critical timing path according to the timing report, it may execute: finding a path whose slack value is less than a preset threshold in the timing report, and using it as the key timing path.

In an embodiment, when the processor 402 performs the setting of the dummy metal barrier layer on the critical timing path, the processor 402 may perform: setting the dummy metal barrier layer around the critical timing path.

In one embodiment, when the processor 402 executes the process of disposing the dummy metal barrier layer around the critical timing path, the processor 402 may execute: disposing the dummy metal barrier layer around and above and below the critical timing path .

In one embodiment, the length of the dummy metal barrier layer is greater than the length of the critical timing path, the width of the dummy metal barrier layer is greater than the width of the critical timing path, and the height of the dummy metal barrier layer is The sum of the heights of the metal layer where the critical timing path is located, the metal layer located above the metal layer where the critical timing path is located, and the metal layer located at the next layer of the metal layer where the critical timing path is located.

In one embodiment, the shape of the critical timing path and the shape of the dummy metal barrier layer are both rectangular parallelepiped shapes.

In one embodiment, after the processor 402 performs the setting of a dummy metal barrier layer on the critical timing path, the dummy metal barrier layer is used to protect the critical timing path, the processor 402 further Can execute:

The data of the layout and wiring after the dummy metal barrier layer is set is exported as a file in a preset format.

In one embodiment, when the processor 402 executes to set the dummy metal outside the range of the dummy metal barrier layer where the layout and wiring density is less than a preset density threshold, the processor 402 may execute:

detecting the position of the dummy metal barrier layer in the file of the preset format;

In the metal layer where the critical timing path is located, the metal layer located at the upper layer of the metal layer where the critical timing path is located, and the metal layer located at the next layer of the metal layer where the critical timing path is located One or more dummy metals are arranged at positions outside the dummy metal barrier layer where the layout and wiring density is less than a preset density threshold.

In one embodiment, each of the dummy metals and their timing paths on the same metal layer are parallel to each other.

In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference may be made to the detailed description of the chip design method above, which will not be repeated here.

The chip design apparatus provided in the embodiment of the present application and the chip design method in the above embodiment belong to the same concept, and any method provided in the chip design method embodiment can be executed on the chip design apparatus. For details of the implementation process, see the chip design method embodiment, which is not repeated here.

It should be noted that, for the chip design method described in the embodiments of the present application, those of ordinary skill in the art can understand that all or part of the process for implementing the chip design method described in the embodiments of the present application can be controlled by a computer program. To complete, the computer program can be stored in a computer-readable storage medium, such as a memory, and executed by at least one processor, and the execution process can include processes such as the embodiments of the chip design method. . The storage medium may be a magnetic disk, an optical disk, a read only memory (ROM, Read Only Memory), a random access memory (RAM, Random Access Memory), and the like.

For the chip design apparatus of the embodiments of the present application, each functional module may be integrated into one processing chip, or each module may exist physically alone, or two or more modules may be integrated into one module. The above-mentioned integrated modules can be implemented in the form of hardware, and can also be implemented in the form of software function modules. If the integrated module is implemented in the form of a software function module and sold or used as an independent product, it can also be stored in a computer-readable storage medium, such as a read-only memory, a magnetic disk or an optical disk, etc. .

The chip design method, device, storage medium, and electronic device provided by the embodiments of the present application are described in detail above. The principles and implementations of the present application are described with specific examples. The descriptions of the above embodiments are only It is used to help understand the method and the core idea of the present application; meanwhile, for those skilled in the art, according to the idea of the present application, there will be changes in the specific embodiments and application scope. In summary, this specification The content should not be construed as a limitation on this application.

Claims (13)

1. a chip design method, applied to electronic equipment, is characterized in that, comprises: Determine the critical timing path in the layout and routing of the chip; setting a dummy metal barrier layer on the critical timing path; A dummy metal is arranged outside the range of the dummy metal barrier layer where the layout and wiring density is less than a preset density threshold. 2. The chip design method according to claim 1, wherein the determining the critical timing path in the layout and wiring of the chip comprises: Perform chip layout and wiring; generating a timing report according to the placement and routing data; Obtain the critical timing path according to the timing report. 3. The chip design method according to claim 2, wherein the acquiring the critical timing path according to the timing report comprises: A path whose slack value is less than a preset threshold is obtained from the timing report, and used as the critical timing path. 4. The chip design method according to claim 1, wherein the setting of a dummy metal barrier layer on the critical timing path comprises: The dummy metal barrier layer is disposed around the critical timing path. 5. The chip design method according to claim 4, wherein the disposing the dummy metal barrier layer around the critical timing path comprises: The dummy metal barrier layer is disposed around and above the critical timing path. 6 . The chip design method according to claim 5 , wherein the length of the dummy metal barrier layer is greater than the length of the critical timing path, and the width of the dummy metal barrier layer is greater than the width of the critical timing path. 7 . , the height of the dummy metal barrier layer is the metal layer where the critical timing path is located, the metal layer above the metal layer where the critical timing path is located, and the metal layer located below the metal layer where the critical timing path is located The sum of the heights of one metal layer. 7 . The chip design method according to claim 1 , wherein the shape of the critical timing path and the shape of the dummy metal barrier layer are both rectangular parallelepiped shapes. 8 . 8 . The chip design method according to claim 1 , wherein after the dummy metal barrier layer is provided on the critical timing path, the dummy metal barrier layer is used to protect the critical timing path, the Methods also include: The data of the layout and wiring after the dummy metal barrier layer is set is exported as a file in a preset format. 9 . The chip design method according to claim 8 , wherein the setting of the dummy metal outside the range of the dummy metal barrier layer where the layout and wiring density is less than a preset density threshold value comprises: 10 . detecting the position of the dummy metal barrier layer in the file of the preset format; In the metal layer where the critical timing path is located, the metal layer located at the upper layer of the metal layer where the critical timing path is located, and the metal layer located at the next layer of the metal layer where the critical timing path is located One or more dummy metals are arranged at positions outside the dummy metal barrier layer where the layout and wiring density is less than a preset density threshold. 10 . The chip design method according to claim 8 , wherein each dummy metal and its timing paths on the same metal layer are parallel to each other. 11 . 11. A chip design device, applied to electronic equipment, characterized in that, comprising: Determine the module to determine the critical timing path in the layout and routing of the chip; a first setting module, configured to set a dummy metal barrier layer on the critical timing path; The second setting module is configured to set dummy metal at a position outside the range of the dummy metal barrier layer where the layout and wiring density is less than a preset density threshold. 12. A computer-readable storage medium on which a computer program is stored, characterized in that, when the computer program is executed on a computer, the computer is made to execute the method described in any one of claims 1 to 10. Methods. 13. An electronic device comprising a memory and a processor, wherein the processor executes the method according to any one of claims 1 to 10 by invoking a computer program stored in the memory.

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