JP2009283618A - Method of designing layout for integrated circuit device and method of manufacturing the device, micro cell, integrated circuit device, and electronic device - Google Patents

Abstract

Provided are an integrated circuit device layout design method and manufacturing method, a macro cell, an integrated circuit device, and an electronic device that can easily find a macro cell arrangement error without increasing design man-hours.
An integrated circuit device layout design method according to the present invention provides a predetermined design in a part of a planned layout area of a macro cell in correspondence with a first dummy pattern that does not satisfy a predetermined design rule formed in a macro cell. A second dummy pattern that does not satisfy the rule is created (S20), a macro cell is arranged (S30), and it is checked whether the layout pattern after the macro cell arrangement satisfies a predetermined design rule (S40). The dummy pattern formed by the first and second dummy patterns satisfies a predetermined design rule when the macro cell is arranged in the planned arrangement area, and the dummy pattern is predetermined when the macro cell is not arranged in the planned arrangement area. Does not meet the design rules.
[Selection] Figure 3

Description

  The present invention relates to an integrated circuit device layout design method and manufacturing method, a macro cell, an integrated circuit device, and an electronic apparatus.

In order to suppress the increase in the number of product development man-hours associated with the increase in scale and multifunction of integrated circuit devices (LSIs), there is a circuit design method using a macro cell that realizes more complex functions by combining multiple basic function cells. Widely known. For example, macrocells such as communication interface circuits, memories, PLLs, and CPUs are widely used as LSI design assets, and the macrocells are also called IP (Intellectual Property) modules.
JP 2006-133835 A JP 2001-142923 A JP 2000-286342 A

  In an LSI design method using a macro cell, for example, a macro cell layout pattern is placed at a predetermined position in an LSI layout area, and necessary signal lines are connected to signal input / output ports formed on the layout pattern. LSI layout design is performed by creating a wiring pattern to be performed. Alternatively, after the wiring pattern is created in the LSI layout area, the layout of the LSI is designed by placing the macro cell at a predetermined position. At each stage of layout design, DRC (Design Rule Check) verification is performed at an appropriate timing in order to determine whether or not the created layout pattern satisfies the design rule. Then, LVS (Layout versus Schematic) verification is performed in which the layout pattern of the finally completed LSI is compared with the circuit connection information of the LSI, and the correctness of the final layout pattern is confirmed.

  However, in the conventional layout design method, even if the placement position of the macro cell is wrong, there is not always a design rule error in DRC verification. In particular, when there are a plurality of different types of macro cells with the same port position, it is easy to imagine a case in which a design rule error does not occur even if the type of macro cell to be arranged is wrong. Therefore, even if DRC verification is performed at each stage of layout design, there is a case where a macro cell arrangement error is not noticed until an error is confirmed in the final LVS verification result. For this reason, in the worst case, design man-hours may be expended for a large redo of the layout. Even if there is an error in the final LVS verification result, the layout pattern of the final LSI is complicated, so that there is a case where a wasteful analysis man-hour is spent assuming that a wiring error actually exists. In order to avoid such a situation, it is conceivable to perform not only DRC verification but also LVS verification at each stage of the layout. However, in order to perform LVS verification at each stage of layout, circuit connection information corresponding to the layout pattern at each stage must be created, which increases the number of design steps. Even if there is an error in the LVS verification result, it is difficult to avoid spending unnecessary analysis steps assuming that there is actually a wiring error. Furthermore, the execution time of the LVS verification is considerably longer than the execution time of the DRC verification, which causes an increase in design man-hours.

  The present invention has been made in view of the above problems, and a layout design method and a manufacturing method for an integrated circuit device that can easily find a macro cell arrangement error without substantially increasing the design man-hours. An object of the present invention is to provide a macro cell, an integrated circuit device, and an electronic device.

(1) The present invention
A layout design method for an integrated circuit device including a macro cell having layout pattern information,
The macro cell included in the layout area of the integrated circuit device in association with a first dummy pattern that does not satisfy a predetermined design rule formed in a layout pattern of at least one layer included in the layout pattern information of the macro cell. A dummy pattern creating step for creating a second dummy pattern that does not satisfy the predetermined design rule in a part of the arrangement planned area;
A macro cell placement step of placing the macro cell in a layout region of the integrated circuit device;
A design rule check step for checking whether or not a layout pattern of the integrated circuit device after the macro cell is arranged satisfies the predetermined design rule,
In the macro cell placement step,
When the macro cell is placed in the planned placement area, the dummy pattern formed by the first dummy pattern and the second dummy pattern satisfies the predetermined design rule, and the macro cell is placed in the planned placement area. If not arranged, the dummy pattern formed by the first dummy pattern and the second dummy pattern does not satisfy the predetermined design rule.

  For example, the first dummy pattern may be formed in any one layer such as a polysilicon wiring layer, a metal 1 wiring layer to a metal 6 wiring layer, or may be formed in two or more layers. Good.

  The first dummy pattern may be formed so as not to satisfy one type of design rule, or may be formed so as not to satisfy two or more types of design rules.

  The second dummy pattern may be created so as not to satisfy one type of design rule, or may be created so as not to satisfy two or more types of design rules.

  When the macro cell is arranged in the planned arrangement area, the dummy pattern formed by the first dummy pattern and the second dummy pattern may be formed so as to have a minimum value satisfying a predetermined design rule. . For example, the dummy pattern may be formed so that the line width or area thereof is the minimum line width or the minimum area that satisfies the design rule.

  According to the present invention, when the macro cell is correctly arranged in the planned arrangement area, the dummy pattern formed by the first dummy pattern and the second dummy pattern satisfies a predetermined design rule. On the other hand, since both the first dummy pattern and the second dummy pattern are formed so as not to satisfy the predetermined design rule, if the macro cell is not correctly arranged in the planned arrangement area, the first dummy pattern The dummy pattern formed by the second dummy pattern does not satisfy a predetermined design rule. Therefore, according to the present invention, a design rule check is performed on the layout pattern of the integrated circuit device after the macro cell is arranged to easily and surely check whether the macro cell is correctly arranged in the planned arrangement area. be able to.

  In addition, according to the present invention, before the final chip layout of the integrated circuit device is completed, the macro cell placement is performed by performing the design rule check on the layout pattern of the integrated circuit device after the placement of the macro cell. Misalignment can be detected early.

(2) The integrated circuit device layout design method of the present invention includes:
In the dummy pattern creating step,
The first dummy pattern may be created in the layout pattern of the at least one layer included in the layout pattern information of the macro cell.

(3) An integrated circuit device layout design method of the present invention includes:
In the dummy pattern creating step,
Creating a dummy pattern satisfying the predetermined design rule, dividing the dummy pattern to create the first dummy pattern and the second dummy pattern;
In the macro cell placement step,
When the macro cell is arranged in the arrangement planned area, the dummy pattern satisfying the predetermined design rule may be formed by the first dummy pattern and the second dummy pattern.

  The dummy pattern may be created so as to have a minimum value that satisfies a predetermined design rule. For example, the dummy pattern may be created so that the line width or area thereof is the minimum line width or the minimum area that satisfies the design rule.

  According to the present invention, first, after forming a dummy pattern satisfying a predetermined design rule, the dummy pattern is divided to create a first dummy pattern and a second dummy pattern. Therefore, if the dummy pattern is created so as to have a minimum value that satisfies the predetermined design rule, the first dummy pattern and the second dummy pattern that do not satisfy the predetermined design rule can be easily created.

(4) An integrated circuit device layout design method of the present invention includes:
The shapes of the first dummy pattern and the second dummy pattern may be non-linearly symmetric and astigmatic.

  According to the present invention, the shape of the first dummy pattern and the second dummy pattern is a layout pattern having a shape that is neither a line symmetry nor a point symmetry. A design rule error also occurs when placing. Therefore, before the final chip layout of the integrated circuit device is completed, a design rule check is performed on the layout of the integrated circuit device after the placement of the macro cell, so that an error in the placement direction of the macro cell can be detected early. can do.

(5) An integrated circuit device layout design method of the present invention includes:
The first dummy pattern is a layout pattern that can identify the type of the macro cell,
In the macro cell placement step,
When the macro cell is arranged in the planned arrangement area, a dummy pattern satisfying the predetermined design rule capable of identifying the type of the macro cell is formed by the first dummy pattern and the second dummy pattern. You may do it.

  The layout pattern that can identify the type of the macro cell may be a layout pattern in the shape of letters and numbers.

  According to the present invention, since the first dummy pattern is a layout pattern that can identify the type of the macro cell, a design rule error also occurs when an incorrect type of macro cell is arranged in the arrangement planned area. Therefore, before the final chip layout of the integrated circuit device is completed, a design rule check is performed on the layout of the integrated circuit device after the placement of the macro cell, so that an error in the type of the placed macro cell can be quickly detected. Can be found.

(6) The integrated circuit device layout design method of the present invention comprises:
The predetermined design rule may be at least one of a design rule that defines a line width of a layout pattern and a design rule that defines an area of the layout pattern.

  Both the first dummy pattern and the second dummy pattern may include a rectangular pattern in which the horizontal line width does not satisfy the design rule and a rectangular pattern in which the vertical line width does not satisfy the design rule. Good. These rectangular patterns may be formed such that the area does not satisfy the design rule. Further, when the macro cell is arranged in the arrangement planned area, the dummy pattern formed by the first dummy pattern and the second dummy pattern is a rectangular pattern having a minimum line width satisfying the design rule in the horizontal line width. In addition, the vertical line width may be formed so as to include a rectangular pattern having a minimum line width that satisfies the design rule. These rectangular patterns may be further formed so that the area thereof is the minimum area that satisfies the design rule.

  The first dummy pattern is configured by a rectangular pattern in which the horizontal line width and the vertical line width do not satisfy the design rule, and the second dummy pattern changes the shape of the first dummy pattern from the rectangular pattern. You may be comprised by the pattern of the hollow shape. Both the first dummy pattern and the second dummy pattern may be formed so that the area does not satisfy the design rule. Further, when the macro cell is arranged in the arrangement planned area, the dummy pattern formed by the first dummy pattern and the second dummy pattern has a design rule for both the horizontal line width and the vertical line width. You may make it form as a rectangular pattern of the minimum line | wire width to satisfy | fill. This rectangular pattern may be formed so that the area thereof is the minimum area that satisfies the design rule.

  As described above, both the first dummy pattern and the second dummy pattern are configured such that the horizontal line width and the vertical line width do not satisfy the design rule, and the macro cell is arranged in the planned arrangement area. If the area of the dummy pattern formed by the first dummy pattern and the second dummy pattern is the minimum area satisfying the design rule, the macro cell is arranged with a slight deviation from the planned arrangement area. A dummy pattern that does not satisfy at least one of the line width and area design rules is formed. Therefore, it is possible to easily find the displacement of the macro cell.

(7) The present invention
Designing a layout pattern of the integrated circuit device by the layout design method according to any one of the above,
Creating a photomask on which the layout pattern is drawn;
Forming an integrated circuit on a semiconductor substrate using the photomask. A method for manufacturing an integrated circuit device, comprising:

(8) The present invention
A macrocell used in the design of an integrated circuit device,
It includes layout pattern information in which a dummy pattern that does not satisfy a predetermined design rule is formed in a layout pattern of at least one layer.

(9) In the macro cell of the present invention,
The shape of the dummy pattern may be non-linearly symmetric and astigmatic.

(10) In the macro cell of the present invention,
The dummy pattern may be a layout pattern that can identify the type of the macro cell.

(11) In the macro cell of the present invention,
The predetermined design rule may be at least one of a design rule that defines a line width of a layout pattern and a design rule that defines an area of the layout pattern.

(12) The present invention
An integrated circuit device including the macro cell according to any one of the above.

(13) The present invention provides:
An integrated circuit device as described above;
Data input means to be processed by the integrated circuit device;
An electronic device comprising: output means for outputting data processed by the integrated circuit device.

  DESCRIPTION OF EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings. The embodiments described below do not unduly limit the contents of the present invention described in the claims. Moreover, not all of the configurations described below are essential constituent requirements of the present invention.

1. Macro cell (IP module)
FIG. 1 is a diagram for explaining a macro cell (IP module) of the present embodiment.

  The macro cell 1 includes circuit connection information 10, layout pattern information 20, simulation delay information 30, and the like.

  The circuit connection information 10 is information that defines a plurality of elements included in a circuit for realizing the function of the macro cell 1 and a net that connects the elements. The circuit connection information 10 may be, for example, analog circuit connection information that defines elements such as transistors, resistors, capacitors, etc. and a net connected between these elements. Further, the circuit connection information 10 may be, for example, digital circuit connection information that defines a logic element and a net connecting between these elements. The circuit connection information 10 may be, for example, a Verilog netlist file.

  The layout pattern information 20 is information including a layout pattern for each layer such as a polysilicon layer or a metal wiring layer. In the macro cell 1, a dummy pattern (first dummy pattern) is formed in a layout pattern of at least one layer (for example, a metal 5 wiring layer). Here, the dummy pattern is a pattern that is not required in order to realize the original function of the macro cell 1 (function exhibited based on circuit connection information). The layout pattern information 20 may be a GDSII file, for example.

  The simulation delay information 30 is information that defines the time during which a signal propagates between the nets defined in the circuit connection information 10, and is used when a logic simulation or a circuit simulation is executed. The time for which the signal propagates between the nets defined in the circuit connection information 10 is calculated based on, for example, the parasitic capacitance and parasitic resistance extracted from the layout pattern information 20. The simulation delay information 30 may be, for example, an SDF file.

  2A to 2D show examples of the first dummy pattern included in the layout pattern information of the macro cell. The first dummy pattern is formed so as not to satisfy a predetermined design rule in the layout pattern of at least one layer (for example, a metal 5 wiring layer). As shown in FIGS. 2A to 2D, the first dummy pattern has, for example, the minimum line width allowed for the layout pattern of one layer (for example, the minimum line of metal five-layer wiring) It may be formed so as not to satisfy the design rule (Minimum-Width rule) that defines (width). Further, the first dummy pattern may be formed so as not to satisfy a design rule (Minimum-Area rule) that defines a minimum area allowed for a layout pattern of one layer, for example. Further, the first dummy pattern may be formed so as not to satisfy both the Minimum-Width rule and the Minimum-Area rule with respect to the layout pattern of one layer, for example.

  A first dummy pattern 100 shown in FIG. 2A is composed of 13 rectangular patterns 101 to 113. The 13 rectangular patterns 101 to 113 may be formed in one layer, or may be formed in two or more layers. For example, the patterns 101, 103, 105, 107, 109, 111, 113 may be formed in the metal 6 wiring layer, and the patterns 102, 104, 106, 108, 110, 112 may be formed in the metal 5 wiring layer.

Here, the lengths (line widths) w ₁ , w ₄ , w ₆ , and w ₁₁ of the vertical sides of each of the rectangular patterns 101, 104, 106, and 111 are smaller than the minimum line width allowed in the design rule. On the other hand, the length (line width) w ₂ , w ₃ , w ₅ , w _7, w ₈ , w of each horizontal side of each of the rectangular patterns 102, 103, 105, 107, 108, 109, 110, 112, 113. _{9, w 10, w 12,} w 13 is smaller than the minimum line width allowed in the design rule. That is, all the rectangular patterns 101 to 113 are formed so as not to satisfy the Minimum-Width rule.

  Furthermore, the area of each of the rectangular patterns 101 to 113 is smaller than the minimum area allowed in the design rule. That is, all the rectangular patterns 101 to 113 are formed so as not to satisfy the Minimum-Area rule.

  Accordingly, the first dummy pattern 100 does not satisfy both the Minimum-Width rule and the Minimum-Area rule.

  The first dummy pattern 100 has a shape in which the characters “P01” are formed by the rectangular patterns 101 to 113. Here, the character “P01” is a character that can identify the type of the macro cell. That is, the first dummy pattern 100 of the macro cell 1 has a shape of “P01”, but the first dummy patterns of other types of macro cells are, for example, “P02”, “P03”,.・ It has a shape that is different from “P01”. In this way, by forming the first dummy pattern in the shape of the unique character representing the type of the macro cell in the layout pattern information of the macro cell, the type of the macro cell can be easily visually determined from the layout pattern information. Can be identified.

  The first dummy pattern 120 shown in FIG. 2B is composed of ten rectangular patterns 121-130. The ten rectangular patterns 121 to 130 may be formed in one layer, or may be formed in two or more layers. For example, the patterns 121, 123, 125, 127, and 129 may be formed in the metal 6 wiring layer, and the patterns 122, 124, 126, 128, and 130 may be formed in the metal 5 wiring layer.

Here, the lengths (line widths) w ₄ and w ₆ of the vertical sides of each of the rectangular patterns 124 and 126 are smaller than the minimum line width allowed in the design rule. On the other hand, the lengths (line widths) w ₁ , w ₂ , w ₃ , w _5, w ₇ , w ₈ , of the horizontal sides of each of the rectangular patterns 121, 122, 123, 125, 127, 128, 129, 130, w ₉ and w ₁₀ are smaller than the minimum line width allowed in the design rule. That is, the rectangular patterns 121 to 130 are all formed so as not to satisfy the Minimum-Width rule.

  Furthermore, the area of each of the rectangular patterns 121 to 130 is smaller than the minimum area allowed in the design rule. That is, the rectangular patterns 121 to 130 are all formed so as not to satisfy the Minimum-Area rule.

  Further, the shape of the dummy pattern 120 is unique to the macro cell 1, and the shape of the dummy pattern of another type of macro cell may be different from the shape of the dummy pattern 120. As described above, by forming the first dummy pattern having a unique shape representing the type of the macro cell in the layout pattern information of the macro cell, the type of the macro cell can be visually identified from the layout pattern information.

  The first dummy pattern 140 shown in FIG. 2C is composed of one L-shaped pattern 141.

Here, the line widths w ₁ and w ₂ of the L-shaped pattern 141 are smaller than the minimum line width allowed in the design rule. That is, the L-shaped pattern 141 is formed so as not to satisfy the Minimum-Width rule.

  Furthermore, the area of the L-shaped pattern 141 is smaller than the minimum area allowed in the design rule. That is, the L-shaped pattern 141 is formed so as not to satisfy the Minimum-Area rule.

  Therefore, the first dummy pattern 140 does not satisfy both the Minimum-Width rule and the Minimum-Area rule.

  Note that the area of the L-shaped pattern 141 may be greater than or equal to the minimum area allowed in the design rule. That is, the L-shaped pattern 141 may be formed so as to satisfy the Minimum-Area rule. In that case, the first dummy pattern 140 does not satisfy the Minimum-Width rule but satisfies the Minimum-Area rule.

  The first dummy pattern 160 shown in FIG. 2D is composed of two rectangular patterns 161 and 162. The two rectangular patterns 161 and 162 may be formed in one layer, or may be formed in two or more layers. For example, the pattern 161 may be formed in the metal 6 wiring layer, and the pattern 162 may be formed in the metal 5 wiring layer.

Here, the length (line width) w ₁ of the horizontal side of the rectangular pattern 161 is smaller than the minimum line width allowed in the design rule. On the other hand, the length of the longitudinal sides of the rectangular pattern 162 (line width) w ₂ is less than the minimum line width allowed in the design rule. That is, the rectangular patterns 161 and 162 are both formed so as not to satisfy the Minimum-Width rule.

  Further, the area of each of the rectangular patterns 161 and 162 is smaller than the minimum area allowed in the design rule. That is, the rectangular patterns 161 and 162 are both formed so as not to satisfy the Minimum-Area rule.

  Therefore, the first dummy pattern 160 does not satisfy both the Minimum-Width rule and the Minimum-Area rule.

2. Integrated Circuit Device Layout Design Method FIG. 3 is a flowchart for explaining the integrated circuit device layout design method of this embodiment.

  First, in the layout pattern of at least one layer included in the layout pattern information of the macro cell (IP module), a first dummy pattern that does not satisfy a predetermined design rule is created (step S10). For example, in the layout pattern of at least one layer included in the layout pattern information of the macro cell (IP module), any one of the dummy patterns (Minimum-Width rule and Minimum-Area rule) shown in FIGS. (A dummy pattern that does not satisfy at least one of the above) may be created as the first dummy pattern.

  Next, in correspondence with the first dummy pattern, a second dummy pattern that does not satisfy the predetermined design rule is created in a part of the planned layout area of the macro cell (IP module) included in the layout area of the integrated circuit device. (Step S20). Steps S10 and S20 correspond to a dummy pattern creation step.

  Next, a macro cell (IP module) is arranged in the layout area of the integrated circuit device (step S30). Step S30 corresponds to a macro cell placement step.

  Next, it is checked whether or not the layout pattern of the integrated circuit device after the macro cell (IP module) is arranged in step S30 satisfies a predetermined design rule (step S40). Step S40 corresponds to a design rule check step.

  If the macro cell is correctly placed in the planned placement area in step S30, the dummy pattern formed by the first dummy pattern created in step S10 and the second dummy pattern created in step S20 has a predetermined design rule. Fulfill. On the other hand, since both the first dummy pattern and the second dummy pattern are formed so as not to satisfy the predetermined design rule, if the macro cell is not correctly arranged in the arrangement planned area in step S30, the first dummy pattern and the second dummy pattern are displayed. The dummy pattern formed by the dummy pattern and the second dummy pattern do not satisfy a predetermined design rule. Therefore, it is possible to easily and surely check whether or not the macro cell is correctly arranged in the planned arrangement area by executing the design rule check on the layout pattern of the integrated circuit device after the macro cell is arranged.

  If an error relating to a predetermined design rule exists (Yes in step S50), the arrangement position of the macro cell (IP module) is corrected (step S60), and the design rule check step in step S40 is executed again.

  On the other hand, if there is no error relating to the predetermined design rule (No in step S50), the process ends.

  FIGS. 4A to 4D are diagrams illustrating examples of the second dummy pattern created in step S20 of the flowchart of FIG.

  The dummy pattern shown in FIGS. 4A to 4D is one of the planned arrangement regions where the macro cells in which the first dummy patterns of FIGS. 2A to 2D are formed are arranged. FIG. 3B is an example of a second dummy pattern created corresponding to the first dummy pattern in FIGS. 2A to 2D in the area of the portion.

  The second dummy pattern is created so as not to satisfy a predetermined design rule. For example, as shown in FIGS. 4A to 4D, the second dummy pattern includes a design rule (Minimum-Width rule) that defines the minimum line width of the layout pattern and a minimum area (Minimum of the layout pattern). -Area rule) may be created so as not to satisfy at least one design rule.

  The second dummy pattern 200 shown in FIG. 4A is composed of 13 rectangular patterns 201-213. The 13 rectangular patterns 201 to 213 may be formed in one layer, or may be formed in two or more layers. However, the rectangular patterns 201 to 213 are formed in the same layer as the rectangular patterns 101 to 113 in FIG. For example, the rectangular patterns 101, 103, 105, 107, 109, 111, and 113 in FIG. 2A are formed in the metal 6 wiring layer, and the patterns 102, 104, 106, 108, 110, and 112 are formed in the metal 5 wiring layer. If formed, the patterns 201, 203, 205, 207, 209, 211, and 213 are formed in the metal 6 wiring layer, and the patterns 202, 204, 206, 208, 210, and 212 are formed in the metal 5 wiring layer. Is done.

Here, the shapes of the rectangular patterns 201 to 213 are the same as the shapes of the rectangular patterns 101 to 113 constituting the first dummy pattern 100 of FIG. That is, the rectangular patterns 201 to 213 are formed such that the widths w _{1 to} w ₁₃ do not satisfy the Minimum-Width rule. The rectangular patterns 201 to 213 are all formed so as not to satisfy the Minimum-Area rule.

  The second dummy pattern 200 has a shape in which the characters “P01” are taken by the rectangular patterns 201 to 213. Here, the characters “P01” indicate the type of macro cell to be placed in the planned placement area. When another type of macro cell is placed in the planned placement area, the second dummy pattern has a shape that is different from “P01” such as “P02”, “P03”,. I am doing. In this way, by creating the second dummy pattern having a shape indicating the type of macro cell, the type of macro cell to be placed in the placeable area can be easily identified visually.

  The second dummy pattern 220 shown in FIG. 4B is composed of ten rectangular patterns 221 to 230. The ten rectangular patterns 221 to 230 may be formed in one layer, or may be formed in two or more layers. However, the rectangular patterns 221 to 230 are formed in the same layer as the rectangular patterns 121 to 130 in FIG. For example, when the rectangular patterns 121, 123, 125, 127, and 129 of FIG. 2B are formed in the metal 6 wiring layer, and the patterns 122, 124, 126, 128, and 130 are formed in the metal 5 wiring layer. The patterns 221, 223, 225, 227, and 229 are formed in the metal 6 wiring layer, and the patterns 222, 224, 226, 228, and 230 are formed in the metal 5 wiring layer.

Here, the shapes of the rectangular patterns 221 to 230 are the same as the shapes of the rectangular patterns 121 to 130 constituting the first dummy pattern 120 of FIG. That is, the rectangular patterns 221 to 230 are formed such that the widths w _{1 to} w ₁₀ do not satisfy the Minimum-Width rule. The rectangular patterns 221 to 230 are all formed so as not to satisfy the Minimum-Area rule.

  The shape of the second dummy pattern 220 is unique to each type of macro cell to be arranged in the planned arrangement area. When another type of macro cell is arranged in the planned arrangement area, the second dummy pattern 220 The shape is created so as to be different from the shape of the dummy pattern 220. In this manner, if the second dummy pattern having a different shape is created for each type of macro cell to be arranged, it can be visually identified whether the macro cell to be arranged is a macro cell to be arranged.

  The second dummy pattern 240 shown in FIG. 4C includes a pattern 241 obtained by hollowing out an L-shaped pattern from a rectangular pattern. The pattern 241 is formed in the same layer as the L-shaped pattern 141 in FIG. Here, the L-shaped shape cut out in the pattern 241 is the same as the L-shaped pattern 241 in FIG.

In addition, the widths w _{1 to} w ₄ of the pattern 241 are smaller than the minimum line width allowed in the design rule. That is, the pattern 241 is formed so as not to satisfy the Minimum-Width rule. Further, the area of the pattern 241 is smaller than the minimum area allowed in the design rule. That is, the pattern 241 is formed so as not to satisfy the Minimum-Area rule.

  Note that the area of the pattern 241 may be equal to or larger than the minimum area allowed in the design rule. That is, the pattern 241 may be formed so as to satisfy the Minimum-Area rule. In that case, the second dummy pattern 240 does not satisfy the Minimum-Width rule but satisfies the Minimum-Area rule.

  The second dummy pattern 260 shown in FIG. 4D is composed of two rectangular patterns 261 and 262. The two rectangular patterns 261 and 262 may be formed in one layer, or may be formed in two or more layers. However, the rectangular patterns 261 and 262 are formed in the same layer as the rectangular patterns 161 and 162 in FIG. For example, when the rectangular pattern 161 of FIG. 2D is formed in the metal 6 wiring layer and the pattern 162 is formed in the metal 5 wiring layer, the pattern 261 is formed in the metal 6 wiring layer, and the pattern 262 is It is formed in the metal 5 wiring layer.

Here, the shapes of the rectangular patterns 261 and 262 are the same as the shapes of the rectangular patterns 161 and 162 in FIG. That is, the rectangular patterns 261 and 262 are formed so that the widths w ₁ and w ₄ do not satisfy the Minimum-Width rule. The rectangular patterns 261 and 262 are both formed so as not to satisfy the Minimum-Area rule.

  FIGS. 5A and 5B are diagrams illustrating an example in which macro cells are arranged in the layout region of the integrated circuit device in step S30 of the flowchart of FIG.

  As shown in FIG. 5A, in step S10 of the flowchart of FIG. 3, for example, the first dummy pattern 100 of FIG. 2A is created in the layout pattern information 20 of the macro cell 1. On the other hand, in step S20 of the flowchart of FIG. 3, for example, the second dummy pattern 200 of FIG. 4A is created in a part of the layout planned area 310 of the macro cell 1 in the layout area 300 of the integrated circuit device. .

  Further, in the layout area 300 of the integrated circuit device, a layout pattern 320 of a high voltage power supply line (VDD power supply) and a layout pattern 330 of a low voltage power supply line (VDD power supply) for supplying power to the macrocell 1 and the macrocell 1 The signal line layout patterns 340, 342, 344, and 346 connected to the input ports and output ports may be formed. For example, when a new product is developed by replacing an IP included in an existing product with another type of IP, the power line layout patterns 320 and 330 and the signal line layout pattern 340 are arranged before the IP is arranged. 342, 344, 346 may be formed. Note that, after the macro cell 1 is arranged, the power line layout patterns 320 and 330 and the signal line layout patterns 340, 342, 344, and 346 may be created.

  In step S30 of the flowchart of FIG. 3, the macro cell 1 is arranged in the layout region 300 of the integrated circuit device. Here, normally, the macro cell 1 is arranged so that the reference point 50 of the macro cell 1 coincides with the position 350 indicated by the coordinates (X, Y) on the layout area 300 specified by the user (automatic arrangement or manual arrangement). Is done. Therefore, if the setting of the position 350 is correct and the reference point 50 of the macro cell 1 coincides with the position 350, the macro cell 1 is correctly arranged in the planned arrangement area 200. FIG. 5B shows an example of the layout pattern of the integrated circuit device after the macro cell 1 is correctly placed in the planned placement area 200. When the macro cell 1 is correctly arranged in the planned arrangement area 200, the dummy pattern 400 formed by the first dummy pattern 100 and the second dummy pattern 200 satisfies a predetermined design rule. On the other hand, when the macro cell 1 is not correctly arranged in the arrangement planned area 200, the dummy pattern formed by the first dummy pattern 100 and the second dummy pattern 200 does not satisfy a predetermined design rule.

  Further, when different first dummy patterns are formed for each type of macro cell, even if the wrong type of macro cell is correctly arranged in the planned arrangement region, it is formed by the first dummy pattern and the second dummy pattern. Dummy pattern does not meet the design rules.

  6A to 6C are diagrams for explaining a dummy pattern formed by the first dummy pattern in FIG. 2A and the second dummy pattern in FIG. 4A. .

  FIG. 6A is a diagram showing a dummy pattern formed when the macro cell is correctly arranged in the planned arrangement area.

  In the dummy pattern 400, the 13 rectangular patterns 101 to 113 constituting the first dummy pattern 100 and the 13 rectangular patterns 201 to 213 constituting the second dummy pattern 200 are in contact with each other in the vertical direction or the horizontal direction. 13 rectangular patterns formed by All 13 rectangular patterns included in the dummy pattern 400 satisfy the Minimum-Width rule and the Minimum-Area rule. Here, in the 13 rectangular patterns included in the dummy pattern 400, at least one of the width and the area may be the minimum value allowed by the design rule. For example, the rectangular pattern formed by the rectangular patterns 101 and 201 may be formed so that the width thereof is the minimum value allowed by the design rule. Further, the rectangular pattern formed by the rectangular patterns 102 and 202 may be formed so that the area thereof is the minimum value allowed by the design rule (and the width is also the minimum allowed by the design rule). Value).

  FIG. 6B is a diagram showing a dummy pattern that is formed when the macro cell is arranged so as to be shifted in the horizontal direction with respect to the planned arrangement area.

  The dummy pattern 400 'does not satisfy the Minimum-Width rule and the Minimum-Area rule. For example, the pattern formed by the rectangular patterns 101 and 201 does not satisfy the Minimum-Width rule. Further, since the rectangular patterns 103 and 203 are not in contact with each other, they become two independent patterns, and both do not satisfy the Minimum-Width rule and the Minimum-Area rule.

  FIG. 6C is a diagram showing a dummy pattern that is formed when the macro cell is arranged so as to be shifted in the vertical direction with respect to the arrangement planned area.

  The dummy pattern 400 ″ does not satisfy the Minimum-Width rule and the Minimum-Area rule. For example, the pattern formed by the rectangular patterns 102 and 202 does not satisfy the Minimum-Width rule. Further, since the rectangular patterns 104 and 204 are not in contact with each other, they become two independent patterns, and both do not satisfy the Minimum-Width rule and the Minimum-Area rule.

  FIGS. 7A to 7C are diagrams for explaining a dummy pattern formed by the first dummy pattern of FIG. 2B and the second dummy pattern of FIG. 4B. .

  FIG. 7A is a diagram showing a dummy pattern formed when a macro cell is correctly arranged in a planned arrangement area.

  In the dummy pattern 420, the ten rectangular patterns 121 to 130 constituting the first dummy pattern 120 and the ten rectangular patterns 221 to 230 constituting the second dummy pattern 220 are in contact with each other in the vertical direction or the horizontal direction. 10 rectangular patterns formed by All ten rectangular patterns included in the dummy pattern 420 satisfy the Minimum-Width rule and the Minimum-Area rule. Here, the ten rectangular patterns included in the dummy pattern 420 may be such that at least one of the width and the area is the minimum value allowed by the design rule. For example, the rectangular pattern formed by the rectangular patterns 121 and 221 may be formed so that the width becomes the minimum value allowed by the design rule. Further, the rectangular pattern formed by the rectangular patterns 122 and 222 may be formed such that the area thereof is the minimum value allowed by the design rule (and the width is also the minimum allowable by the design rule). Value).

  FIG. 7B is a diagram showing a dummy pattern that is formed when the macro cell is arranged so as to be shifted in the horizontal direction with respect to the planned arrangement area.

  The dummy pattern 420 'does not satisfy the Minimum-Width rule and the Minimum-Area rule. For example, the pattern formed by the rectangular patterns 124 and 224 does not satisfy the Minimum-Width rule. The rectangular patterns 122 and 222 partially overlap. Accordingly, when both the width and area of the rectangular pattern formed by the rectangular patterns 122 and 222 in FIG. 7A are the minimum values allowed by the design rule, the rectangular patterns 122 and 222 in FIG. The formed rectangular pattern does not satisfy the Minimum-Width rule and Minimum-Area rule.

  FIG. 7C is a diagram showing a dummy pattern that is formed when the macro cell is arranged so as to be shifted in the vertical direction with respect to the arrangement planned area.

  The dummy pattern 420 ″ does not satisfy the Minimum-Width rule and the Minimum-Area rule. For example, the pattern formed by the rectangular patterns 121 and 221 does not satisfy the Minimum-Width rule. Further, since the rectangular patterns 126 and 226 are not in contact with each other, they become two independent patterns, and both do not satisfy the Minimum-Width rule and the Minimum-Area rule.

  FIGS. 8A to 8C are diagrams for explaining a dummy pattern formed by the first dummy pattern of FIG. 2C and the second dummy pattern of FIG. 4C. .

  FIG. 8A is a diagram showing a dummy pattern formed when the macro cell is correctly arranged in the planned arrangement area.

  The dummy pattern 440 is formed as a rectangular pattern by the first dummy pattern 140 (L-shaped pattern 141) being closely fitted to the second dummy pattern 240 (pattern 241 obtained by hollowing out an L-shaped pattern from the rectangular pattern). Is done. The dummy pattern 440 satisfies the Minimum-Width rule and the Minimum-Area rule. The dummy pattern 440 may be formed such that the width and area are the minimum values allowed by the design rule.

  FIG. 8B is a diagram showing a dummy pattern that is formed when the macro cell is arranged so as to be shifted in the horizontal direction with respect to the planned arrangement area.

The dummy pattern 440 ′ does not satisfy the Minimum-Width rule in the widths w ₁ , w ₂ , w ₃ , and w ₄ . Further, the dummy pattern 440 ′ is formed so that the first dummy pattern 140 (L-shaped pattern 141) and the second dummy pattern 240 (pattern 241 obtained by hollowing out the L-shaped pattern from the rectangular pattern) partially overlap. Is formed. Therefore, when the area of the dummy pattern 440 in FIG. 8A is the minimum value allowed by the design rule, the dummy pattern 440 ′ in FIG. 8B does not satisfy the Minimum-Area rule.

  FIG. 8C is a diagram showing a dummy pattern that is formed when the macro cell is arranged so as to be shifted in the vertical direction and the horizontal direction with respect to the planned arrangement region.

The dummy pattern 440 ″ is formed so that the first dummy pattern 140 (L-shaped pattern 141) and the second dummy pattern 240 (pattern 241 obtained by hollowing out the L-shaped pattern from the rectangular pattern) are in contact with each other. . Therefore, since the area of the dummy pattern 440 ″ is the same as the area of the dummy pattern 440 in FIG. 8A, the dummy pattern 440 ″ satisfies the Minimum-Area rule. However, the dummy pattern 440 ″ does not satisfy the Minimum-Width rule in the widths w ₁ , w ₂ , w ₃ , and w ₄ .

  9A to 9C are diagrams for explaining a dummy pattern formed by the first dummy pattern in FIG. 2D and the second dummy pattern in FIG. 4D. .

  FIG. 9A is a diagram showing a dummy pattern formed when a macro cell is correctly arranged in a planned arrangement area.

  In the dummy pattern 460, the two rectangular patterns 161 and 162 constituting the first dummy pattern 160 and the two rectangular patterns 261 and 262 constituting the second dummy pattern 260 are in contact with each other in the horizontal direction and the vertical direction, respectively. Including two rectangular patterns. Both of the two rectangular patterns included in the dummy pattern 460 satisfy the Minimum-Width rule and the Minimum-Area rule. Here, in the two rectangular patterns included in the dummy pattern 460, at least one of the width and the area may be a minimum value allowed by the design rule. Further, the two rectangular patterns included in the dummy pattern 460 may have minimum values allowed by the design rule for both width and area.

  FIG. 9B is a diagram showing a dummy pattern formed when the macro cell is arranged so as to be shifted in the horizontal direction with respect to the planned arrangement area.

The two patterns included in the dummy pattern 460 ′ are formed such that the rectangular patterns 161 and 261 and the rectangular patterns 162 and 262 are in contact with each other. Therefore, in the dummy pattern 460 in FIG. 9A and the dummy pattern 460 ′ in FIG. 9B, the areas of the patterns formed by the rectangular patterns 161 and 261 are the same. Similarly, in the dummy pattern 460 in FIG. 9A and the dummy pattern 460 ′ in FIG. 9B, the areas of the patterns formed by the rectangular patterns 162 and 262 are the same. Accordingly, the dummy pattern 460 ′ satisfies the Minimum-Area rule. However, the dummy pattern 460 ′ does not satisfy the Minimum-Width rule in the widths w ₁ and w ₂ of the pattern formed by the rectangular patterns 162 and 262.

  FIG. 9C is a diagram showing a dummy pattern that is formed when the macro cell is arranged so as to be shifted in the vertical direction with respect to the arrangement planned area.

The two patterns included in the dummy pattern 460 ″ are formed such that the rectangular patterns 161 and 261 and the rectangular patterns 162 and 262 are in contact with each other. Therefore, in the dummy pattern 460 in FIG. 9A and the dummy pattern 460 ″ in FIG. 9C, the areas of the patterns formed by the rectangular patterns 161 and 261 are the same. Similarly, in the dummy pattern 460 of FIG. 9A and the dummy pattern 460 ″ of FIG. 9C, the areas of the patterns formed by the rectangular patterns 162 and 262 are the same. Accordingly, the dummy pattern 460 ″ satisfies the Minimum-Area rule. However, the dummy pattern 460 ″ does not satisfy the Minimum-Width rule in the widths w ₁ and w ₂ of the pattern formed by the rectangular patterns 161 and 261.

  As described above, according to the integrated circuit device design method of the present embodiment, when the macro cell 1 is correctly arranged in the arrangement planned area 310, the first dummy patterns 100, 120, 140, 160 and The dummy patterns 400, 420, 440, and 460 formed by the two dummy patterns 200, 220, 240, and 260 satisfy the Minimum-Width rule and the Minimum-Area rule, respectively. On the other hand, the first dummy patterns 100, 120, 140, 160 and the second dummy patterns 200, 220, 240, 260 are all formed so as not to satisfy at least one of the Minimum-Width rule and the Minimum-Area rule. Therefore, if the macro cell 1 is not correctly placed in the planned placement area 310, the dummy formed by the first dummy patterns 100, 120, 140, 160 and the second dummy patterns 200, 220, 240, 260, respectively. The patterns 400 ′, 420 ′, 440 ′, 460 ′ or 400 ″, 420 ″, 440 ″, 460 ″, etc. do not satisfy at least one of the Minimum-Width rule and the Minimum-Area rule. Therefore, according to the integrated circuit device design method of the present embodiment, the macro cell 1 is correctly placed in the planned placement region 310 by executing the design rule check on the layout pattern of the integrated circuit device after the macro cell 1 is placed. It is possible to easily and reliably check whether or not it has been done.

  Also, according to the integrated circuit device design method of the present embodiment, the design rule check is performed on the layout pattern of the integrated circuit device after the macro cell 1 is arranged before the final chip layout of the integrated circuit device is completed. By executing the above, it is possible to detect the displacement of the macro cell 1 at an early stage.

  The first dummy patterns 100, 120, 140, and 160 are layout patterns having shapes that are neither line-symmetric nor point-symmetric. Therefore, according to the design method of the integrated circuit device of the present embodiment, the design rule check is executed on the layout pattern of the integrated circuit device after the macro cell 1 is placed, so that the mistake in the placement direction of the macro cell 1 is avoided. It can be easily checked.

  FIGS. 10A and 10B are diagrams for explaining a dummy pattern formed by the first dummy pattern and the second dummy pattern when the type of the macro cell to be arranged is wrong.

  FIG. 10A is a diagram illustrating an example of a first dummy pattern formed in a macro cell of a different type from the macro cell 1 in which the first dummy pattern in FIG. 2A is formed.

  The first dummy pattern 180 is composed of 16 rectangular patterns 181 to 196.

Here, the length (line width) w ₁ , w ₄ , w ₆ , w ₁₁ , w ₁₂ , w ₁₄ , w of each vertical side of each of the rectangular patterns 181, 184, 186, 191, 192, 194, 196 ₁₆ is smaller than the minimum line width allowed in the design rule. On the other hand, the length (line width) w ₂ , w ₃ , w ₅ , w _7, w ₈ , w of each side of each of the rectangular patterns 182, 183, 185, 187, 188, 189, 190, 193, 195 ₉ , w ₁₀ , w _{13, and} w ₁₅ are smaller than the minimum line width allowed in the design rule. That is, the rectangular patterns 181 to 196 are all formed so as not to satisfy the Minimum-Width rule.

  Further, the area of each of the rectangular patterns 181 to 196 is smaller than the minimum area allowed in the design rule. That is, the rectangular patterns 181 to 196 are all formed so as not to satisfy the Minimum-Area rule.

  Therefore, the first dummy pattern 180 does not satisfy both the Minimum-Width rule and the Minimum-Area rule. Note that the rectangular patterns 181 to 191 may have the same size and the same shape as the rectangular patterns 101 to 111 in FIG.

  Further, the first dummy pattern 180 has a shape in which the characters “P02” are taken by the rectangular patterns 181 to 196. Here, the character “P02” is a character that can identify the type of the macro cell.

  FIG. 10B is a diagram showing a dummy pattern formed when a wrong type of macro cell is arranged in the planned arrangement area.

  In the dummy pattern 480, 11 rectangular patterns 181 to 191 included in the first dummy pattern 180 and 11 rectangular patterns 201 to 211 included in the second dummy pattern 200 are in contact with each other in the vertical direction or the horizontal direction. 11 rectangular patterns formed by These eleven rectangular patterns satisfy the Minimum-Width rule and the Minimum-Area rule. However, a pattern formed by the five rectangular patterns 192 to 196 included in the first dummy pattern 180 and the two rectangular patterns 212 and 213 included in the second dummy pattern 200 is a minimum-width rule and a minimum. -Area rules are not met.

  According to the design method of the integrated circuit device of this embodiment, since the first dummy pattern 100 is a layout pattern that can identify the type of the macro cell 1, when the wrong type of macro cell is arranged in the arrangement planned area 310, the first dummy pattern 100 can be identified. Even a design rule error occurs. Therefore, before the final chip layout of the integrated circuit device is completed, a design rule check is performed on the layout of the integrated circuit device after the placement of the macro cell, so that an error in the type of the placed macro cell can be quickly detected. Can be found.

  FIG. 11 is a flowchart for explaining a modified example of the layout design method of the integrated circuit device of the present embodiment.

  First, a dummy pattern that satisfies a predetermined design rule is created (step S100). For example, the dummy pattern 400 shown in FIG. 6A (dummy pattern satisfying the Minimum-Width rule and the Minimum-Area rule) may be created.

  Next, the dummy pattern created in step S100 is divided, and a first dummy pattern that does not satisfy the predetermined design rule (a dummy pattern that does not satisfy the Minimum-Width rule and the Minimum-Area rule) and a second dummy pattern ( A dummy pattern that does not satisfy the Minimum-Width rule and Minimum-Area rule is created (step S102). For example, the dummy pattern 400 in FIG. 6A may be divided to create the first dummy pattern 100 in FIG. 2A and the second dummy pattern 200 in FIG.

  Next, the first dummy pattern created in step S102 is placed on at least one layer included in the layout pattern information of the macro cell (IP module) (step S110).

  Next, in correspondence with the first dummy pattern, the second dummy pattern created in Step S102 is arranged in a part of the planned arrangement area of the macro cell (IP module) included in the layout area of the integrated circuit device (Step S102). S120). Steps S100, S102, S110, and S120 correspond to a dummy pattern creation step.

  Next, a macro cell (IP module) is arranged in the layout area of the integrated circuit device (step S130). Step S130 corresponds to a macro cell placement step.

  Next, it is checked whether or not the layout pattern of the integrated circuit device after the macro cell (IP module) is arranged in step S130 satisfies a predetermined design rule (step S140). Step S140 corresponds to a design rule check step.

  If the macro cell is correctly arranged in the planned arrangement area in step S130, a dummy pattern (dummy pattern created in step S100) satisfying a predetermined design rule is formed by the first dummy pattern and the second dummy pattern. . For example, the dummy pattern 400 in FIG. 6A satisfies the Minimum-Width rule and the Minimum-Area rule. On the other hand, since both the first dummy pattern and the second dummy pattern are formed so as not to satisfy the predetermined design rule, if the macro cell is not correctly placed in the planned placement area in step S130, the first dummy pattern and the second dummy pattern are The dummy pattern formed by the dummy pattern and the second dummy pattern do not satisfy a predetermined design rule. For example, the dummy pattern 400 ′ in FIG. 6B and the dummy pattern 400 ″ in FIG. 6C do not satisfy the Minimum-Width rule and the Minimum-Area rule.

  Therefore, it is possible to easily and surely check whether or not the macro cell is correctly arranged in the planned arrangement area by executing the design rule check on the layout pattern of the integrated circuit device after the macro cell is arranged.

  If an error relating to a predetermined design rule exists (Yes in step S150), the arrangement position of the macro cell (IP module) is corrected (step S160), and the design rule check step in step S140 is executed again.

  On the other hand, if there is no error relating to the predetermined design rule (No in step S150), the process ends.

  According to the integrated circuit device design method of the present embodiment, first, a dummy pattern 400 satisfying a predetermined design rule is formed, and then the dummy pattern 400 is divided to form the first dummy pattern 100 and the second dummy pattern 200. create. Therefore, if the dummy pattern 400 is created so as to have a minimum value that satisfies a predetermined design rule, the first dummy pattern 100 and the second dummy pattern 200 that do not satisfy the predetermined design rule can be easily created. it can.

3. Method of Manufacturing Integrated Circuit Device In the method of manufacturing an integrated circuit device according to the present embodiment, first, a layout pattern of an integrated circuit device is designed by a layout design method based on the flowchart of FIG. 3 or the flowchart of FIG. Next, a photomask on which the designed layout pattern is drawn is created. Finally, an integrated circuit device is manufactured by forming an integrated circuit on a semiconductor substrate by an existing manufacturing process using the created photomask.

4). Integrated Circuit Device FIG. 12 is an example of a block diagram of the integrated circuit device of this embodiment.

  The microcomputer 700 includes a CPU 510, a cache memory 520, a ROM 710, a RAM 720, an MMU 730, an LCD controller 530, a reset circuit 540, a programmable timer 550, a real time clock (RTC) 560, a DMA controller 570, an interrupt controller 580, a communication control circuit 590, and a bus. Controller 600, A / D converter 610, D / A converter 620, input port 630, output port 640, I / O port 650, clock generator 660, prescaler 670, clock stop control circuit 740, and general purpose for connecting them A bus 680, a dedicated bus 750, etc., various pins 690, etc. are included.

  The CPU 510, the ROM 710, the RAM 720, the LD controller 530, and the like are macrocells of this embodiment, and the microcomputer 700 is manufactured by using the integrated circuit device of this embodiment or the manufacturing method of the integrated circuit device of this embodiment. Integrated circuit device.

5. Electronic Device FIG. 13 shows an example of a block diagram of an electronic device of this embodiment. The electronic apparatus 800 includes a microcomputer (integrated circuit device) 810, an input unit 820, a memory 830, a power generation unit 840, an LCD 850, and a sound output unit 860.

  Here, the input unit 820 is for inputting various data. The microcomputer 810 performs various processes based on the data input by the input unit 820. The memory 830 serves as a work area for the microcomputer 810 and the like. The power generation unit 840 is for generating various power sources used in the electronic device 800. The LCD 850 is for outputting various images (characters, icons, graphics, etc.) displayed by the electronic device.

  The sound output unit 860 is for outputting various sounds (sound, game sound, etc.) output from the electronic device 800, and the function can be realized by hardware such as a speaker.

  FIG. 14A illustrates an example of an external view of a cellular phone 950 that is one of electronic devices. The cellular phone 950 includes a dial button 952 that functions as an input unit, an LCD 954 that displays a telephone number, a name, an icon, and the like, and a speaker 956 that functions as a sound output unit and outputs sound.

  FIG. 14B illustrates an example of an external view of a portable game device 960 that is one of electronic devices. The portable game device 960 includes an operation button 962 that functions as an input unit, a cross key 964, an LCD 966 that displays a game image, and a speaker 968 that functions as a sound output unit and outputs game sound.

  FIG. 14C illustrates an example of an external view of a personal computer 970 that is one of electronic devices. The personal computer 970 includes a keyboard 972 that functions as an input unit, an LCD 974 that displays characters, numbers, graphics, and the like, and a sound output unit 976.

  By incorporating the integrated circuit device of this embodiment into the electronic devices in FIGS. 14A to 14C, an electronic device with high cost performance can be provided in a short period of time.

Note that electronic devices that can use this embodiment include, in addition to those shown in FIGS. 14A to 14C, portable information terminals, pagers, electronic desk calculators, devices equipped with touch panels, projectors, Various electronic devices such as a word processor, a viewfinder type or a monitor direct view type video tape recorder, a car navigation device, and the like can be considered. The present invention is not limited to this embodiment, and various electronic devices can be used within the scope of the present invention. Can be implemented.

  For example, in the flowchart of FIG. 1, when a macro cell including the first dummy pattern is prepared in advance, the process of step S10 is unnecessary. That is, for example, even when the IP including the first dummy pattern is purchased and the processing after step S20 is performed, it is included in the scope of the present invention.

  The present invention includes configurations that are substantially the same as the configurations described in the embodiments (for example, configurations that have the same functions, methods, and results, or configurations that have the same objects and effects). In addition, the invention includes a configuration in which a non-essential part of the configuration described in the embodiment is replaced. In addition, the present invention includes a configuration that exhibits the same operational effects as the configuration described in the embodiment or a configuration that can achieve the same object. Further, the invention includes a configuration in which a known technique is added to the configuration described in the embodiment.

The figure for demonstrating the macrocell (IP module) of this embodiment. FIG. 2A to FIG. 2D are diagrams showing examples of a first dummy pattern included in layout pattern information of a macro cell. FIG. 5 is a flowchart for explaining a layout design method of the integrated circuit device according to the embodiment. FIG. 4A to FIG. 4D are diagrams showing examples of second dummy patterns created corresponding to the first dummy patterns. FIGS. 5A and 5B are diagrams illustrating examples in which macro cells are arranged in a layout region of an integrated circuit device. FIG. 6A to FIG. 6C are diagrams for explaining a dummy pattern formed by a first dummy pattern and a second dummy pattern. FIGS. 7A to 7C are diagrams for describing a dummy pattern formed by a first dummy pattern and a second dummy pattern. FIG. 8A to FIG. 8C are diagrams for explaining a dummy pattern formed by a first dummy pattern and a second dummy pattern. FIG. 9A to FIG. 9C are diagrams for explaining a dummy pattern formed by a first dummy pattern and a second dummy pattern. 10A and 10B are diagrams for explaining a dummy pattern formed by the first dummy pattern and the second dummy pattern when the type of the macro cell to be arranged is wrong. FIG. 9 is a flowchart for explaining a modification of the layout design method for the integrated circuit device according to the embodiment. 1 is an example of a block diagram of an integrated circuit device of an embodiment. 1 is an example of a block diagram of an electronic device including an integrated circuit device. 14A to 14C are examples of external views of various electronic devices.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Macrocell (IP module), 10 Circuit connection information, 20 Layout pattern information, 30 Simulation delay time information, 50 Reference point, 100 1st dummy pattern, 101-113 Rectangular pattern, 120 1st dummy pattern, 121- 130 rectangular pattern, 140 first dummy pattern, 141 L-shaped pattern, 160 first dummy pattern, 161-162 rectangular pattern, 180 first dummy pattern, 181-196 rectangular pattern, 200 second dummy pattern, 201-213 rectangular pattern, 220 second dummy pattern, 221-230 rectangular pattern, 240 second dummy pattern, 241 pattern cut out of L-shaped pattern, 260 second dummy pattern, 261-262 rectangular pattern , 300 Layout area, 310 Macro cell planned layout area, 320 Power line layout pattern, 330 Power line layout pattern, 340 Signal line layout pattern, 342 Signal line layout pattern, 344 Signal line layout pattern, 346 Signal line Layout pattern, position indicated by 350 coordinates (X, Y), 400 dummy pattern, 400 ′ dummy pattern, 400 ″ dummy pattern, 420 dummy pattern, 420 ′ dummy pattern, 420 ″ dummy pattern, 440 dummy pattern, 440 ′ dummy pattern, 440 ″ dummy pattern, 460 dummy pattern, 460 ′ dummy pattern, 460 ″ dummy pattern, 480 dummy pattern, 510 CPU, 520 Cache memory, 530 LCD controller, 540 reset circuit, 550 programmable timer, 560 real-time clock (RTC), 570 DMA controller, 580 interrupt controller, 590 communication control circuit, 600 bus controller, 610 A / D converter, 620 D / A conversion 630 input port, 640 output port, 650 I / O port, 660 clock generator, 670 prescaler, 680 general purpose bus, 690 various pins, 700 microcomputer (semiconductor integrated circuit device), 710 ROM, 720 RAM, 730 MMU 740 clock stop control circuit, 750 dedicated bus, 800 electronic equipment, 810 microcomputer (semiconductor integrated circuit device), 820 input unit, 830 memory, 40 power generation unit, 850 LCD, 860 sound output unit, 950 mobile phone, 952 dial button, 954 LCD, 956 speaker, 960 portable game device, 962 operation button, 964 cross key, 966 LCD, 968 speaker, 970 personal computer 972 Keyboard, 974 LCD, 976 sound output unit

Claims (13)

A layout design method for an integrated circuit device including a macro cell having layout pattern information,
The macro cell included in the layout area of the integrated circuit device in association with a first dummy pattern that does not satisfy a predetermined design rule formed in a layout pattern of at least one layer included in the layout pattern information of the macro cell. A dummy pattern creating step for creating a second dummy pattern that does not satisfy the predetermined design rule in a part of the arrangement planned area;
A macro cell placement step of placing the macro cell in a layout region of the integrated circuit device;
A design rule check step for checking whether a layout pattern of the integrated circuit device after the macro cell is arranged satisfies the predetermined design rule,
In the macro cell placement step,
When the macro cell is placed in the planned placement area, the dummy pattern formed by the first dummy pattern and the second dummy pattern satisfies the predetermined design rule, and the macro cell is placed in the planned placement area. In the integrated circuit device layout design method, the dummy pattern formed by the first dummy pattern and the second dummy pattern does not satisfy the predetermined design rule. In claim 1,
In the dummy pattern creating step,
A layout design method for an integrated circuit device, wherein the first dummy pattern is created in a layout pattern of the at least one layer included in the layout pattern information of the macro cell. In claim 2,
In the dummy pattern creating step,
Creating a dummy pattern satisfying the predetermined design rule, dividing the dummy pattern to create the first dummy pattern and the second dummy pattern;
In the macro cell placement step,
When the macro cell is arranged in the planned arrangement area, the dummy pattern satisfying the predetermined design rule is formed by the first dummy pattern and the second dummy pattern. Device layout design method. In any one of Claims 1 thru | or 3,
A layout design method for an integrated circuit device, wherein shapes of the first dummy pattern and the second dummy pattern are non-linearly symmetric and asymmetrical. In any one of Claims 1 thru | or 4,
The first dummy pattern is a layout pattern that can identify the type of the macro cell,
In the macro cell placement step,
When the macro cell is arranged in the planned arrangement area, a dummy pattern satisfying the predetermined design rule capable of identifying the type of the macro cell is formed by the first dummy pattern and the second dummy pattern. A layout design method for an integrated circuit device. In any one of Claims 1 thru | or 5,
The layout design method for an integrated circuit device, wherein the predetermined design rule is at least one of a design rule that defines a line width of a layout pattern and a design rule that defines an area of the layout pattern. A step of designing a layout pattern of the integrated circuit device by the layout design method according to claim 1;
Creating a photomask on which the layout pattern is drawn;
Forming an integrated circuit on a semiconductor substrate using the photomask. A method for manufacturing an integrated circuit device, comprising: A macrocell used in the design of an integrated circuit device,
A macro cell comprising layout pattern information in which a dummy pattern not satisfying a predetermined design rule is formed in a layout pattern of at least one layer. In claim 8,
The macro cell according to claim 1, wherein the dummy pattern has a non-linear symmetry and a point symmetry. In claim 8 or 9,
The macro cell according to claim 1, wherein the dummy pattern is a layout pattern capable of identifying a type of the macro cell. In any one of Claims 8 thru | or 10.
The macro cell according to claim 1, wherein the predetermined design rule is at least one of a design rule that defines a line width of a layout pattern and a design rule that defines an area of the layout pattern.   An integrated circuit device comprising the macro cell according to claim 8. An integrated circuit device according to claim 12;
Data input means to be processed by the integrated circuit device;
And an output means for outputting data processed by the integrated circuit device.

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