CN116579280B - Time sequence performance adjusting method and device - Google Patents
Time sequence performance adjusting method and device Download PDFInfo
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- CN116579280B CN116579280B CN202310843149.5A CN202310843149A CN116579280B CN 116579280 B CN116579280 B CN 116579280B CN 202310843149 A CN202310843149 A CN 202310843149A CN 116579280 B CN116579280 B CN 116579280B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/337—Design optimisation
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
- G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
- G06F30/3312—Timing analysis
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
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- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
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Abstract
The invention provides a time sequence performance adjusting method, which comprises the following steps: predefining an optimization frequency threshold value and a critical path delay expected value; performing time sequence analysis on the current circuit and returning key path delay information; judging whether the current circuit meets the threshold value of the optimizing times or the expected value of the critical path delay based on the critical path delay information and the current optimizing times, if so, performing optimized compiling operation on the current circuit, and if not, performing time sequence optimizing operation to obtain the optimized circuit, and judging whether the time sequence performance of the optimized circuit is improved. By defining the optimization frequency threshold, the optimization dead cycle is prevented, if the circuit timing requirement cannot be met all the time, the circuit cannot exit, and the critical path delay expected value effectively prevents excessive optimization, so that the overall circuit layout efficiency is improved; the layout optimization effect and the layout optimization efficiency are improved, and the performance of the circuit is improved. The device provided by the invention has corresponding advantages.
Description
Technical Field
The invention belongs to the technical field of Electronic Design Automation (EDA), and particularly relates to a time sequence performance adjustment method and device.
Background
Integrated circuit layout is a very important ring in Electronic Design Automation (EDA) with the aim of arranging circuit elements reasonably on a chip to achieve optimal performance of the circuit. Timing analysis is also a very important step in the design of integrated circuits, the purpose of which is to analyze the longest critical path in the circuit to determine the maximum operating frequency and timing performance of the circuit. With the improvement of chip technology, the scale of the FPGA is also larger and larger, the processes of layout and wiring are more and more important, and the processes have direct influence on the performance of the use area, the power consumption, the working frequency of a user circuit and the like of the chip, and particularly, the time sequence performance meeting the time sequence constraint of the user circuit is a very important target, and the process directly influences whether the design function can be realized.
The existing EDA compiling flow is to execute layout firstly, and then to route according to the layout result after the layout is completed; the link of no time sequence analysis in the prior art leads to the fact that the integrated circuit which is often found to be wired after being laid out and wired does not meet the design requirement, and the integrated circuit needs to be pushed over again to greatly reduce the design efficiency of the integrated circuit; meanwhile, in the prior art, a method for optimizing and verifying an integrated circuit by using a heuristic algorithm exists, but because the layout of the integrated circuit has extremely high complexity, the efficiency and the quality are difficult to ensure by performing layout optimization only in an operation mode, and the phenomena of low design efficiency and inconsistent optimization results are caused.
Therefore, it is required to develop a timing performance adjustment method to achieve the purposes of improving the timing performance adjustment efficiency and improving the timing performance adjustment effect.
Disclosure of Invention
The present invention provides a timing performance adjustment method to improve the efficiency and effect of timing performance adjustment. The invention also provides a time sequence performance adjusting device.
The invention provides a time sequence performance adjusting method, which comprises the following steps: predefining an optimization frequency threshold value and a critical path delay expected value; performing optimization: s1, carrying out time sequence analysis on a current circuit and returning key path delay information; s2, judging whether the current circuit meets the threshold value of the optimizing times or the expected value of the critical path delay based on the critical path delay information and the current optimizing times, if so, performing optimized compiling operation on the current circuit, and if not, performing time sequence optimizing operation to obtain the optimized circuit, and executing step S3; and S3, carrying out time sequence analysis on the optimized circuit, and judging whether the time sequence performance is improved.
The predefined optimization frequency threshold value refers to an upper limit value of the optimization frequency, and because the complexity of the integrated circuit layout is hard to reach the optimal layout, whether the existing layout is the optimal layout cannot be verified, and at the moment, the problem of low efficiency caused by unlimited repeated optimization is prevented by setting the maximum optimization frequency; the critical path delay information refers to a path with the strongest performance restriction capability on the integrated circuit, and by setting the critical path delay expected value, the integrated circuit is not optimized again after being optimized to the setting degree, so that the design efficiency is improved; and (3) carrying out time sequence analysis again after layout optimization, reserving a forward optimization result, discarding a new layout without an optimization effect or a negative optimization effect, and ensuring the optimization efficiency.
The first time sequence analysis is performed before: layout is carried out on the current circuit; and wiring the current circuit, wherein the layout needs to call the layout module, and the wiring needs to call the wiring module.
In the step S2, after the compiling operation, the execution is ended; in the step S3, it is determined whether the timing performance is improved; if the current optimization result is improved, the current optimization result is reserved, the step S1 is returned, and the execution is continued based on the current optimization result; if not, discarding the optimized result, returning to the step S1, and re-executing. Because the integrated circuit has high complexity and high complexity among signals, the critical paths are difficult to be in place in one step each time when being optimized, in order to obtain the better optimizing effect compared with the traditional integrated circuit optimizing mode, a cumulative optimizing method is adopted, and the sequential analysis, the sequential optimization and the repeated sequential analysis are circularly carried out to confirm and preserve or discard the result of the sequential optimization, and the steps ensure that the circuit is positively optimized or not changed each time, so that the positive result of the sequential optimization is continuously accumulated, and the circuit layout with better performance is obtained.
The method for time sequence analysis comprises the following steps: two timing parameters are established: the first parameter and the second parameter respectively represent the arrival time of the received data and the required arrival time of the time data; based on the first parameter and the second parameter, calculating a slot value of a critical path as the critical path information, wherein the first parameter and the second parameter are acquired through static time sequence analysis, and the static time sequence analysis comprises: the set up time analysis and the hold time analysis are more specifically completed through the set up time analysis in the static time sequence analysis, the critical path is the longest path in the integrated circuit, the working efficiency of the whole circuit can be influenced by the small floating of the critical path, and the time required by the critical path determines the time required by the whole circuit.
The method for calculating the slot value of the critical path comprises the steps of setting a delay formula; the delay formula is as follows: the slack value = second parameter-first parameter.
The critical path refers to a path with the minimum slot value, wherein the critical path restricts the performance of a circuit, the frequency of the circuit depends on the value of the slot of the critical path, the frequency of the circuit can reach a user expected value when the slot value is more than or equal to zero, the frequency of the circuit cannot reach the user expected value when the slot value is less than or equal to zero, and at the moment, the circuit needs to be optimized, and the lower the slot value, the lower the frequency of the circuit, the lower the efficiency.
The logic blocks are divided into null logic blocks and non-null logic blocks.
The timing optimization operation includes: exchanging logic blocks; the method for exchanging logic blocks comprises the following steps: defining the exchange range of the logic block; preferentially traversing the empty logic blocks in the switching range, and sequentially switching positions with the logic blocks on the critical path until the calculated slot value is increased; after traversing all the empty logic blocks, if the slot value is not increased, exchanging the logic blocks on the critical path with non-empty logic blocks in the exchanging range until the calculated slot value is increased; after all logic blocks within the switching range are switched, the slot value is not increased, and the method is executed according to the predefined mode: exchanging adjacent logic blocks outside the exchange range or directly returning exchange failure; the process of executing the switching of adjacent logic blocks outside the switching range comprises the following steps: if the switch causes the increase of the slot value, the layout causing the increase of the slot value is reserved and output, and if the switch does not cause the increase of the slot value, the original layout is directly output. The predefining refers to an operation set by a user before the optimization starts and executed when the slot value is not increased after all logic blocks in the exchange range are exchanged, wherein adjacent logic blocks refer to a part which does not belong to the logic blocks in the exchange range in a new range formed by expanding one logic block outwards from the exchange range, the sum of Manhattan distances among the logic blocks after the exchange is smaller than the sum of initial distances before the exchange, and based on the predefining, the user can flexibly select the exchange traversal degree of the logic blocks to perform time sequence optimization operation according to requirements.
The routing operation uses a non-negotiated incremental routing method. Wherein the non-negotiated incremental routing method can improve efficiency of the routing operation.
The optimization frequency threshold is the maximum optimization frequency defined by a user; in the step S2, the current optimization times are obtained to judge whether the current optimization times reach the threshold, if yes, the optimization conditions are not met, the compiling is directly performed, and if not, the step S3 is executed; and in the step S2, whether the delay expected value of the critical path is greater than the expected value or not is obtained, if yes, the optimization condition is not met, the compiling is directly carried out, and if not, the step S3 is executed. The threshold limits the maximum cycle times, so that the optimization times can be controlled within a reasonable range, the occurrence of the condition of excessive optimization is prevented, and the efficiency is effectively improved; meanwhile, the setting of the expected value of the slot controls the optimizing effect, and when the delay of the critical path is optimized to an expected degree, the optimizing cycle stops optimizing to enter the compiling flow, so that excessive optimizing is prevented on one hand, and the optimizing effect is guaranteed on the other hand.
In another aspect, the invention provides an apparatus comprising: the layout module is used for mapping the packed logic blocks onto the chip according to the physical constraint rule; the wiring module is used for acquiring the position and delay information of the logic block and feeding back the position and delay information to the layout module, and the device can achieve the purpose of efficiently optimizing the circuit through the layout module and the wiring module.
The invention improves the layout efficiency of the integrated circuit by using a timing analysis and a preset logic block moving method; the threshold value is set to prevent the integrated circuit with the circulation optimization from being excessively optimized, so that resources are saved; meanwhile, because the time sequence analysis based on the actual circuit can have higher accuracy relative to theoretical operation, the invention can achieve the effect of improving the optimization accuracy of the integrated circuit.
Drawings
Fig. 1 is a flowchart illustrating a timing performance adjustment method according to an embodiment of the invention.
Description of the embodiments
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The technical problems solved by this embodiment mainly include:
1. how to improve the timing performance adjustment efficiency;
2. how to prevent the timing performance adjustment method using the loop optimization method from being excessively optimized;
3. how to move the logic blocks precisely to optimize the layout;
4. how to improve the timing performance adjustment accuracy.
As shown in fig. 1, a specific embodiment of a timing performance adjustment method may be:
the threshold value of the optimizing times and the expected value of the critical path delay are predefined, and the method is carried out before the first time sequence analysis:
using a layout module to layout the current circuit;
wiring the current circuit by using a wiring module;
the following steps are performed: step S1, carrying out time sequence analysis on a circuit with the layout and the wiring completed currently and returning key path delay information;
step S2, judging whether the current circuit meets the threshold value of the optimizing times or the expected value of the critical path delay based on the critical path delay information and the current optimizing times, if so, directly executing compiling and ending the process, and if not, executing step S3;
step S3, obtaining the positions of the logic blocks on the critical path and optimizing the arrangement of the logic blocks; performing time sequence analysis on the optimized circuit, judging whether the time sequence performance is improved, if so, reserving the optimized circuit layout and returning to the step S1, wherein the optimized circuit layout is used as the current circuit layout; if not, discarding the optimized circuit layout and returning to the step S1, wherein the current circuit layout is not the circuit layout before optimization.
In step S2, the wiring operation uses an incremental wiring method that is not negotiated.
In step S3, the method for timing analysis includes: two timing parameters are established: a first parameter and a second parameter, respectively characterizing Data Arrival Time (received data arrival time), data Required Time (setup time data required arrival time); calculating a slot value of the critical path based on a delay formula (slot value=second parameter-first parameter) set by a user, the first parameter and the second parameter; obtaining a slot value as critical path information; the critical path is the longest path in the integrated circuit and is the longest path required by the completion of the function, so the time required by the critical path determines the time required by the whole circuit, and the efficiency of the critical path influences the efficiency of the whole integrated circuit; the method has the advantages that the frequency and the running speed of the integrated circuit are represented by the slack value, the lower the slack value is, the lower the frequency is, the lower the efficiency of the integrated circuit is, the higher the slack value is, the higher the efficiency of the integrated circuit is, the higher the slack value is, the lower the delay is, the lower the efficiency of the integrated circuit is, compared with the traditional method for optimizing the integrated circuit through a calculation method, the optimization method based on time sequence analysis is closer to the actual situation, the problem that the calculation result is unreliable due to the complexity of the layout of the integrated circuit is avoided, and the optimization quality is improved.
In step S2, the threshold of the optimization times is the maximum optimization times defined by the user; in step S4, the current optimization times are obtained through a counter, the current optimization times and the custom maximum optimization times are compared, whether the threshold value is reached or not is judged, and if yes, compiling is directly carried out; in step S4, whether the delay expected value of the critical path is the expected value of the slot value is greater than the expected value is obtained, if yes, the compiling is not directly performed, if not, the optimization frequency does not reach the threshold, and step S3 is executed.
In step S3, the timing optimization operation includes: exchanging logic blocks; the timing optimization operation includes: exchanging logic blocks; the logic blocks are divided into empty logic blocks and non-empty logic blocks; the method for exchanging logic blocks comprises the following steps: defining the exchange range of the logic block; preferentially traversing the empty logic blocks in the switching range, and sequentially switching positions with the logic blocks on the critical path until the calculated slot value is increased; after traversing all the empty logic blocks, if the slot value is not increased, exchanging the logic blocks on the critical path with non-empty logic blocks in the exchanging range until the calculated slot value is increased; after all logic blocks within the switching range are switched, the slot value is not increased, and the method is executed according to the predefined mode: exchanging adjacent logic blocks outside the exchange range or directly returning exchange failure; the process of executing the switching of adjacent logic blocks outside the switching range comprises the following steps: if the switch causes the slot value to be increased, reserving a layout which causes the slot value to be increased and outputting, and if the switch does not cause the slot value to be increased, directly outputting the original layout; the predefining refers to an operation set by a user before the start of optimization and executed when the slot value is not increased after all logic blocks in the exchange range are exchanged, wherein the sum of Manhattan distances among the logic blocks after the exchange is smaller than the sum of initial Manhattan distances before the exchange, and the Manhattan distances refer to the sum of distances of the two logic blocks in the transverse and longitudinal directions under a two-dimensional coordinate system.
The embodiment also provides a device for executing the time sequence performance adjustment method; comprising the following steps: the layout module is used for reasonably mapping the packed logic blocks onto the chip by using a corresponding algorithm according to a physical constraint rule; the wiring module is used for acquiring the position and delay information of the logic block and feeding back the position and delay information to the layout module.
Although the invention has been described with respect to the preferred embodiments, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention, and it is intended that the invention be limited only by the claims appended hereto.
Claims (9)
1. A timing performance adjustment method, comprising:
predefining an optimization frequency threshold value and a critical path delay expected value; performing optimization:
s1, carrying out time sequence analysis on a current circuit and returning key path delay information;
s2, judging whether the current circuit meets the threshold value of the optimizing times or the expected value of the critical path delay based on the critical path delay information and the current optimizing times,
if yes, performing optimized compiling operation on the current circuit;
if not, executing time sequence optimization operation to obtain the optimized circuit, and executing step S3;
s3, carrying out time sequence analysis on the optimized circuit, and judging whether the time sequence performance is improved;
wherein the timing optimization operation includes: exchanging logic blocks;
the method for exchanging logic blocks comprises the following steps: defining the exchange range of the logic block; preferentially traversing the empty logic blocks in the switching range, and sequentially switching positions with the logic blocks on the critical path until the calculated slot value is increased; after traversing all the empty logic blocks, if the slot value is not increased, exchanging the logic blocks on the critical path with non-empty logic blocks in the exchanging range until the calculated slot value is increased;
after all logic blocks within the switching range are switched, the slot value is not increased, and the method is executed according to the predefined mode: exchanging adjacent logic blocks outside the exchange range or directly returning exchange failure;
the process of executing the switching of adjacent logic blocks outside the switching range comprises the following steps:
if the switch causes the increase of the slot value, the layout causing the increase of the slot value is reserved and output, and if the switch does not cause the increase of the slot value, the original layout is directly output.
2. The timing performance adjustment method according to claim 1, wherein:
the first time sequence analysis is performed before:
layout is carried out on the current circuit;
the current circuit is routed.
3. The timing performance adjustment method according to claim 1, wherein:
in the step S2, after the compiling operation, the execution is ended;
in the step S3, it is determined whether the timing performance is improved:
if the current optimized circuit is lifted, reserving the current optimized circuit, returning to the step S1, and continuously executing based on the current optimized circuit;
if not, discarding the optimized circuit, returning to the step S1, and re-executing.
4. A timing performance adjustment method according to claim 3, characterized in that:
the method for time sequence analysis comprises the following steps:
two timing parameters are established: the first parameter and the second parameter respectively represent the arrival time of the received data and the required arrival time of the time data;
and calculating a slot value of the critical path based on the first parameter and the second parameter to serve as the critical path information.
5. The timing performance adjustment method according to claim 4, wherein:
the method for calculating the slot value of the critical path comprises the steps of setting a delay formula; the delay formula is as follows: the slack value = second parameter-first parameter.
6. The timing performance adjustment method according to claim 4, wherein:
the critical path refers to a path with the minimum slot value.
7. The timing performance adjustment method according to claim 2, wherein:
the routing operation uses a non-negotiated incremental routing method.
8. The timing performance adjustment method according to claim 1, wherein:
the optimization frequency threshold is the maximum optimization frequency defined by a user; in the step S2, the current optimization times are obtained to judge whether the current optimization times reach the threshold, if yes, the optimization conditions are not met, the compiling is directly performed, and if not, the step S3 is executed;
and in the step S2, whether the delay expected value of the critical path is the expected value of the slot value or not is obtained, if yes, the optimization condition is not met, the compiling is directly carried out, and if not, the step S3 is executed.
9. An apparatus for timing performance adjustment, characterized by: for performing a timing performance adjustment method according to any of claims 1-8; comprising the following steps: the layout module is used for mapping the packed logic blocks onto the chip according to the physical constraint rule; and the wiring module is used for acquiring the position and delay information of the logic block and feeding back the position and delay information to the layout module.
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| CN118569176B (en) * | 2024-08-01 | 2024-12-20 | 中科亿海微电子科技（苏州）有限公司 | Incremental boxing method and device capable of automatically optimizing time sequence performance |
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