CN118569176B - Incremental boxing method and device capable of automatically optimizing time sequence performance - Google Patents
Incremental boxing method and device capable of automatically optimizing time sequence performance Download PDFInfo
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Abstract
一种自动优化时序性能的增量装箱方法及装置，在整体布局完成后对关键路径上BLE增量调整CLB的位置，根据调整后时序是否变化来决定是否接受此次调整；调用时序分析获取建立时间裕度最小的连接集合C，对C中的每条连接,执行增量装箱将该连接起点的BLE移动到该连接终点BLE所在的CLB，增量装箱将该连接终点的BLE移动到该连接起点BLE所在的CLB；如果2次增量装箱中有一次可行，并使建立时间裕度最小值worst_slack变好或slack最小连接数量变少，则保持结果，更新C，转入下一轮；否则还原增量装箱前结果，转入C中下一条连接的优化中，通过这样迭代优化来进一步减少关键路径的延时，提高电路的时序性能。
An incremental packing method and device for automatically optimizing timing performance, after the overall layout is completed, the position of the CLB of the BLE on the critical path is incrementally adjusted, and whether to accept the adjustment is determined according to whether the timing changes after the adjustment; the timing analysis is called to obtain the connection set C with the smallest establishment time margin, and for each connection in C, incremental packing is performed to move the BLE at the starting point of the connection to the CLB where the BLE at the end point of the connection is located, and the incremental packing moves the BLE at the end point of the connection to the CLB where the BLE at the starting point of the connection is located; if one of the two incremental packings is feasible and makes the minimum value of the establishment time margin worst_slack better or the minimum number of slack connections is reduced, the result is maintained, C is updated, and the next round is entered; otherwise, the result before incremental packing is restored, and the optimization of the next connection in C is entered, and the delay of the critical path is further reduced through such iterative optimization, and the timing performance of the circuit is improved.
Description
Technical Field
The invention relates to the technical field of Field Programmable Gate Arrays (FPGA) in digital integrated circuits, in particular to an incremental boxing method capable of automatically optimizing time sequence performance and an incremental boxing device capable of automatically optimizing time sequence performance.
Background
An FPGA (Field-Programmable GATE ARRAY) is a general-purpose logic circuit, and a CPU, a DSP, and is called a three-large general-purpose signal processing device. The method has the advantages of high flexibility, high parallelism and low development risk, is widely applied to the fields of industrial control, aerospace, communication, automotive electronics, data centers, intelligent processing and the like, and occupies more and more market share.
The design flow of the FPGA EDA (Electronic Design Automation ) software mainly comprises a plurality of steps of design input, synthesis, mapping, boxing, layout, wiring, time sequence analysis, code stream generation, downloading and the like. The packing stage is to divide the basic logic unit BLE (Basic Logic Element) in the synthesized netlist into boxes, so that each box can be mapped to one programmable logic block CLB (Configurable Logic Block) inside the FPGA chip, while meeting the constraint condition of the resources to ensure that the logic of the box can be implemented in the CLB unit. The layout stage is to correspond each CLB to a physical coordinate location inside the FPGA chip and meet constraint and optimization objectives such as area or timing.
The processing stage of a conventional FPGA binning is completed before the layout stage, which means that the binning result cannot be modified after the layout stage is completed. If the delay on the critical path is still large after the layout stage is completed, the time sequence requirement of the user cannot be met, and at the moment, the number of CLBs on the critical path cannot be reduced because the boxing result cannot be modified any more, so that the delay of the critical path cannot be obviously reduced, and the time sequence requirement of the user cannot be met.
Disclosure of Invention
In order to overcome the defects of the prior art, the technical problem to be solved by the invention is to provide an incremental boxing method capable of automatically optimizing the time sequence performance, which can further reduce the delay of a critical path through iterative optimization and improve the time sequence performance of a circuit.
The technical scheme of the invention is that the incremental boxing method for automatically optimizing the time sequence performance comprises the following steps:
(1) Running time sequence analysis, obtaining a connection set C with a minimum setup time margin value of worst_slot and a setup time margin equal to worst_slot, and marking that each connection in C is optimizable;
(2) Judging whether the optimized connection exists in the C, if so, finding out the first optimized connection C in the C, otherwise, stopping;
(3) Performing incremental boxing, and moving BLE of the starting point c to CLB where BLE of the ending point c is located;
(4) Judging whether the boxing is feasible or not, if so, executing the step (5), otherwise, executing the step (7);
(5) Running a time sequence analysis, and acquiring the latest establishment time margin minimum value of the word_slot ́ and a connection set C ́ with the establishment time margin equal to the word_slot ́;
(6) Judging whether the word_slot ́ > word_slot or the connection number of C ́ < the connection number of C, if so, executing the step (11), otherwise, executing the step (7);
(7) Performing incremental boxing, and moving BLE of the c end point to CLB where BLE of the c start point is located;
(8) Judging whether the boxing is feasible or not, if so, executing the step (9), otherwise, executing the step (12);
(9) Running a time sequence analysis, and acquiring the latest establishment time margin minimum value of the word_slot ́ and a connection set C ́ with the establishment time margin equal to the word_slot ́;
(10) Judging whether the word_slot ́ > word_slot or the connection number of C ́ < the connection number of C, if so, executing the step (11), otherwise, executing the step (12);
(11) Reserving an incremental boxing result, and updating a slack minimum connection set C of the latest time sequence analysis result;
(12) Restoring the boxing result, marking c as non-optimizable, and switching to the step (2).
After the whole layout is finished, the invention adjusts the positions of the CLBs of the BLEs on the critical paths in an incremental way, decides whether to accept or reject the adjustment according to whether the adjusted time sequence changes, and further reduces the delay of the critical paths through iterative optimization so as to improve the time sequence performance of the circuit.
There is also provided an incremental boxing apparatus for automatically optimizing timing performance, comprising:
A first operation time sequence analysis unit configured to acquire a connection set C with a setup time margin minimum value of w_slot and a setup time margin equal to w_slot, and mark each connection in C as optimizable;
the first judging unit is configured to judge whether the optimizable connection exists in the C, if so, the first optimizable connection C in the C is found, and if not, stopping;
A first delta boxing unit configured to perform delta boxing, moving BLE at the c start point to CLB where BLE at the c end point is located;
A second judging unit configured to judge whether this boxing is possible, if so, execute the second operation timing analysis unit, otherwise execute the second increment boxing unit;
a second operation timing analysis unit configured to operate timing analysis, obtain the latest setup time margin minimum value of the word_slot ́ and the connection set C ́ with the setup time margin equal to the word_slot ́;
A third judging unit configured to judge whether the number of connections of the word_slot ́ > word_slot, or the number of connections of the C ́ < the number of connections of the C, if so, executing the reservation unit, otherwise, executing the second delta boxing unit;
A second delta boxing unit configured to perform delta boxing, moving BLE at c-end to CLB where BLE at c-start is located;
a fourth judging unit configured to judge whether this time of packing is possible, and if so, execute the third operation timing analysis unit, otherwise execute the restoring unit;
A third operation timing analysis unit configured to operate timing analysis, obtain the latest setup time margin minimum value of the word_slot ́ and the connection set C ́ with the setup time margin equal to the word_slot ́;
A fifth judging unit configured to judge whether the number of connections of the C ́ is greater than the number of connections of the w rst_slot, or whether the number of connections of the C ́ is greater than the number of connections of the C, if so, executing the reservation unit, otherwise, executing the restoration unit;
The reservation unit is configured to reserve the incremental boxing result and update a slack minimum connection set C of the latest time sequence analysis result;
and the restoring unit is configured to restore the boxing result and mark c as non-optimizable, and the first judging unit is shifted to.
Drawings
FIG. 1 illustrates a flow chart of an incremental boxing method that automatically optimizes timing performance in accordance with the present invention.
Fig. 2 is a flowchart of acquiring a connection set C with a minimum setup time margin by performing timing analysis.
Fig. 3 is a schematic flow chart of the incremental binning to move a basic logic unit BLE1 from the original programmable logic block CLB1 to CLB 2.
Detailed Description
As shown in fig. 1, this incremental boxing method for automatically optimizing timing performance includes the steps of:
(1) Running time sequence analysis, obtaining a connection set C with a minimum setup time margin value of worst_slot and a setup time margin equal to worst_slot, and marking that each connection in C is optimizable;
(2) Judging whether the optimized connection exists in the C, if so, finding out the first optimized connection C in the C, otherwise, stopping;
(3) Performing incremental boxing, and moving BLE of the starting point c to CLB where BLE of the ending point c is located;
(4) Judging whether the boxing is feasible or not, if so, executing the step (5), otherwise, executing the step (7);
(5) Running a time sequence analysis, and acquiring the latest establishment time margin minimum value of the word_slot ́ and a connection set C ́ with the establishment time margin equal to the word_slot ́;
(6) Judging whether the word_slot ́ > word_slot or the connection number of C ́ < the connection number of C, if so, executing the step (11), otherwise, executing the step (7);
(7) Performing incremental boxing, and moving BLE of the c end point to CLB where BLE of the c start point is located;
(8) Judging whether the boxing is feasible or not, if so, executing the step (9), otherwise, executing the step (12);
(9) Running a time sequence analysis, and acquiring the latest establishment time margin minimum value of the word_slot ́ and a connection set C ́ with the establishment time margin equal to the word_slot ́;
(10) Judging whether the word_slot ́ > word_slot or the connection number of C ́ < the connection number of C, if so, executing the step (11), otherwise, executing the step (12);
(11) Reserving an incremental boxing result, and updating a slack minimum connection set C of the latest time sequence analysis result;
(12) Restoring the boxing result, marking c as non-optimizable, and switching to the step (2).
After the whole layout is finished, the invention adjusts the positions of the CLBs of the BLEs on the critical paths in an incremental way, decides whether to accept or reject the adjustment according to whether the adjusted time sequence changes, and further reduces the delay of the critical paths through iterative optimization so as to improve the time sequence performance of the circuit.
Preferably, in the step (1), the step of obtaining the connection set C with the smallest setup time margin by running the time sequence analysis includes:
(1.1) traversing the timing diagram G from front to back, and calculating the arrival time Tarrival of each node;
(1.2) traversing the time sequence diagram G from back to front, and calculating the required arrival time Trequired of each node;
(1.3) calculating a setup time margin, slack, for each connection;
(1.4) ordering each connection in order of slots from small to large;
(1.5) obtaining a minimum value of the slots, the minimum value of the slots being equal to the slots of the first connection after ordering;
(1.6) obtaining a first connection c after sequencing;
(1.7) judging that if the slot of c is equal to the word_slot, executing the step (1.8), otherwise, exiting;
(1.8) adding C to set C and forwarding to the next connection.
Preferably, in the step (3), the step of moving the basic logic unit BLE1 from the original programmable logic block CLB1 to CLB2 by incremental boxing includes:
(3.1) removing BLE1 from the list of subunits of CLB 1;
(3.2) updating the attributes of CLB 1;
(3.3) adding BLE1 from the list of subunits of CLB 2;
(3.4) updating the attributes of CLB 2;
(3.5) signal i for each input port in BLE 1;
(3.6) finding the sink reaching the CLB1 in the final node sink list in the signal i, and modifying the sink reaching the CLB 2;
(3.7) outputting a signal o for each of BLE 1;
(3.8) modifying the origin source information in signal o to CLB2.
Preferably, in the step (4), it is possible to determine that the incremental bin where the c start point BLE1 moves to the c end point BLE2 is located is that the bin of BLE1 is of CLB type, the bin of BLE2 is of CLB type, BLE1 is not on a carry chain, BLE2 is not on a carry chain, the number of BLE of CLB2 does not reach the maximum capacity, the maximum limit of CLB data signals is satisfied after BLE1 is added to CLB2, and the maximum limit of CLB control signals is satisfied after BLE1 is added to CLB 2.
It will be appreciated by those of ordinary skill in the art that implementing all or part of the steps of the methods of the above embodiments may be accomplished by a program that is stored in a computer readable storage medium that, when executed, comprises the steps of the methods of the above embodiments, and that the storage medium may be a ROM/RAM, magnetic disk, optical disk, memory card, etc. Accordingly, the present invention also includes, corresponding to the method of the present invention, an incremental boxing apparatus for automatically optimizing timing performance, typically in the form of functional blocks corresponding to the steps of the method. The device comprises:
there is also provided an incremental boxing apparatus for automatically optimizing timing performance, comprising:
A first operation time sequence analysis unit configured to acquire a connection set C with a setup time margin minimum value of w_slot and a setup time margin equal to w_slot, and mark each connection in C as optimizable;
the first judging unit is configured to judge whether the optimizable connection exists in the C, if so, the first optimizable connection C in the C is found, and if not, stopping;
A first delta boxing unit configured to perform delta boxing, moving BLE at the c start point to CLB where BLE at the c end point is located;
A second judging unit configured to judge whether this boxing is possible, if so, execute the second operation timing analysis unit, otherwise execute the second increment boxing unit;
a second operation timing analysis unit configured to operate timing analysis, obtain the latest setup time margin minimum value of the word_slot ́ and the connection set C ́ with the setup time margin equal to the word_slot ́;
A third judging unit configured to judge whether the number of connections of the word_slot ́ > word_slot, or the number of connections of the C ́ < the number of connections of the C, if so, executing the reservation unit, otherwise, executing the second delta boxing unit;
A second delta boxing unit configured to perform delta boxing, moving BLE at c-end to CLB where BLE at c-start is located;
a fourth judging unit configured to judge whether this time of packing is possible, and if so, execute the third operation timing analysis unit, otherwise execute the restoring unit;
A third operation timing analysis unit configured to operate timing analysis, to obtain a latest setup time margin minimum value of the word_slot ́ and a connection set C ́ with a setup time margin equal to the word_slot ́;
A fifth judging unit configured to judge whether the number of connections of the C ́ is greater than the number of connections of the w rst_slot, or whether the number of connections of the C ́ is greater than the number of connections of the C, if so, executing the reservation unit, otherwise, executing the restoration unit;
The reservation unit is configured to reserve the incremental boxing result and update a slack minimum connection set C of the latest time sequence analysis result;
and the restoring unit is configured to restore the boxing result and mark c as non-optimizable, and the first judging unit is shifted to.
Preferably, in the first operation timing analysis unit, the step of obtaining the connection set C with the smallest setup time margin by operation timing analysis includes:
(1.1) traversing the timing diagram G from front to back, and calculating the arrival time Tarrival of each node;
(1.2) traversing the time sequence diagram G from back to front, and calculating the required arrival time Trequired of each node;
(1.3) calculating a setup time margin, slack, for each connection;
(1.4) ordering each connection in order of slots from small to large;
(1.5) obtaining a minimum value of the slots, the minimum value of the slots being equal to the slots of the first connection after ordering;
(1.6) obtaining a first connection c after sequencing;
(1.7) judging that if the slot of c is equal to the word_slot, executing the step (1.8), otherwise, exiting;
(1.8) add C to C and transfer to the next connection.
Preferably, in the first incremental boxing unit, the step of moving a basic logic unit BLE1 from the original programmable logic block CLB1 to CLB2 by incremental boxing includes:
(3.1) removing BLE1 from the list of subunits of CLB 1;
(3.2) updating the attributes of CLB 1;
(3.3) adding BLE1 from the list of subunits of CLB 2;
(3.4) updating the attributes of CLB 2;
(3.5) signal i for each input port in BLE 1;
(3.6) finding the sink reaching the CLB1 in the final node sink list in the signal i, and modifying the sink reaching the CLB 2;
(3.7) outputting a signal o for each of BLE 1;
(3.8) modifying the origin source information in signal o to CLB2.
Preferably, in the second judging unit, it is possible to judge that the incremental bin where the c start point BLE1 moves to the c end point BLE2 is located is that the bin of BLE1 is of CLB type, the bin of BLE2 is of CLB type, BLE1 is not on a carry chain, BLE2 is not on a carry chain, the number of BLE of CLB2 does not reach the maximum capacity, the maximum limit of CLB data signals is satisfied after BLE1 is added to CLB2, and the maximum limit of CLB control signals is satisfied after BLE1 is added to CLB 2.
The present invention is not limited to the preferred embodiments, but can be modified in any way according to the technical principles of the present invention, and all such modifications, equivalent variations and modifications are included in the scope of the present invention.
Claims (8)
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| CN114282471A (en) * | 2021-11-19 | 2022-04-05 | 中科亿海微电子科技（苏州）有限公司 | A Packing Method for FPGA Adaptive Logic Module |
| CN115392168A (en) * | 2022-09-01 | 2022-11-25 | 北京工商大学 | Boxing method for FPGA (field programmable Gate array) chips |
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| CN116579280B (en) * | 2023-07-11 | 2023-10-20 | 中科亿海微电子科技（苏州）有限公司 | Time sequence performance adjusting method and device |
| CN117574820B (en) * | 2024-01-15 | 2024-09-17 | 中科亿海微电子科技（苏州）有限公司 | Incremental time sequence analysis method |
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| CN114282471A (en) * | 2021-11-19 | 2022-04-05 | 中科亿海微电子科技（苏州）有限公司 | A Packing Method for FPGA Adaptive Logic Module |
| CN115392168A (en) * | 2022-09-01 | 2022-11-25 | 北京工商大学 | Boxing method for FPGA (field programmable Gate array) chips |
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