CN114286514A - Embedded element structure and manufacturing method thereof - Google Patents
Embedded element structure and manufacturing method thereof Download PDFInfo
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- CN114286514A CN114286514A CN202111495773.8A CN202111495773A CN114286514A CN 114286514 A CN114286514 A CN 114286514A CN 202111495773 A CN202111495773 A CN 202111495773A CN 114286514 A CN114286514 A CN 114286514A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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Abstract
本发明提供一种内埋式元件结构及其制造方法，内埋式元件结构包括线路板、电子元件、介电材料层及连接线路层。线路板具有穿槽且包括核心层、第一线路层、第二线路层及导通孔。第一线路层与第二线路层位于核心层的相对两侧。穿槽贯穿第一线路层及核心层。导通孔电性连接第一线路层与第二线路层。电子元件设置于穿槽内且包括多个连接垫。第一线路层的第一电性连接面与连接垫的第二电性连接面共平面。介电材料层填充于穿槽内。连接线路层接触第一电性连接面与第二电性连接面。
The invention provides an embedded element structure and a manufacturing method thereof. The embedded element structure includes a circuit board, an electronic element, a dielectric material layer and a connection circuit layer. The circuit board has through grooves and includes a core layer, a first circuit layer, a second circuit layer and a through hole. The first circuit layer and the second circuit layer are located on opposite sides of the core layer. The through groove penetrates through the first circuit layer and the core layer. The via hole electrically connects the first circuit layer and the second circuit layer. The electronic components are arranged in the through grooves and include a plurality of connection pads. The first electrical connection surface of the first circuit layer is coplanar with the second electrical connection surface of the connection pad. A dielectric material layer is filled in the through grooves. The connection circuit layer contacts the first electrical connection surface and the second electrical connection surface.
Description
The application is a divisional application of a Chinese patent application with the application number of 201810842418.5 (application date: 7 and 27 in 2018, the name of the invention: an embedded element structure and a manufacturing method thereof).
Technical Field
The present disclosure relates to electronic devices, and particularly to an embedded device structure and a method for manufacturing the embedded device structure.
Background
In a typical embedded component structure, at least a conductive through via (PCB) is used to connect an electronic component with a Printed Circuit Board (PCB). However, the above connection method may cause a long electrical transmission path between the electronic device and the printed circuit board, which may cause a high attenuation degree of power and/or signal (signal) of the electronic product, and may also easily generate noise (noise), thereby reducing the quality of the electronic product. Moreover, the embedded element structure is complex in manufacturing mode and thick.
Disclosure of Invention
The invention provides an embedded element structure and a manufacturing method thereof, wherein the thickness of the embedded element structure can be thinner, and the manufacturing method can be simpler.
The embedded element structure comprises a circuit board, an electronic element, a dielectric material layer and a connecting circuit layer. The circuit board is provided with a through groove. The circuit board comprises a core layer, a first circuit layer, a second circuit layer and at least one through hole. The first circuit layer and the second circuit layer are respectively positioned at two opposite sides of the core layer. The through groove at least penetrates through the first circuit layer and the core layer. The via hole penetrates through the core layer to electrically connect the first circuit layer and the second circuit layer. The electronic element is arranged in the through groove. The electronic component includes a plurality of connection pads exposed outside the through-slots. The first electrical connection surface of the first circuit layer is coplanar with the second electrical connection surface of each connection pad. The dielectric material layer is at least filled in the through groove. The connection circuit layer covers and contacts the first electrical connection surface and each second electrical connection surface. The connecting pad is electrically connected to the first circuit layer through the connecting circuit layer.
In an embodiment of the invention, the dielectric material layer is further filled between each connecting pad and the first circuit layer. The dielectric material layer has a dielectric surface coplanar with the first electrical connection surface. The connection circuit layer covers and contacts the first electrical connection surface, the dielectric surface and the second electrical connection surface.
In an embodiment of the invention, the cross-sectional thickness of the connection circuit layer on the first electrical connection surface, the dielectric surface and the second electrical connection surface is uniform on a cross-section perpendicular to the first electrical connection surface.
In an embodiment of the invention, a cross-sectional area of the through groove is larger than a surface area of the electronic component on the second electrical connection surface.
In an embodiment of the invention, the embedded device structure further includes a first dielectric layer. The first dielectric layer and the first circuit layer are arranged on the same side of the core layer. The first dielectric layer covers at least part of the first circuit layer and at least part of the connection circuit layer, and the first dielectric layer has at least one opening exposing the first circuit layer or the connection circuit layer.
In an embodiment of the invention, a material of the first dielectric layer includes a solder mask material.
In an embodiment of the invention, the dielectric material layer has a covering portion located outside the through groove. The covering part covers one side of the core layer where the second circuit layer is located, and the covering part covers at least part of the second circuit layer.
In an embodiment of the invention, the covering portion of the dielectric material layer has at least one dielectric opening exposing the second circuit layer or the via hole.
In an embodiment of the invention, the embedded device structure further includes a second dielectric layer. The second dielectric layer covers the covering part of the dielectric material layer, and the second dielectric layer is provided with at least one opening exposing the second circuit layer or the through hole.
In an embodiment of the invention, a material of the second dielectric layer includes a solder mask material.
In an embodiment of the invention, the through groove is communicated with at least one via hole.
The manufacturing method of the embedded element structure comprises the following steps. A vector is provided. The circuit board is placed on a carrier. The circuit board is provided with a through groove. The circuit board comprises a core layer, a first circuit layer and a second circuit layer. The first circuit layer contacts the carrier. The first circuit layer and the second circuit layer are respectively positioned at two opposite sides of the core layer. The through groove at least penetrates through the first circuit layer and the core layer. The electronic component is placed on a carrier. The electronic component has a plurality of connection pads. These connection pads contact the carrier. After the circuit board and the electronic element are arranged on the carrier and the electronic element is embedded in the through groove, the dielectric material layer is formed on the carrier. The dielectric material layer is at least filled in the through groove. The carrier is removed to expose the first circuit layer and the connecting pads. The first electrical connection surface of the first circuit layer is coplanar with the second electrical connection surface of each connection pad. After the carrier is removed, a connection circuit layer is formed. The connection circuit layer covers and contacts the first electrical connection surface and each second electrical connection surface.
In an embodiment of the invention, the circuit board further includes at least one via hole. The via hole penetrates through the core layer to electrically connect the first circuit layer and the second circuit layer.
In an embodiment of the invention, the through groove and the via hole are communicated with each other.
In an embodiment of the invention, the method for manufacturing the embedded component further includes the following steps. After forming the connection line layer, a first dielectric layer is formed. The first dielectric layer covers at least a portion of the first circuit layer and at least a portion of the connection circuit layer.
In an embodiment of the invention, a material of the first dielectric layer includes a solder mask material.
In an embodiment of the invention, the method for manufacturing the embedded device structure further includes the following steps. After the dielectric material layer is formed, at least one through hole penetrating through the core layer, the first circuit layer and the second circuit layer is formed on the circuit board. And filling a conductive material into the at least one through hole to form at least one through hole penetrating through the core layer. The via hole is electrically connected with the first circuit layer and the second circuit layer.
In an embodiment of the invention, the dielectric material layer has a covering portion located outside the through groove. The covering part covers the side of the core layer where the second circuit layer is located, and covers at least part of the second circuit layer.
In an embodiment of the invention, the method for manufacturing the embedded device structure further includes the following steps. At least one dielectric opening is formed on the covering portion of the dielectric material layer. The dielectric opening exposes the second circuit layer.
In an embodiment of the invention, the method for manufacturing the embedded device structure further includes the following steps. Forming a second dielectric layer. The second dielectric layer covers the covering part of the dielectric material layer.
In an embodiment of the invention, the method for manufacturing the embedded device structure further includes the following steps. At least one second opening is formed in the second dielectric layer. The second opening exposes the second circuit layer.
In an embodiment of the invention, a material of the second dielectric layer includes a solder mask material.
In view of the above, in the embedded device structure of the present invention, the electronic device is directly electrically connected to the circuit board through the connection circuit layer, and the formation of the via hole between the electronic device and the circuit board is not required or can be omitted. Therefore, the manufacturing method of the embedded element structure can be simpler, and the thickness can be thinner. In addition, the circuit length between the electronic element and the circuit board can be reduced by connecting the circuit layers, so that the signal transmission time (i.e. delay time) can be reduced, and the transmission rate between different electronic elements can be improved.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
Fig. 1A to fig. 1H are schematic cross-sectional views illustrating a method for manufacturing an embedded device structure according to a first embodiment of the invention.
Fig. 1I is a schematic top view of a buried device structure according to a first embodiment of the present invention.
Fig. 2 is a schematic cross-sectional view of a buried device structure according to a second embodiment of the present invention.
Fig. 3A to fig. 3E are schematic cross-sectional views illustrating a method for manufacturing an embedded device structure according to a third embodiment of the invention.
Fig. 4A, fig. 4B and fig. 4D are schematic bottom views illustrating a method for manufacturing an embedded device structure according to a fourth embodiment of the invention.
Fig. 4C, fig. 4E to fig. 4H are schematic cross-sectional views illustrating a method for manufacturing an embedded device structure according to a fourth embodiment of the invention.
Fig. 5A to 5F are schematic cross-sectional views illustrating a method for manufacturing an embedded device structure according to a fifth embodiment of the invention.
Fig. 5G is a schematic top view of a buried device structure according to a fifth embodiment of the invention.
Fig. 6 is a schematic cross-sectional view of a buried device structure according to a sixth embodiment of the present invention.
Fig. 7 is a schematic cross-sectional view of a buried device structure according to a seventh embodiment of the present invention.
[ notation ] to show
100. 200, 300, 400, 500, 600, 700: embedded element
110. 310', 310, 410', 410: circuit board
110a, 310' a, 310a, 410 a: first side
110b, 310b, 410 b: second side
110c, 410 c: trough penetrating
310 e: through hole
111: core layer
111 d: core layer side wall
112. 112', 112 ": first circuit layer
112 a: the first electrical connection surface
112 d: first circuit layer side wall
113: second circuit layer
113 a: third electrical connection surface
113 d: side wall of the second circuit layer
114. 114', 114 ", 314: conducting hole
120. 520, the method comprises the following steps: electronic component
121: connecting pad
121a, 521 a: second electrical connection surface
521: first connecting pad
522: second connecting pad
130: dielectric material layer
130a, 530 a: dielectric surface
530: a first dielectric material layer
131. 531: covering part
131a, 531 a: dielectric opening
535: a second dielectric material layer
535 a: dielectric opening
140: connection circuit layer
140h1, 140h2, 140h 3: thickness of
150. 250, 350, 450, 650: a first dielectric layer
150a, 250a, 350a, 450a, 650 a: a first dielectric opening
160. 260, 360, 460: a second dielectric layer
160a, 260a, 360a, 460 a: second dielectric opening
170: third circuit layer
180: a fourth circuit layer
590: line layer
10: carrier
10 a: surface of the carrier
R: region(s)
Detailed Description
The foregoing and other technical and scientific aspects, features and utilities of the present invention will be apparent from the following detailed description of various embodiments, which is to be read in connection with the accompanying drawings. Directional terms as referred to in the following examples, for example: "upper", "lower", "front", "rear", "left", "right", etc., refer only to the orientation of the figures. Accordingly, the directional terminology is used for purposes of illustration and is in no way limiting.
In the detailed description of the embodiments, terms such as "first," "second," "third," "fourth," etc. may be used to describe various elements. These terms are only used to distinguish one element from another, but in the structure, these elements should not be limited by these terms. For example, a first element may be termed a second element, and, similarly, a second element may be termed a first element, without departing from the scope of the present inventive concept. In addition, in the manufacturing method, the order of formation of these elements or members should not be limited by these terms, except for a specific manufacturing flow. For example, the first element may be formed before the second element. Alternatively, the first element may be formed after the second element. Alternatively, the first element and the second element may be formed in the same manufacturing method or step.
Also, the thickness of layers and regions in the drawings may be exaggerated for clarity. The same or similar symbols represent the same or similar elements, and the following paragraphs will not be repeated.
Fig. 1A to fig. 1H are schematic cross-sectional views illustrating a method for manufacturing an embedded device structure according to a first embodiment of the invention. Fig. 1I is a schematic top view of a buried device structure according to a first embodiment of the present invention. Specifically, fig. 1H is an enlarged view of the region R in fig. 1G.
Referring to fig. 1A, a circuit board 110 is provided. The wiring board 110 includes a core layer 111, a first wiring layer 112, and a second wiring layer 113. A first circuit layer 112 is on the first side 110a of the circuit board 110 and is located on the core layer 111, and a second circuit layer 113 is on the second side 110b of the circuit board 110 and is located on the core layer 111. The first side 110a is opposite the second side 110 b. The wiring board 110 has a through hole 110 c. The through-groove 110c penetrates at least the first circuit layer 112 and the core layer 111. That is, the through-groove 110c is at least formed by the sidewall 111d of the core layer 111 and the sidewall 112d of the first wiring layer 112. And the two first circuit layers 112', 112 ″ on both sides of the through-groove 110c are structurally and electrically separated from each other.
In the present embodiment, the through groove 110c also penetrates the second circuit layer 113. That is, in the present embodiment, the through groove 110c may be formed by the sidewall 111d of the core layer 111, the sidewall 112d of the first circuit layer 112, and the sidewall 113d of the second circuit layer 113.
In the embodiment, the core layer 111 may include a polymer glass fiber composite substrate, a glass substrate, a ceramic substrate, an insulating silicon substrate, a Polyimide (PI) glass fiber composite substrate, or the like, but the invention is not limited thereto. That is, in the present embodiment, the core layer 111, the first circuit layer 112 and the second circuit layer 113 on two opposite sides thereof may constitute a double-sided wiring board (double-sided wiring board). For example, the circuit board 110 may be a Copper Clad Laminate (CCL) or other suitable printed circuit board, but the invention is not limited thereto.
In some embodiments, the first circuit layer 112 and/or the second circuit layer 113 may be one or more conductive layers, which is not limited in the present invention. In addition, the first circuit layer 112 and/or the second circuit layer 113 may be a plurality of conductive layers, and the plurality of conductive layers may be separated from each other by insulating layers, and different conductive layers may be electrically connected to each other by a conductive via (conductive via). The Via Hole is, for example, a Buried Via Hole (BVH), but the present invention is not limited thereto.
In this embodiment, the circuit board 110 may further include at least one via hole 114, so that the first circuit layer 112 on the first side 110a and the second circuit layer 113 on the second side 110b may be electrically connected to each other. In other embodiments, similar circuit boards may not have vias.
In the embodiment, the via hole 114 may be a hollow Plated Through Hole (PTH), but the invention is not limited thereto. In some embodiments, the via 114 may be a solid conductive post. In some embodiments, the via hole 114 may also be filled with a resin material or a polymer glass-ceramic mixture, but is not limited thereto.
Referring to fig. 1B, a carrier 10 is provided. Also, the wiring board 110 is placed on the carrier 10 in such a manner that the first electrical connection face 112a of the first wiring layer 112 on the core layer 111 (i.e., the exposed surface of the first wiring layer 112 farthest from the core layer 111) faces the carrier surface 10a of the carrier 10. The carrier 10 may be a carrier tape (carrier tape), such as a blue tape (blue tape), but the present invention is not limited thereto. In other embodiments, the carrier 10 may be a metal substrate, a silicon substrate, a glass substrate, a ceramic substrate, or other suitable carrier that can be used for supporting.
As shown in fig. 1B, after the wiring board 110 is placed on the carrier 10, the first wiring layer 112 contacts the carrier 10. In the present embodiment, the first electrical connection surface 112a of the first circuit layer 112 may directly contact the carrier surface 10a of the carrier 10, but the invention is not limited thereto. In other embodiments, if an adhesive layer (e.g., a release film) is disposed between the circuit board 110 and the carrier 10, the first electrical connection surface 112a of the first circuit layer 112 can indirectly contact the carrier 10. In general, the thickness of the carrier 10 or the wiring board 110 may be a millimeter (mm) grade or a centimeter (cm) grade, and the adhesive layer may be a micrometer (mum) grade. Therefore, the thickness of the adhesive layer can be very thin compared to the thickness of the carrier 10 or the thickness of the circuit board 110, so that even though the circuit board 110 and the carrier 10 have the adhesive layer therebetween, the first circuit layer 112 can be viewed as contacting the carrier 10 by the naked eye.
Referring to fig. 1C, the electronic component 120 is disposed on the carrier 10. Specifically, one side of the electronic component 120 may have a plurality of connection pads 121, and the electronic component 120 is disposed on the carrier 10 in such a manner that the second electrical connection surfaces 121a of the connection pads 121 of the electronic component 120 face the carrier surface 10a of the carrier 10.
As shown in fig. 1C, these connection pads 121 contact the carrier 10 after the electronic component 120 is placed on the carrier 10. In the present embodiment, the second electrical connection surface 121a of each connection pad 121 may directly contact the carrier surface 10a of the carrier 10, but the invention is not limited thereto. In other embodiments, if an adhesive layer (e.g., a release film) is disposed between the electronic component 120 and the carrier 10, the second electrical connection surface 121a of each connection pad 121 may indirectly contact the carrier 10. Taking a Multilayer Ceramic Capacitor (MLCC) as the electronic component 120, the thickness of the 0402 Capacitor is about 500 microns, and the thickness of the 0603 Capacitor is about 800 microns. Therefore, the thickness of the adhesive layer can be very thin compared to the thickness of the electronic component 120, so that even though the electronic component 120 and the carrier 10 have the adhesive layer therebetween, the electronic component 120 can be regarded as contacting the carrier 10 in the general visual field.
In this embodiment, the circuit board 110 may be first placed on the carrier 10, the electronic component 120 may be placed on the carrier 10, and the electronic component 120 may be embedded in the through groove 110c of the circuit board 110, but the invention is not limited thereto. In other embodiments, the electronic component 120 may be first placed on the carrier 10, then the circuit board 110 is placed on the carrier 10, and the through-groove 110c of the circuit board 110 is aligned with the electronic component 120, so that the electronic component 120 is embedded in the through-groove 110c of the circuit board 110.
In the embodiment, the thickness of the circuit board 110 and the thickness of the electronic element 120 may be the same or different, and the invention is not limited thereto. It should be noted that the cross-sectional area of the through-groove 110c of the circuit board 110 is larger than the cross-sectional area of the electronic component 120 on the connecting pad 121 side, so that the electronic component 120 is suitably embedded in the through-groove 110c of the circuit board 110 and the connecting pad 121 of the electronic component 120 is exposed outside the through-groove 110 c.
Referring to fig. 1D, after the circuit board 110 and the electronic component 120 are disposed on the carrier 10 and the electronic component 120 is embedded in the through-groove 110C, a dielectric material layer 130 is formed on the carrier 10, and the dielectric material layer 130 is at least filled in the through-groove 110C (shown in fig. 1C). In this embodiment, a resin (e.g., epoxy), silane (e.g., Hexamethyldisiloxane (HMDSN), Tetraethoxysilane (TEOS), bis (dimethylamino) dimethylsilane (BDMADMS)), or other suitable dielectric material may be coated on the carrier 10 and cured to form the dielectric material layer 130. Therefore, the dielectric material layer 130 can be filled in the through groove 110c and located between the electronic element 120 and the circuit board 110, so that a good buffer is provided between the electronic element 120 and the circuit board 110.
In the embodiment, the dielectric material layer 130 filled in the through groove 110c may contact the carrier 10, but the invention is not limited thereto.
In the present embodiment, the dielectric material layer 130 may include a covering portion 131. The covering portion 131 is located outside the through groove 110c and covers the second circuit layer 113.
In this embodiment, at least one dielectric opening 131a may be formed in the covering portion 131 by etching, grinding, drilling, laser drilling or other suitable manufacturing methods.
In the embodiment, the dielectric opening 131a may expose the via hole 114, but the invention is not limited thereto. In other embodiments, the dielectric opening 131a may expose the third electrical connection surface 113a of the second circuit layer 113 (i.e., the exposed surface of the second circuit layer 113 farthest from the core layer 111).
Referring to fig. 1E, after the dielectric material layer 130 is formed, the carrier 10 (shown in fig. 1D) and the adhesive layer (if any) on the carrier 10 are removed to expose the first electrical connection surfaces 112a of the first circuit layer 112 and the second electrical connection surfaces 121a of the connection pads 121. Since the circuit board 110 and the electronic device 120 are both disposed on the carrier 10 and are in contact with the carrier 10, the first electrical connection surface 112a of the first circuit layer 112 and the second electrical connection surface 121a of each connection pad 121 may be substantially coplanar (coplanar).
In the present embodiment, if the dielectric material layer 130 filled in the through-grooves 110C (shown in fig. 1C) contacts the carrier 10, the dielectric surface 130a of the dielectric material layer 130, the first electrical connection surface 112a of the first circuit layer 112 and the second electrical connection surface 121a of each connection pad 121 may be substantially coplanar.
In addition, the structure of fig. 1D may be turned upside down (upside down) before or after the removal of the carrier 10, so that the structure shown in fig. 1E may be constructed after the removal of the carrier 10.
Referring to fig. 1F, a connection line layer 140 is formed. The connection wire layer 140 is a layer covering and contacting the first electrical connection surface 112a and each of the second electrical connection surfaces 121 a. The connection line layer 140 may be formed by a redistribution layer process (RDL process) or other suitable patterned conductive line manufacturing method.
One exemplary manner of forming the connection wiring layer 140 may be as follows. First, a seed layer (not shown) may be formed on the first side 110a of the circuit board 110 by sputtering. The seed layer conforms to the first electrical connection surface 112a of the first circuit layer 112, the second electrical connection surface 121a of the connection pad 121, and the dielectric surface 130a of the dielectric material layer 130. Typical seed layers are titanium and/or copper layers, however, the actual material of the seed layer depends on the conductive material to be subsequently formed on the seed layer. Next, a photoresist layer (not shown) is formed on the seed layer. The photoresist layer covers a portion of the seed layer. The photoresist layer may be formed by a photolithography process. The photoresist layer has a plurality of openings corresponding to the first electrical connection surface 112a, the second electrical connection surface 121a and the dielectric surface 130a, so as to expose a portion of the seed layer above the first electrical connection surface 112a, the second electrical connection surface 121a and the dielectric surface 130 a. After forming the photoresist layer, a conductive material layer (not shown) is formed on the seed layer exposed by the opening. A layer of conductive material may be formed on the seed layer by electroplating. The material of the conductive material layer may be similar to that of the seed layer, but the invention is not limited thereto. After the conductive material layer is formed, the photoresist layer and a portion of the conductive material layer on the photoresist layer are removed. Then, the unremoved conductive material layer is used as a mask to remove part of the seed layer uncovered by the conductive material layer. As a result, the unremoved seed layer and the unremoved conductive material layer may form the connection line layer 140.
Referring to fig. 1G, after forming the connection line layer 140, a first dielectric layer 150 is formed on the first side 110a of the circuit board 110. The first dielectric layer 150 may be formed by a deposition manufacturing method or a coating manufacturing method. Then, the first dielectric opening 150a exposing a portion of the first circuit layer 112 and/or a portion of the connection circuit layer 140 may be formed by patterning through a photolithography process and an etching process.
In this embodiment, a second dielectric layer 160 may be formed on the second side 110b of the circuit board 110. The second dielectric layer 160 may be formed by a deposition manufacturing method or a coating manufacturing method. Then, the second dielectric opening 160a exposing a portion of the second circuit layer 113 and/or a portion of the via hole 114 may be formed by patterning through photolithography and etching.
In the present embodiment, after the first dielectric layer 150 is formed, a third circuit layer 170 may be formed on the first dielectric layer 150. The third circuit layer 170 may be formed in a manner similar to that of the connection circuit layer 140, and therefore, the description thereof is omitted. In addition, the conductive material for forming the third circuit layer 170 may be filled in the first dielectric opening 150a of the first dielectric layer 150, so that the third circuit layer 170 may be electrically connected to the first circuit layer 112 and/or the connection circuit layer 140.
In the present embodiment, after the second dielectric layer 160 is formed, the fourth circuit layer 180 may be formed on the second dielectric layer 160. The fourth circuit layer 180 may be formed in a manner similar to that of the connection circuit layer 140, and therefore, the description thereof is omitted. In addition, the conductive material for forming the fourth circuit layer 180 may be filled in the second dielectric opening 160a of the second dielectric layer 160, so that the fourth circuit layer 180 can be electrically connected to the second circuit layer 113 and/or the via hole 114.
Referring to fig. 1G to fig. 1I, the fabrication of the embedded device structure 100 of the present embodiment can be substantially completed through the above-mentioned fabrication. The embedded device structure 100 includes a circuit board 110, an electronic device 120, a dielectric material layer 130, and a connection circuit layer 140. The wiring board 110 has a through groove 110 c. The circuit board 110 includes a core layer 111, a first circuit layer 112, a second circuit layer 113, and at least one via hole 114. The first circuit layer 112 and the second circuit layer 113 are respectively located on two opposite sides of the core layer 111. The through-groove 110c penetrates the first wiring layer 112, the core layer 111, and the second wiring layer 113. The via hole 114 penetrates the core layer 111 to electrically connect the first circuit layer 112 and the second circuit layer 113. The electronic component 120 is disposed in the through groove 110 c. The electronic component 120 includes a plurality of connection pads 121. In the top view, the bonding pads 121 are exposed outside the through-grooves 110 c. In the cross-sectional view, the first electrical connection surface 112a of the first circuit layer 112 is substantially coplanar with the second electrical connection surface 121a of each bonding pad 121. The dielectric material layer 130 is at least filled in the through-groove 110 c. The connection wire layer 140 covers and contacts the first electrical connection surface 112a and each of the second electrical connection surfaces 121 a. The bonding pad 121 is electrically connected to the first circuit layer 112 through the connecting wire layer 140.
In the present embodiment, the dielectric material layer 130 is further filled between each of the connecting pads 121 and the first circuit layer 112. The dielectric material layer 130 has a dielectric surface 130 a. The dielectric surface 130a is substantially coplanar with the first electrical connection surface 112 a. The connection wire layer 140 covers and contacts the first electrical connection surface 112a, the dielectric surface 130a and the second electrical connection surface 121 a.
In the present embodiment, in the cross-sectional view, on a cross-section perpendicular to the first electrical connection surface 112a, a cross-sectional thickness 140h1 of the connection wire layer 140 on the first electrical connection surface 112a, a cross-sectional thickness 140h3 of the connection wire layer 140 on the dielectric surface 130a and a cross-sectional thickness 140h2 of the connection wire layer 140 on the second electrical connection surface 121a are substantially the same.
In the present embodiment, in the top view, the cross-sectional area of the through groove 110c is larger than the surface area of the second electrical connection surface 121 a.
In the present embodiment, the embedded device structure 100 further includes a first dielectric layer 150. The first dielectric layer 150 and the first circuit layer 112 are disposed on the same side of the core layer 111. The first dielectric layer 150 covers at least a portion of the first circuit layer 112 and at least a portion of the connection circuit layer 140. The first dielectric layer 150 has at least one first dielectric opening 150a exposing the first circuit layer 112 or the connection circuit layer 140.
In the present embodiment, the dielectric material layer 130 has a covering portion 131 located outside the through groove 110 c. The cover 131 covers the core layer 111 on the side where the second circuit layer 113 is located. The covering portion 131 covers at least a portion of the second circuit layer 113.
In the present embodiment, the covering portion 131 of the dielectric material layer 130 has at least one dielectric opening 131a exposing the second circuit layer 113 or the via hole 114.
In the present embodiment, the embedded device structure 100 further includes a second dielectric layer 160. The second dielectric layer 160 and the second circuit layer 113 are disposed on the same side of the core layer 111. The second dielectric layer 160 covers at least a portion of the second circuit layer 113 and at least a portion of the via hole 114. The second dielectric layer 160 has at least one second dielectric opening 160a exposing the second circuit layer 113 or the via hole 114.
Based on the above, the electronic component 120 is directly electrically connected to the circuit board 110 through the connection circuit layer 140, and a via hole (not shown) between the electronic component 120 and the circuit board 110 may not be formed or omitted. Therefore, the manufacturing method of the embedded device structure 100 can be simple and the thickness can be thin. In addition, the connection circuit layer 140 can reduce the circuit length between the electronic component 120 and the circuit board 110, thereby reducing the signal transmission time and increasing the transmission rate between different electronic components.
Fig. 2 is a schematic cross-sectional view of a buried device structure according to a second embodiment of the present invention.
The method for manufacturing the embedded component structure 200 of the present embodiment is similar to the method for manufacturing the embedded component structure 100 of the first embodiment, and similar components are denoted by the same reference numerals and have similar functions, materials, or formation manners, and descriptions thereof are omitted. Structurally, the embedded component structure 200 of the present embodiment is similar to the embedded component structure 100 of the first embodiment, and the main differences are: the constituent material of the first dielectric layer 250 comprises a solder mask material and/or the constituent material of the second dielectric layer 260 comprises a solder mask material.
In the present embodiment, the first dielectric layer 250 may be a Dry Film Solder Mask (DFSM) or a Liquid Photosensitive Solder Mask (LPSM). The first dielectric layer 250 has a plurality of first dielectric openings 250 a. The first dielectric opening 250a may expose a portion of the first circuit layer 112, a portion of the connection circuit layer 140 and/or a portion of the via hole 114.
In this embodiment, the second dielectric layer 260 may be a dry film solder mask or a liquid photosensitive solder mask. The second dielectric layer 260 has at least one second dielectric opening 260 a. The second dielectric opening 260a may expose a corresponding portion of the via hole 114. In other embodiments, the second dielectric opening 260a may expose a corresponding portion of the second circuit layer 113.
Fig. 3A to fig. 3E are schematic cross-sectional views illustrating a method for manufacturing an embedded device structure according to a third embodiment of the invention.
The method for manufacturing the embedded component structure 300 of the present embodiment is similar to the method for manufacturing the embedded component structure 100 of the first embodiment, and similar components are denoted by the same reference numerals and have similar functions, materials, or formation manners, and descriptions thereof are omitted.
Referring to fig. 3A, a circuit board 310' is provided. Structurally, the circuit board 310' in fig. 3A is similar to the circuit board 110 in fig. 1A, and the main difference is: the wiring board 310' does not have vias (not shown because none).
Next, the circuit board 310' and the electronic component 120 may be placed on the carrier 10 by steps similar to those in fig. 1A to 1D, and the electronic component 120 is embedded in the through groove 110 c. Then, a dielectric material layer 130 is formed on the carrier 10, and the dielectric material layer 130 is at least filled in the through-groove 110c (shown in fig. 3A) to form the structure shown in fig. 3B.
Referring to fig. 3C, before or after removing the carrier 10, the structure of fig. 3B may be turned upside down, so that after removing the carrier 10, at least one through hole 310e may be formed on the circuit board 310' by etching, grinding, drilling, laser drilling or other suitable manufacturing methods. The via 310e passes through the core layer 111, the first circuit layer 112 and the second circuit layer 113.
It should be noted that, in the present embodiment, the sequence of the step of removing the carrier 10, the step of turning the carrier upside down, and the step of forming the at least one through hole 310e is not limited. That is, the three steps can be adjusted in front and back order according to the requirement of the manufacturing method.
In the embodiment, since the electronic component 120 is embedded in the through-groove 110c (shown in fig. 3A) of the circuit board 310', and the dielectric material layer 130 filled in the through-groove 110c can fix the electronic component 120 in the through-groove 110c and provide good buffering between the electronic component 120 and the circuit board 310'. Therefore, in the process of forming the through hole 310e, the electronic component 120 or the circuit board 310 'may be affected by stress (e.g., the electronic component 120 or the circuit board 310' may be stressed due to vibration during grinding and drilling), but the offset of the electronic component 120 may still be reduced.
Referring to fig. 3D, after removing the carrier 10 (shown in fig. 3B) and forming at least one via 310e (shown in fig. 3C), the connection line layer 140 is formed. Furthermore, a conductive material is filled into the through hole 310e by a method similar to the connection line layer 140 to form the via hole 114. For example, the via hole 114 and the connection line layer 140 may be formed by the same manufacturing method. The seed layer for forming the connection line layer 140 or the conductive material covering the seed layer may be filled into the via hole 310e to form the via hole 314. The via hole 314 may be electrically connected to the first circuit layer 112 and the second circuit layer 113. In this way, the circuit board 310 having the core layer 111, the first circuit layer 112, the second circuit layer 113, and the via hole 314 can be configured.
Referring to fig. 3E, after forming the connection line layer 140 and the via hole 314, a first dielectric layer 350 may be formed on the first side 310a of the circuit board 310. The first dielectric layer 350 has at least one first dielectric opening 350 a. The first dielectric opening 350a exposes a portion of the first circuit layer 112, a portion of the connection circuit layer 140 and/or a portion of the via hole 314.
In this embodiment, a second dielectric layer 360 may be formed on the second side 310b of the circuit board 310. The second dielectric layer 360 has at least one second dielectric opening 360 a. The second dielectric opening 360a exposes a portion of the second circuit layer 113 and/or a portion of the via 314.
In other embodiments, the first dielectric layer 350 and/or the second dielectric layer 360 may be a dry film solder mask or a liquid photosensitive solder mask.
The embedded device structure 300 of the present embodiment can be substantially completed through the above-mentioned manufacturing process. The embedded component structure 300 of the present embodiment is similar to the embedded component structure 100 of the first embodiment, with the difference that: the embedded device structure 300 of the present embodiment is fabricated by first embedding the electronic device 120 into the through-groove 110c of the circuit board 310' without the via hole, and then forming the circuit board 310 with the via hole 314.
Fig. 4A, fig. 4B and fig. 4D are schematic bottom views illustrating a method for manufacturing an embedded device structure according to a fourth embodiment of the invention. Fig. 4C, fig. 4E to fig. 4H are schematic cross-sectional views illustrating a method for manufacturing an embedded device structure according to a fourth embodiment of the invention.
The method for manufacturing the embedded device structure 400 of the present embodiment is similar to the method for manufacturing the embedded device structure 100 of the first embodiment, and similar components are denoted by the same reference numerals and have similar functions, materials, or formation manners, and descriptions thereof are omitted.
Referring to fig. 4A, a circuit board 410' is provided. Structurally, the circuit board 410' in fig. 4A is similar to the circuit board 110 in fig. 1A, and the main difference is that: the circuit board 410' does not have a through slot (not shown because none).
Referring to fig. 4B and fig. 4C, a circuit board 410 having a through groove 410C is formed. For example, a portion of the first circuit layer 112 and a portion of the core layer 111 of the first circuit layer 112 of the circuit board 410' (shown in fig. 4A) may be removed by etching, grinding, drilling, laser drilling or other suitable manufacturing methods to form the circuit board 410 with the through-grooves 410 c.
In the embodiment, the through groove 410c and the at least one via hole 114 may be structurally communicated with each other, but the invention is not limited thereto. In other embodiments, the through groove 410c and the via hole 114 may be separated from each other.
Next, the wiring board 410 having the through groove 410c is placed on the carrier 10. In general, in order to reduce damage or unevenness of the carrier surface 10a of the carrier 10, the circuit board 410 having the through grooves 410c may be formed first, and then the circuit board 410 having the through grooves 410c may be placed on the carrier 10.
Referring to fig. 4D and fig. 4E, the electronic component 120 is disposed on the carrier 10.
In this embodiment, the circuit board 410 may be first placed on the carrier 10, the electronic component 120 may be placed on the carrier 10, and the electronic component 120 may be embedded in the through groove 410c of the circuit board 410, but the invention is not limited thereto. In other embodiments, the electronic component 120 may be first placed on the carrier 10, then the circuit board 410 is placed on the carrier 10, and the through-groove 410c of the circuit board 410 is aligned with the electronic component 120, so that the electronic component 120 is embedded in the through-groove 410c of the circuit board 410.
In the present embodiment, the through groove 410c is located between the plurality of via holes 114', 114 ″ and can be structurally communicated with the via holes 114', 114 ″, and the electronic component 120 is located between the via holes 114', 114 ″. Therefore, the through holes 114', 114 ″ corresponding to the connection pads 121 of the electronic component 120 are electrically separated from each other by the through groove 410 c.
Referring to fig. 4F, after the circuit board 410 and the electronic component 120 are disposed on the carrier 10 and the electronic component 120 is embedded in the through-groove 410c, the dielectric material layer 130 is formed on the carrier 10, and the dielectric material layer 130 is at least filled in the through-groove 410c (shown in fig. 4D). The dielectric material layer 130 may include a cover 131. The covering portion 131 is located outside the through groove 410c and covers the second circuit layer 113. The covering portion 131 has at least one dielectric opening 131 a. The dielectric opening 131a may expose the third electrical connection surface 113a of the second circuit layer 113.
Referring to fig. 4G, the structure of fig. 4F may be turned upside down before or after the carrier 10 is removed. And, after removing the carrier 10, the connection wiring layer 140 is formed. The connection wire layer 140 covers and contacts the first electrical connection surface 112a and each of the second electrical connection surfaces 121 a. The connection circuit layer 140 is electrically connected to the second circuit layer 113 through the corresponding via hole 114.
Referring to fig. 4H, after the connection line layer 140 is formed, a first dielectric layer 450 is formed on the first side 410a of the circuit board 410. The first dielectric layer 450 has at least one first dielectric opening 450 a. The first dielectric opening 450a exposes a portion of the connection line layer 140.
In this embodiment, a second dielectric layer 460 may be formed on the second side 410b of the circuit board 410. The second dielectric layer 460 has at least one second dielectric opening 460 a. The second dielectric opening 460a exposes a portion of the second circuit layer 113.
In other embodiments, the first dielectric layer 450 and/or the second dielectric layer 460 may be a dry film solder mask or a liquid photosensitive solder mask.
The embedded device structure 400 of the present embodiment can be substantially completed through the above-mentioned manufacturing process. The embedded component structure 400 of the present embodiment is similar to the embedded component structure 100 of the first embodiment, with the difference that: the through groove 410c of the circuit board 410 and the at least one via hole 114 may be structurally communicated.
Fig. 5A to 5F are schematic cross-sectional views illustrating a method for manufacturing an embedded device structure according to a fifth embodiment of the invention. Fig. 5G is a schematic top view of a buried device structure according to a fifth embodiment of the invention.
The method for manufacturing the embedded component structure 500 of the present embodiment is similar to the method for manufacturing the embedded component structure 300 of the third embodiment, and similar components are denoted by the same reference numerals and have similar functions, materials, or formation manners, and descriptions thereof are omitted.
Referring to fig. 5A, the circuit board 310' and the electronic component 520 may be disposed on the carrier 10 by steps similar to those in fig. 1A to 1C, and the electronic component 520 is embedded in the through groove 110C.
In the embodiment, one side of the electronic device 520 may have a plurality of first connecting pads 521, and one side of the electronic device 520 may have a second connecting pad 522. And the electronic component 520 is placed on the carrier 10 in such a way that the second electrical connection surface 521a of each first connection pad 521 of the electronic component 520 faces the carrier surface 10a of the carrier 10. In the embodiment, the second electrical connection surface 521a of each first connection pad 521 may directly contact the carrier surface 10a of the carrier 10, but the invention is not limited thereto. In other embodiments, if an adhesive layer (not shown) is disposed between the electronic component 520 and the carrier 10, the second electrical connection surface 521a of each first connection pad 521 may indirectly contact the carrier 10. For example, a Vertical Cavity Surface Emitting Laser (VCSEL) die, a Light Emitting Diode (LED) die, or other active device may be used as the electronic device 520, and the thickness thereof may be on the order of microns to millimeters. Therefore, the thickness of the adhesive layer can be very thin compared to the thickness of the electronic component 520, so that even though the electronic component 520 has the adhesive layer between the carrier 10, the electronic component 520 can be regarded as contacting the carrier 10 in the general visual sense of the naked eye.
In this embodiment, the circuit board 310 'may be first placed on the carrier 10, the electronic component 520 may be placed on the carrier 10, and the electronic component 520 may be embedded in the through groove 110c of the circuit board 310', but the invention is not limited thereto. In other embodiments, the electronic component 520 may be first placed on the carrier 10, the circuit board 310' may be placed on the carrier 10, and the through-hole 110c of the circuit board 310' is aligned with the electronic component 520, so that the electronic component 520 is embedded in the through-hole 110c of the circuit board 310 '.
In the embodiment, the thickness of the circuit board 310' may be the same as or different from the thickness of the electronic element 520, and the invention is not limited thereto. It should be noted that the cross-sectional area of the through-groove 110c of the circuit board 310 'needs to be larger than the cross-sectional area of the electronic element 520 at the side of the first connection pads 521, so that the electronic element 520 is suitably embedded in the through-groove 110c of the circuit board 310' and the first connection pads 521 of the electronic element 520 are exposed outside the through-groove 110 c.
Referring to fig. 5B, after the circuit board 310' and the electronic device 520 are disposed on the carrier 10 and the electronic device 520 is embedded in the through-groove 110c (shown in fig. 5A), a first dielectric material layer 530 is formed on the carrier 10, and the first dielectric material layer 530 is at least filled in the through-groove 110 c. The first dielectric material layer 530 may include an overlay 531. The covering portion 531 is located outside the through groove 110c and covers the second circuit layer 113. The cover 531 has a dielectric opening 531 a. The dielectric opening 531a may expose the third electrical connection surface 113a of the second circuit layer 113 and the second connection pad 522 of the electronic component 520.
The material forming manner of the first dielectric material layer 530 may be the same as or similar to the material forming manner of the dielectric material layer 130 in the foregoing embodiments, and therefore, the description thereof is omitted.
Referring to fig. 5C, after the first dielectric material layer 530 is formed, the carrier 10 is removed to expose the first electrical connection surface 112a of the first circuit layer 112 and the second electrical connection surface 521a of each of the first connection pads 521. Since the circuit board 310' and the electronic device 520 are disposed on the carrier 10 and contact the carrier 10, the first electrical connection surface 112a of the first circuit layer 112 and the second electrical connection surface 521a of each first connection pad 521 may be substantially coplanar.
In the present embodiment, if the first dielectric material layer 530 filled in the through-groove 110c contacts the carrier 10, the dielectric surface 530a of the first dielectric material layer 530, the first electrical connection surface 112a of the first circuit layer 112 and the second electrical connection surface 521a of each connection pad 121 may be substantially coplanar.
In addition, before or after the carrier 10 is removed, the structure of fig. 5B may be turned upside down, so that after the carrier 10 is removed, the structure as shown in fig. 5C may be formed.
With continued reference to fig. 5C, after removing the carrier 10, a second dielectric material layer 535 is formed on the first side 310'a of the circuit board 310'. The second dielectric material layer 535 has a dielectric opening 535 a. The dielectric opening 535a may expose the dielectric surface 530a of the first dielectric material layer 530, the first electrical connection surface 112a of the first circuit layer 112, and the second electrical connection surface 521a of each of the first connection pads 521.
The material forming manner of the second dielectric material layer 535 may be the same as or similar to the material forming manner of the first dielectric material layer 530, and therefore, the description thereof is omitted.
Referring to fig. 5D, after forming the second dielectric material layer 535, at least one via 310e may be formed on the circuit board 310' (shown in fig. 5C) by etching, grinding, drilling, laser drilling, or other suitable manufacturing methods. The via 310e passes through the core layer 111, the first circuit layer 112 and the second circuit layer 113.
In the embodiment, since the electronic component 520 is embedded in the through-groove 110c of the circuit board 310', and the dielectric material layer 530 filled in the through-groove 110c can fix the electronic component 520 in the through-groove 110c, and provide a good buffer between the electronic component 520 and the circuit board 310'. Therefore, in the process of forming the through hole 310e, the electronic component 520 or the circuit board 310 'may be affected by stress (e.g., the vibration generated during the grinding and drilling process may cause stress between the electronic component 520 or the circuit board 310'), but the offset of the electronic component 520 may still be reduced.
Referring to fig. 5E, after the via 310E (shown in fig. 5D) is formed, the connection line layer 140 is formed. Furthermore, a conductive material is filled into the through hole 310e by a method similar to the connection line layer 140 to form a via hole 314. In this way, the circuit board 310 having the core layer 111, the first circuit layer 112, the second circuit layer 113, and the via hole 314 can be configured.
In the present embodiment, a circuit layer 590 may be formed on the second circuit layer 113 and/or the second connecting pad 522. The circuit layer 590 may be formed in a manner similar to that of the connection circuit layer 140, and therefore, will not be described herein. In addition, the conductive material for forming the circuit layer 590 may fill the dielectric opening 531a of the second dielectric material layer 535, so that the circuit layer 590 may be electrically connected to the second circuit layer 113 and/or the via 314.
Referring to fig. 5F and 5G, after the connection line layer 140 and the via hole 314 are formed, a first dielectric layer 350 is formed on the first side 310a of the circuit board 310. The first dielectric layer 350 has at least one first dielectric opening 350 a. The first dielectric opening 350a exposes a portion of the connection line layer 140 and/or a portion of the via hole 314.
In this embodiment, a second dielectric layer 360 may be formed on the second side 310b of the circuit board 310. The second dielectric layer 360 has at least one second dielectric opening 360 a. The second dielectric opening 360a exposes a portion of the circuit layer 590 and/or a portion of the via 314.
Structurally, the embedded component structure 500 of the present embodiment is similar to the embedded component structure 300 of the third embodiment, and the main differences are: the connecting pads 521 and 522 of the electronic component 520 have different configurations.
Fig. 6 is a schematic cross-sectional view of a buried device structure according to a sixth embodiment of the present invention.
The embedded component structure 600 of the present embodiment is similar to the embedded component structure 500 of the fifth embodiment, and similar components are denoted by the same reference numerals, and have similar functions, materials, or formation manners, and descriptions thereof are omitted. Structurally, the embedded component structure 600 of the present embodiment is similar to the embedded component structure 500 of the fifth embodiment, and the main differences are: the first dielectric layer 650 has a first dielectric opening 650a exposing the electronic element 520.
Fig. 7 is a schematic cross-sectional view of a buried device structure according to a seventh embodiment of the present invention.
The embedded component structure of this embodiment is similar to the embedded component structure 600 of the sixth embodiment, and similar components are denoted by the same reference numerals, and have similar functions, materials, or formation manners, and descriptions thereof are omitted. Structurally, the embedded component structure 700 of the present embodiment is similar to the embedded component structure 600 of the sixth embodiment, and the main differences are: in the embedded component structure 700 of the present embodiment, the through groove 410c (shown in fig. 4B) of the circuit board 410 and the at least one via hole 114 may be structurally communicated with each other. For example, the wiring board 410 in which the through groove 410C and the via hole 114 can be structurally communicated with each other can be formed by the manufacturing method as shown in fig. 4A to 4C.
In summary, in the embedded device structure of the present invention, the electronic device is directly electrically connected to the circuit board through the connection circuit layer, and the formation of the via hole between the electronic device and the circuit board is not required or omitted. Therefore, the manufacturing method of the embedded element structure can be simpler, and the thickness can be thinner. In addition, the circuit length between the electronic element and the circuit board can be reduced through the connecting circuit layer, so that the signal transmission time can be reduced, and the transmission rate between different electronic elements can be improved.
Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.
Claims (3)
1. An embedded component structure, comprising:
a circuit board having a through slot, and the circuit board comprising:
a core layer;
a first circuit layer;
the second circuit layer and the first circuit layer are respectively positioned at two opposite sides of the core layer, and the through groove at least penetrates through the first circuit layer and the core layer; and
at least one via hole penetrating through the core layer to electrically connect the first circuit layer and the second circuit layer;
the electronic element is arranged in the through groove, wherein one side of the electronic element is provided with a plurality of first connecting pads, the other side of the electronic element opposite to the one side is provided with a second connecting pad, and a first electrical connection surface of the first circuit layer is coplanar with a second electrical connection surface of each first connecting pad;
a first dielectric material layer filled in the through-groove and between each of the first connection pads and the first circuit layer, and having a dielectric surface coplanar with the first electrical connection surface, wherein the first dielectric material layer has a covering portion located outside the through-groove, covering a side of the core layer where the second circuit layer is located, and covering at least a portion of the second circuit layer, the covering portion of the first dielectric material layer having at least one dielectric opening exposing the second circuit layer or the via hole;
a second dielectric material layer disposed on the first circuit layer and the electronic element, wherein the second dielectric material layer has an opening to expose the dielectric surface of the first dielectric material layer, the first electrical connection surface of the first circuit layer, and the second electrical connection surface of each of the first connection pads;
a connection circuit layer covering and contacting the first electrical connection surface, the dielectric surface and each of the second electrical connection surfaces, wherein the plurality of first connection pads are electrically connected to the first circuit layer only through the connection circuit layer;
the circuit layer is arranged on the second circuit layer and the second connecting pad and is electrically connected with the second circuit layer and the through hole;
a first dielectric layer disposed on the same side of the core layer as the first circuit layer, covering at least a portion of the first circuit layer and at least a portion of the connection circuit layer, and having at least a first dielectric opening exposing the electronic component or the connection circuit layer, wherein the first dielectric layer comprises solder resist material; and
a second dielectric layer covering the covering portion of the first dielectric material layer and having at least one second dielectric opening exposing the circuit layer or the via hole, wherein the second dielectric layer comprises solder mask material,
the cross-sectional thickness of the connection circuit layer on the first electrical connection surface, the dielectric surface and the second electrical connection surface is consistent on the cross-section perpendicular to the first electrical connection surface, and the cross-sectional area of the through groove is larger than the surface area of the electronic element on the second electrical connection surface.
2. A method of manufacturing an embedded component structure, comprising:
providing a vector;
placing a circuit board on the carrier, the circuit board having a through slot, and the circuit board comprising:
a core layer;
a first circuit layer, wherein the first circuit layer contacts the carrier; and
the second circuit layer and the first circuit layer are respectively positioned at two opposite sides of the core layer, and the through groove at least penetrates through the first circuit layer and the core layer;
placing an electronic component on the carrier, wherein one side of the electronic component is provided with a plurality of first connecting pads, and the other side of the electronic component opposite to the one side is provided with a second connecting pad, and the plurality of first connecting pads are contacted with the carrier;
after the circuit board and the electronic element are placed on the carrier and the electronic element is embedded in the through groove, a first dielectric material layer is formed on the carrier and at least filled in the through groove, wherein the first dielectric material layer is provided with a covering part positioned outside the through groove, covers one side of the core layer where the second circuit layer is positioned, and covers at least part of the second circuit layer;
forming at least one dielectric opening on the covering part of the first dielectric material layer, wherein the at least one dielectric opening exposes the second circuit layer;
removing the carrier to expose the first circuit layer and the first connection pads, wherein a first electrical connection surface of the first circuit layer is coplanar with a second electrical connection surface of each first connection pad;
forming a second dielectric material layer on the first circuit layer and the electronic element, the second dielectric material layer having an opening to expose a dielectric surface of the first dielectric material layer, the first electrical connection surface of the first circuit layer, and the second electrical connection surface of each of the first connection pads;
forming at least one through hole penetrating through the core layer, the first circuit layer and the second circuit layer on the circuit board;
filling a conductive material into the at least one through hole to form at least one through hole penetrating through the core layer so as to electrically connect the first circuit layer and the second circuit layer;
after removing the carrier, forming a connection circuit layer, wherein the connection circuit layer covers and contacts the first electrical connection surface and each second electrical connection surface;
forming a circuit layer on the second circuit layer and the second connection pad;
after the connection circuit layer is formed, forming a first dielectric layer, wherein the first dielectric layer covers at least part of the first circuit layer and at least part of the connection circuit layer and is provided with at least one first dielectric opening for exposing the electronic element or the connection circuit layer, and the composition material of the first dielectric layer comprises solder mask material;
forming a second dielectric layer overlying the overlying portion of the first dielectric material layer, wherein a constituent material of the second dielectric layer comprises a solder mask material; and
at least one second dielectric opening is formed on the second dielectric layer, and the circuit layer is exposed out of the at least one second dielectric opening.
3. The method as claimed in claim 2, wherein after the forming of the connection trace layer, the first connection pads are electrically connected to the first trace layer only through the connection trace layer.
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| US201862645784P | 2018-03-20 | 2018-03-20 | |
| US62/645,784 | 2018-03-20 | ||
| CN201810842418.5A CN110310937B (en) | 2018-03-20 | 2018-07-27 | Embedded element structure and manufacturing method thereof |
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| CN201810842418.5A Division CN110310937B (en) | 2018-03-20 | 2018-07-27 | Embedded element structure and manufacturing method thereof |
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| TWI715261B (en) * | 2019-10-23 | 2021-01-01 | 強茂股份有限公司 | Chip size packaging structure and manufacturing method thereof |
| US11049781B1 (en) | 2020-02-13 | 2021-06-29 | Panjit International Inc. | Chip-scale package device |
| TWI856865B (en) * | 2022-09-29 | 2024-09-21 | 璦司柏電子股份有限公司 | Embedded thermal and electrical separation circuit board with ceramic substrate and power transistor |
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| TWI269365B (en) * | 2005-08-08 | 2006-12-21 | Advanced Semiconductor Eng | Substrate process and structure for embedded component |
| TWI264051B (en) * | 2005-08-08 | 2006-10-11 | Advanced Semiconductor Eng | Substrate process for embedded component |
| TWI298941B (en) * | 2006-04-19 | 2008-07-11 | Advanced Semiconductor Eng | Method of fabricating substrate with embedded component therein |
| KR20090130727A (en) * | 2008-06-16 | 2009-12-24 | 삼성전기주식회사 | Electronic component embedded printed circuit board and manufacturing method |
| TWI453877B (en) * | 2008-11-07 | 2014-09-21 | Advanced Semiconductor Eng | Structure and process of embedded chip package |
| CN103219306A (en) * | 2012-01-19 | 2013-07-24 | 欣兴电子股份有限公司 | Package structure embedded with electronic components and its manufacturing method |
| CN103906372B (en) * | 2012-12-27 | 2017-03-01 | 碁鼎科技秦皇岛有限公司 | There is circuit board of embedded element and preparation method thereof |
| TW201436684A (en) * | 2013-03-01 | 2014-09-16 | Unimicron Technology Corp | Circuit board having embedded electronic component and method of manufacture |
| JP6503687B2 (en) * | 2014-10-23 | 2019-04-24 | イビデン株式会社 | Printed wiring board |
| TWI539874B (en) * | 2014-11-07 | 2016-06-21 | 欣興電子股份有限公司 | Buried component packaging structure and manufacturing method thereof |
| TWI581688B (en) * | 2014-11-13 | 2017-05-01 | 欣興電子股份有限公司 | Embedded component package structure and manufacturing method thereof |
| TWI553792B (en) * | 2014-12-02 | 2016-10-11 | 旭德科技股份有限公司 | Package structure and manufacturing method thereof |
| TWI546908B (en) * | 2014-12-22 | 2016-08-21 | 恆勁科技股份有限公司 | Package structure and method of fabricating the same |
-
2018
- 2018-07-27 CN CN201810842418.5A patent/CN110310937B/en active Active
- 2018-07-27 TW TW107126005A patent/TWI672079B/en active
- 2018-07-27 CN CN202111495773.8A patent/CN114286514A/en not_active Withdrawn
Also Published As
| Publication number | Publication date |
|---|---|
| CN110310937B (en) | 2022-08-16 |
| TWI672079B (en) | 2019-09-11 |
| CN110310937A (en) | 2019-10-08 |
| TW201941672A (en) | 2019-10-16 |
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