CN112188731B - Embedded element structure and manufacturing method thereof - Google Patents

Abstract

The invention provides an embedded element structure, which includes a circuit board, an electronic element, a dielectric material layer and a connecting circuit layer. The circuit board has through grooves and includes a core layer, a first circuit layer, a second circuit layer and a through hole. The first circuit layer and the second circuit layer are located on opposite sides of the core layer. The through groove penetrates the first circuit layer and the core layer. The via hole electrically connects the first circuit layer and the second circuit layer. The electronic components are arranged in the through grooves and include a plurality of connection pads. The first electrical connection surface of the first circuit layer is coplanar with the second electrical connection surface of the connection pad. The dielectric material layer is filled in the through groove. The Young's modulus of the core layer is greater than that of the dielectric material layer. The connection circuit layer contacts the first electrical connection surface and the second electrical connection surface. A manufacturing method of the embedded device structure is also proposed.

Description

Embedded element structure and its manufacturing method

technical field

The invention relates to an electronic component and a manufacturing method thereof, in particular to an embedded component structure and a manufacturing method thereof.

Background technique

In a general embedded component structure, at least a conductive through via is used to connect the electronic component to a printed circuit board (PCB). However, the above-mentioned connection method will make the electrical transmission path between the electronic components and the printed circuit board long, which may result in a high degree of attenuation of the power and/or signal of the electronic product, and is also prone to noise ( noise), thus reducing the quality of electronic products. In addition, the manufacturing method of such an embedded element structure is relatively complicated, and the thickness is relatively thick.

SUMMARY OF THE INVENTION

The present invention provides an embedded element structure and a manufacturing method thereof, the thickness of which can be relatively thin and the manufacturing method can be relatively simple.

The embedded element structure of the present invention includes a circuit board, an electronic element, a dielectric material layer and a connecting circuit layer. The circuit board has through-slots. The circuit board includes a core layer, a first circuit layer, a second circuit layer and at least one via hole. The first circuit layer and the second circuit layer are respectively located on opposite sides of the core layer. The through groove runs through at least the first circuit layer and the core layer. The via hole penetrates through the core layer to electrically connect the first circuit layer and the second circuit layer. The electronic components are arranged in the through grooves. The electronic component includes a plurality of connection pads exposed out of the through-grooves. The first electrical connection surface of the first circuit layer is coplanar with the second electrical connection surface of each connection pad. The dielectric material layer is filled at least in the through groove. The Young's modulus of the core layer is greater than that of the dielectric material layer. The connection circuit layer covers and contacts the first electrical connection surface and each of the second electrical connection surfaces. The connection pad is electrically connected to the first circuit layer through the connection circuit layer.

In an embodiment of the present invention, the above-mentioned dielectric material layer is further filled between each connection pad and the first circuit layer. The dielectric material layer has a dielectric surface coplanar with the first electrical connection surface. The connection circuit layer covers and contacts the first electrical connection surface, the dielectric surface and the second electrical connection surface.

In an embodiment of the present invention, on a cross section perpendicular to the first electrical connection surface, the cross-sectional thicknesses of the above-mentioned connecting circuit layer on the first electrical connection surface, the dielectric surface and the second electrical connection surface are the same .

In an embodiment of the present invention, the cross-sectional area of the above-mentioned through groove is larger than the surface area of the electronic device on the second electrical connection surface.

In an embodiment of the present invention, the above-mentioned embedded device structure further includes a first dielectric layer. The first dielectric layer and the first wiring layer are disposed on the same side of the core layer. The first dielectric layer covers at least part of the first circuit layer and at least part of the connection circuit layer, and the first dielectric layer has at least one opening exposing the first circuit layer or the connection circuit layer.

In an embodiment of the present invention, the above-mentioned constituent material of the first dielectric layer includes a solder resist material.

In an embodiment of the present invention, the above-mentioned dielectric material layer has a covering portion located outside the through-groove. The cover part covers the side of the core layer where the second circuit layer is located, and the cover part covers at least part of the second circuit layer.

In an embodiment of the present invention, the covering portion of the above-mentioned dielectric material layer has at least one dielectric opening exposing the second circuit layer or the via hole.

In an embodiment of the present invention, the above-mentioned embedded device structure further includes a second dielectric layer. The second dielectric layer covers the cover portion of the dielectric material layer, and the second dielectric layer has at least one opening exposing the second circuit layer or the via hole.

In an embodiment of the present invention, the constituent material of the above-mentioned second dielectric layer includes a solder resist material.

In an embodiment of the present invention, the above-mentioned through-groove communicates with at least one via hole.

The manufacturing method of the embedded element structure of the present invention includes the following steps. Provide a carrier. Place the circuit board on the carrier. The circuit board has through-slots. The circuit board includes a core layer, a first circuit layer and a second circuit layer. The first wiring layer contacts the carrier. The first circuit layer and the second circuit layer are respectively located on opposite sides of the core layer. The through groove runs through at least the first circuit layer and the core layer. The electronic components are placed on the carrier. Electronic components have multiple connection pads. These connection pads contact the carrier. After placing the circuit board and the electronic components on the carrier and embedding the electronic components in the through grooves, a dielectric material layer is formed on the carrier. The dielectric material layer is filled at least in the through groove. The Young's modulus of the core layer is greater than that of the dielectric material layer. The carrier is removed to expose the first wiring layer and these connection pads. The first electrical connection surface of the first circuit layer is coplanar with the second electrical connection surface of each connection pad. After the carrier is removed, the connection wiring layer is formed. The connection circuit layer covers and contacts the first electrical connection surface and each of the second electrical connection surfaces.

In an embodiment of the present invention, the above-mentioned circuit board further includes at least one via hole. The via hole penetrates through the core layer to electrically connect the first circuit layer and the second circuit layer.

In an embodiment of the present invention, the above-mentioned through-grooves and the via holes communicate with each other.

In an embodiment of the present invention, the above-mentioned manufacturing method of the embedded element structure further includes the following steps. After forming the connection line layer, a first dielectric layer is formed. The first dielectric layer covers at least part of the first wiring layer and at least part of the connecting wiring layer.

In an embodiment of the present invention, the above-mentioned constituent material of the first dielectric layer includes a solder resist material.

In an embodiment of the present invention, the above-mentioned manufacturing method of the embedded element structure further includes the following steps. After the dielectric material layer is formed, at least through holes penetrating the core layer, the first circuit layer and the second circuit layer are formed on the circuit board. A conductive material is filled in at least one through hole to form at least one through hole penetrating through the core layer. The via hole electrically connects the first circuit layer and the second circuit layer.

In an embodiment of the present invention, the above-mentioned dielectric material layer has a covering portion located outside the through-groove. The covering part covers the side of the core layer where the second circuit layer is located, and covers at least part of the second circuit layer.

In an embodiment of the present invention, the above-mentioned manufacturing method of the embedded element structure further includes the following steps. At least one dielectric opening is formed on the covering portion of the dielectric material layer. The dielectric opening exposes the second wiring layer.

In an embodiment of the present invention, the above-mentioned manufacturing method of the embedded element structure further includes the following steps. A second dielectric layer is formed. The second dielectric layer covers the cover portion of the dielectric material layer.

In an embodiment of the present invention, the above-mentioned manufacturing method of the embedded element structure further includes the following steps. At least one second opening is formed on the second dielectric layer. The second opening exposes the second circuit layer.

In an embodiment of the present invention, the constituent material of the above-mentioned second dielectric layer includes a solder resist material.

Based on the above, in the embedded component structure of the present invention, the electronic component and the circuit board are directly electrically connected by connecting the circuit layer, and the via hole between the electronic component and the circuit board may not need to be formed or omitted. Therefore, the manufacturing method of the embedded element structure can be relatively simple, and the thickness can be relatively thin. In addition, by connecting the circuit layers, the length of the circuit between the electronic component and the circuit board can be reduced, the signal transmission time (ie, the delay time) can be reduced, and the transmission rate between different electronic components can be improved.

In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, the following embodiments are given and described in detail with the accompanying drawings as follows.

Description of drawings

1A to 1H are schematic cross-sectional views of a method for manufacturing an embedded element structure according to a first embodiment of the present invention;

1I is a schematic top view of an embedded element structure according to the first embodiment of the present invention;

2 is a schematic cross-sectional view of an embedded element structure according to a second embodiment of the present invention;

3A to 3E are schematic cross-sectional views of a method for manufacturing an embedded device structure according to a third embodiment of the present invention;

4A, FIG. 4B and FIG. 4D are schematic bottom views of a method for manufacturing an embedded element structure according to a fourth embodiment of the present invention;

4C, FIG. 4E to FIG. 4H are schematic cross-sectional views of a method for manufacturing an embedded element structure according to a fourth embodiment of the present invention;

5A to 5F are schematic cross-sectional views of a method for manufacturing an embedded element structure according to a fifth embodiment of the present invention;

5G is a schematic top view of a buried element structure according to the fifth embodiment of the present invention;

6 is a schematic cross-sectional view of a buried element structure according to a sixth embodiment of the present invention;

7 is a schematic cross-sectional view of a buried element structure according to a seventh embodiment of the present invention;

8 is a schematic cross-sectional view of an embedded element structure according to an eighth embodiment of the present invention;

9 is a schematic cross-sectional view of an embedded element structure according to a ninth embodiment of the present invention.

Description of reference numbers:

100, 200, 300, 400, 500, 600, 700, 800, 900: Embedded element structure

110, 310', 310, 410', 410: circuit board

110a, 310'a, 310a, 410a: first side

110b, 310b, 410b: second side

110c, 410c: Grooving

310e: Through hole

111: Core layer

111d: Core layer sidewalls

112, 112', 112": the first circuit layer

112a: the first electrical connection surface

112d: sidewall of the first circuit layer

113: Second circuit layer

113a: the third electrical connection surface

113d: Sidewall of the second circuit layer

114, 114', 114", 314: Vias

120, 520, 820, 920: Electronic components

820a: Active side

820b: Back

920a: Sensing area

121, 821: Connection pad

121a, 521a, 821a: the second electrical connection surface

521: First connection pad

522: Second connection pad

130: Dielectric material layer

130a, 530a: Dielectric surface

530: First Dielectric Material Layer

131, 531: Covering Department

131a, 531a: Dielectric openings

535: Second Dielectric Material Layer

535a: Dielectric Opening

140: Connect the circuit layer

140h1, 140h2, 140h3: Thickness

150, 250, 350, 450, 650: first dielectric layer

150a, 250a, 350a, 450a, 650a: first dielectric openings

160, 260, 360, 460: Second Dielectric Layer

160a, 260a, 360a, 460a: second dielectric openings

170: The third circuit layer

180: Fourth circuit layer

590: circuit layer

10: Carrier

20: Cooling components

30: Protective layer

10a: carrier surface

R: region

Detailed ways

The foregoing and other technical contents, features and effects of the present invention will be clearly presented in the following detailed description of the embodiments with reference to the accompanying drawings. The directional terms mentioned in the following embodiments, such as "up", "down", "front", "rear", "left", "right", etc., only refer to the directions of the drawings. Accordingly, the directional terms used are intended to illustrate rather than limit the present invention.

In the detailed description of various embodiments, terms such as "first," "second," "third," and "fourth" may be used to describe different elements. These terms are only used to distinguish elements from each other, but in structure, these elements should not be limited by these terms. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element without departing from the scope of the present inventive concept. In addition, in the manufacturing method, except for a specific process flow, the formation sequence of these elements or components should not be limited by these terms. For example, the first element may be formed before the second element. Alternatively, the first element may be formed after the second element. Alternatively, the first element and the second element may be formed in the same process or step.

Also, the thicknesses of layers and regions in the drawings may be exaggerated for clarity. The same or similar reference numerals denote the same or similar elements, and the detailed description in the following paragraphs will not be repeated.

1A to 1H are schematic cross-sectional views of a method for fabricating an embedded device structure according to a first embodiment of the present invention. FIG. 1I is a schematic top view of an embedded device structure according to the first embodiment of the present invention. Specifically, FIG. 1H is an enlarged view of region R in FIG. 1G .

Referring to FIG. 1A , a circuit board 110 is provided. The circuit board 110 includes a core layer 111 , a first circuit layer 112 and a second circuit layer 113 . The first wiring layer 112 is on the first side 110 a of the wiring board 110 and on the core layer 111 , and the second wiring layer 113 is on the second side 110 b of the wiring board 110 and on the core layer 111 . The first side 110a is opposite to the second side 110b. The wiring board 110 has a through hole 110c. The through groove 110c penetrates at least the first circuit layer 112 and the core layer 111 . That is to say, the through groove 110c is formed by at least the sidewalls 111d of the core layer 111 and the sidewalls 112d of the first circuit layer 112 . And the two first circuit layers 112', 112" on both sides of the through slot 110c are structurally and electrically separated from each other.

In this embodiment, the through-groove 110c further penetrates through the second circuit layer 113 . That is to say, in this embodiment, the through-grooves 110c may be formed by the sidewalls 111d of the core layer 111 , the sidewalls 112d of the first wiring layer 112 and the sidewalls 113d of the second wiring layer 113 .

In this embodiment, the core layer 111 may include a polymer glass fiber composite substrate, a glass substrate, a ceramic substrate, an insulating silicon substrate, a polyimide (PI) glass fiber composite substrate, or other substrates with higher (compared to) The subsequent dielectric material layer 130 is a substrate formed of a material with a Young's modulus. In this way, in the subsequent manufacturing process, the circuit board 110 may be suitable for carrying the film layer formed thereon or the components disposed thereon.

In this embodiment, the core layer 111 of the circuit board 110 is made of a material with a higher Young's modulus. Therefore, in the manufacturing process of the embedded device structure 100 (marked in FIG. 1F , FIG. 1G or FIG. 1I ), the core layer 111 can basically be used as a support member in the manufacturing process or the final overall structure.

In one embodiment, the Young's modulus of the core layer 111 may be greater than or equal to 70 gigapascals (GPa).

In this embodiment, the core layer 111 can form a double sided wiring board with the first wiring layer 112 and the second wiring layer 113 on opposite sides of the core layer 111 . For example, the circuit board 110 may be a copper clad laminate (CCL) or other suitable printed circuit boards, but the invention is not limited thereto.

In one embodiment, the circuit board 110 may be referred to as a hard board PCB.

In some embodiments, the first circuit layer 112 and/or the second circuit layer 113 may be one or more conductive layers, but the invention is not limited thereto. In addition, or the first circuit layer 112 and/or the second circuit layer 113 are multi-layer conductive layers, the multi-layer conductive layers can be separated from each other by insulating layers, and can be separated from each other by conductive vias. The different conductive layers can be electrically connected to each other. The via hole is, for example, a buried via (Buried Via Hole; BVH), but the present invention is not limited thereto.

In this embodiment, the circuit board 110 may further include at least one via hole 114 so that the first circuit layer 112 on the first side 110a and the second circuit layer 113 on the second side 110b can be electrically connected to each other. In other embodiments, similar circuit boards may not have vias.

In this embodiment, the via hole 114 may be a hollow plating through hole (PTH), but the invention is not limited thereto. In some embodiments, the vias 114 may be solid conductive pillars. In some embodiments, the center of the via hole 114 may also be a plug-in resin material or a polymer glass-ceramic hybrid material, but is not limited thereto.

Referring to FIG. 1B , a carrier 10 is provided. In addition, the first electrical connection surface 112a of the first circuit layer 112 on the core layer 111 (ie, the exposed surface of the first circuit layer 112 farthest from the core layer 111 ) faces the carrier surface 10a of the carrier 10 . The circuit board 110 is joined with the carrier 10 . The carrier 10 may be a carrier tape, such as a blue tape, but the present invention is not limited thereto. In other embodiments, the carrier 10 may be a metal substrate, a silicon substrate, a glass substrate, a ceramic substrate, or other suitable carriers for supporting some components (eg, electronic components 120 to be placed on the carrier 10 later).

As shown in FIG. 1B , after the wiring board 110 is bonded to the carrier 10 , the first wiring layer 112 contacts the carrier 10 . In this embodiment, the first electrical connection surface 112a of the first circuit layer 112 may directly contact the carrier surface 10a of the carrier 10, but the present invention is not limited thereto. In other embodiments, if there is an adhesive layer (eg, a release film) between the circuit board 110 and the carrier 10 , the first electrical connection surface 112 a of the first circuit layer 112 can indirectly contact the carrier 10 . Generally speaking, the thickness of the carrier 10 or the circuit board 110 can be in a millimeter (millimeter; mm) level or a centimeter (centimeter; cm) level, and the adhesive layer can be in a micrometer (micrometer; μm) level. Therefore, compared with the thickness of the carrier 10 or the thickness of the circuit board 110 , the thickness of the adhesive layer can be very thin. Therefore, in the general visual sense, even if there is an adhesive layer between the circuit board 110 and the carrier 10 , it can be seen The carrier 10 is contacted for the first wiring layer 112 .

In this embodiment, the size of the carrier 10 only needs to be larger than the size of the through slot 110c. That is, the surface area of the carrier surface 10a of the carrier 10 only needs to be larger than the opening area of the through groove 110c. For example, the size of the carrier 10 may be smaller than or equal to the size of the circuit board 110 and larger than the size of the through slot 110c. In this way, after the circuit board 110 is combined with the carrier 10, the carrier surface 10a of the carrier 10 can completely cover the opening of the through-groove 110c.

Referring to FIG. 1C , the electronic component 120 is placed on the carrier 10 . Specifically, one side of the electronic component 120 may have a plurality of connection pads 121 , and the electronic component 120 is connected to the electronic component 120 in such a way that the second electrical connection surface 121a of each connection pad 121 of the electronic component 120 faces the carrier surface 10a of the carrier 10 . placed on the carrier 10 .

As shown in FIG. 1C , these connection pads 121 contact the carrier 10 after the electronic components 120 are placed on the carrier 10 . In this embodiment, the second electrical connection surface 121a of each connection pad 121 may directly contact the carrier surface 10a of the carrier 10, but the invention is not limited thereto. In other embodiments, if there is an adhesive layer (eg, a release film) between the electronic component 120 and the carrier 10 , the second electrical connection surface 121 a of each connection pad 121 can indirectly contact the carrier 10 . Taking a multilayer ceramic capacitor (MLCC) as the electronic component 120 as an example, the thickness of the 0402 capacitor is about 500 microns, and the thickness of the 0603 capacitor is about 800 microns. Therefore, compared with the thickness of the electronic component 120, the thickness of the adhesive layer can be very thin. Therefore, in the general visual sense, even if there is an adhesive layer between the electronic component 120 and the carrier 10, the electronic component 120 can be regarded as being in contact with the carrier 10. Vector 10.

In this embodiment, the circuit board 110 can be joined to the carrier 10 first, then the electronic components 120 are placed on the carrier 10, and the electronic components 120 are embedded in the through grooves 110c of the circuit board 110, but the present invention does not limited to this. In other embodiments, the electronic component 120 may be placed on the carrier 10 first, then the circuit board 110 is joined to the carrier 10 , and the through groove 110 c of the circuit board 110 is aligned with the electronic component 120 , so that the electronic component 120 Embedded in the through groove 110c of the circuit board 110 .

In this embodiment, the thickness of the circuit board 110 and the thickness of the electronic component 120 may be the same or different, which are not limited in the present invention. However, it should be noted that the cross-sectional area of the through grooves 110c of the circuit board 110 needs to be larger than the cross-sectional areas of the electronic components 120 on one side of the connection pads 121, so that the electronic components 120 can be suitably embedded in the through grooves 110c of the circuit board 110, and The connection pads 121 of the electronic components 120 are exposed to the outside of the through-grooves 110c.

Referring to FIG. 1D , after the circuit board 110 and the electronic components 120 are placed on the carrier 10 and the electronic components 120 are embedded in the through grooves 110c, a dielectric material layer 130 is formed on the carrier 10, and the dielectric material layer 130 It is filled at least in the through-grooves 110c (shown in FIG. 1C ). In this embodiment, for example, resin (eg: epoxy resin (epoxy) or other similar thermosetting cross-linked resin), silane (eg: hexamethyldisiloxane (HMDSN), tetraethoxy Silane (tetraethoxysilane; TEOS), bis(dimethylamino)dimethylsilane (BDMADMS) or other suitable dielectric materials are coated on the carrier 10 and cured to form a dielectric Material layer 130 . Generally speaking, the aforementioned dielectric materials have better adhesion and may not need to have a higher Young's modulus. For example, the Young's modulus of epoxy resin may be less than 5 GPa, and the Young's modulus of silicone resin (silicone) may be less than 1 GPa. That is to say, in the structure shown in FIG. 1D , the core layer 111 can basically be used as a support for the overall structure.

In this embodiment, the dielectric material layer 130 can be filled in the through groove 110 c and located between the electronic element 120 and the circuit board 110 , so that the electronic element 120 is fixed in the through groove 110 c of the circuit board 110 . In addition, since the dielectric material layer 130 is made of a material with a lower Young's modulus (compared to the core layer 111 ), a good buffer can be provided between the electronic device 120 and the circuit board 110 .

In one embodiment, the Young's modulus of the dielectric material layer 130 may be less than or equal to 10 Gigapascals (GPa).

In this embodiment, the dielectric material layer 130 filled in the through groove 110c may contact the carrier 10, but the invention is not limited thereto.

In this embodiment, the dielectric material layer 130 may include a covering portion 131 . The covering portion 131 is located outside the through-groove 110c and covers the second circuit layer 113 .

In this embodiment, at least one dielectric opening 131 a may be formed on the cover portion 131 by etching, grinding drilling, laser drilling or other suitable processes.

In this embodiment, the dielectric opening 131a may expose the via hole 114, but the present invention is not limited thereto. In other embodiments, the dielectric opening 131a may expose the third electrical connection surface 113a of the second wiring layer 113 (ie, the exposed surface of the second wiring layer 113 farthest from the core layer 111 ).

Referring to FIG. 1E , after the dielectric material layer 130 is formed, the carrier 10 (shown in FIG. 1D ) and the adhesive layer (if any) on the carrier 10 are removed to expose the first electrical properties of the first wiring layer 112 The connection surface 112a is connected to the second electrical connection surface 121a of each connection pad 121 . Since the circuit board 110 and the electronic components 120 are both placed on the carrier 10 and in contact with the carrier 10 , the first electrical connection surface 112 a of the first circuit layer 112 and the second electrical connection surface 121 a of each connection pad 121 are basically can be coplanar.

In this embodiment, if the dielectric material layer 130 filled in the through groove 110 c (shown in FIG. 1C ) contacts the carrier 10 , the dielectric surface 130 a of the dielectric material layer 130 and the first circuit layer 112 The electrical connection surface 112a and the second electrical connection surface 121a of each connection pad 121 may be substantially coplanar.

In addition, before or after the carrier 10 is removed, the structure of FIG. 1D can be turned upside down, so that after the carrier 10 is removed, the structure shown in FIG. 1E can be formed. That is to say, in the structure shown in FIG. 1E , the core layer 111 can basically be used as a support for the overall structure.

Referring to FIG. 1F , a connection circuit layer 140 is formed. The connection circuit layer 140 is a film layer covering and contacting the first electrical connection surface 112a and each of the second electrical connection surfaces 121a. The connection wiring layer 140 may be formed by a redistribution layer process (RDL process) or other suitable patterned wire processes.

One exemplary manner of forming the connection wiring layer 140 may be as follows. First, a seed layer (not shown) may be comprehensively formed on the first side 110a of the circuit board 110 by sputtering. The seed layer is conformal to the first electrical connection surface 112 a of the first circuit layer 112 , the second electrical connection surface 121 a of the connection pad 121 and the dielectric surface 130 a of the dielectric material layer 130 . Common seed layers include titanium and/or copper layers, however, the actual material of the seed layer depends on the conductive material to be formed on the seed layer subsequently. Next, a photoresist layer (not shown) is formed on the seed layer. The photoresist layer covers the seed layer of the portion 131 . The photoresist layer can be formed by a lithography process. The photoresist layer has a plurality of openings corresponding to the first electrical connection surface 112a, the second electrical connection surface 121a and the dielectric surface 130a to expose the first electrical connection surface 112a and the second electrical connection surface 121a and a portion of the seed layer above the dielectric surface 130a. After the photoresist layer is formed, a conductive material layer (not shown) is formed on the seed layer exposed by the opening. The conductive material layer may be formed on the seed layer by electroplating. The material of the conductive material layer may be similar to that of the seed layer, but the present invention is not limited thereto. After the conductive material layer is formed, the photoresist layer and part of the conductive material layer on the photoresist layer are removed. Next, using the unremoved conductive material layer as a mask, a part of the seed layer not covered by the conductive material layer is removed. In this way, the unremoved seed layer and the unremoved conductive material layer can constitute the connection line layer 140 .

Referring to FIG. 1G , after the connection circuit layer 140 is formed, a first dielectric layer 150 is formed on the first side 110 a of the circuit board 110 . The first dielectric layer 150 may be formed through a deposition process or a coating process. Then, patterning may be performed through a photolithography process and an etching process to form the first dielectric openings 150 a exposing a portion of the first wiring layer 112 and/or a portion of the connecting wiring layer 140 .

In this embodiment, the second dielectric layer 160 may be formed on the second side 110 b of the circuit board 110 . The second dielectric layer 160 may be formed through a deposition process or a coating process. Then, patterning may be performed through a lithography process and an etching process to form a second dielectric opening 160 a exposing a portion of the second wiring layer 113 and/or a portion of the via hole 114 .

In this embodiment, after the first dielectric layer 150 is formed, the third wiring layer 170 may be formed on the first dielectric layer 150 . The third circuit layer 170 may be formed in a manner similar to that of the connection circuit layer 140 , so it will not be repeated here. In addition, the conductive material used to form the third circuit layer 170 may be filled in the first dielectric openings 150a of the first dielectric layer 150, so that the third circuit layer 170 can be connected to the first circuit layer 112 and/or the circuit layer 140 electrical connections.

In this embodiment, after the second dielectric layer 160 is formed, a fourth wiring layer 180 may be formed on the second dielectric layer 160 . The fourth circuit layer 180 may be formed in a manner similar to that of the connection circuit layer 140 , so it will not be repeated here. In addition, the conductive material used to form the fourth circuit layer 180 can be filled in the second dielectric openings 160a of the second dielectric layer 160, so that the fourth circuit layer 180 can be connected to the second circuit layer 113 and/or the via holes 114 Electrical connection.

Referring to FIG. 1G to FIG. 1I , the fabrication of the embedded device structure 100 of the present embodiment can be substantially completed after the above process. The above-mentioned embedded element structure 100 includes a circuit board 110 , an electronic element 120 , a dielectric material layer 130 and a connection circuit layer 140 . The circuit board 110 has a through groove 110c. The circuit board 110 includes a core layer 111 , a first circuit layer 112 , a second circuit layer 113 and at least one via hole 114 . The first circuit layer 112 and the second circuit layer 113 are respectively located on opposite sides of the core layer 111 . The through-grooves 110c penetrate through the first wiring layer 112 , the core layer 111 and the second wiring layer 113 . The via hole 114 penetrates through the core layer 111 to electrically connect the first circuit layer 112 and the second circuit layer 113 . The electronic component 120 is disposed in the through groove 110c. The electronic component 120 includes a plurality of connection pads 121 . In the top view, the plurality of connection pads 121 are exposed outside the through-grooves 110c. In the cross-sectional view, the first electrical connection surface 112a of the first circuit layer 112 and the second electrical connection surface 121a of each connection pad 121 are substantially coplanar. The dielectric material layer 130 is filled at least in the through-grooves 110c. The Young's modulus of the core layer 111 is greater than that of the dielectric material layer 130 . The connection circuit layer 140 covers and contacts the first electrical connection surface 112a and each of the second electrical connection surfaces 121a. The connection pad 121 is electrically connected to the first circuit layer 112 through the connection circuit layer 140 .

In this embodiment, the dielectric material layer 130 is further filled between each connection pad 121 and the first circuit layer 112 . The dielectric material layer 130 has a dielectric surface 130a. The dielectric surface 130a is substantially coplanar with the first electrical connection surface 112a. The connection circuit layer 140 covers and contacts the first electrical connection surface 112a, the dielectric surface 130a and the second electrical connection surface 121a.

In the present embodiment, in the cross-sectional view, on a cross-section perpendicular to the first electrical connection surface 112a, the cross-sectional thickness of the connection line layer 140 on the first electrical connection surface 112a is 140h1, and the connection line layer 140 on the dielectric The cross-sectional thickness 140h3 on the surface 130a is substantially the same as the cross-sectional thickness 140h2 of the connecting circuit layer 140 on the second electrical connection surface 121a.

In this embodiment, in the top view, the cross-sectional area of the through groove 110c is larger than the surface area of the second electrical connection surface 121a.

In this embodiment, the embedded device structure 100 further includes a first dielectric layer 150 . The first dielectric layer 150 and the first wiring layer 112 are disposed on the same side of the core layer 111 . The first dielectric layer 150 covers at least a portion of the first wiring layer 112 and at least a portion of the connection wiring layer 140 . The first dielectric layer 150 has at least one first dielectric opening 150 a exposing the first wiring layer 112 or connecting the wiring layer 140 .

In this embodiment, the dielectric material layer 130 has a covering portion 131 located outside the through-groove 110c. The covering portion 131 covers the side of the core layer 111 where the second circuit layer 113 is located. The covering portion 131 covers at least part of the second wiring layer 113 .

In this embodiment, the covering portion 131 of the dielectric material layer 130 has at least one dielectric opening 131 a exposing the second circuit layer 113 or the via hole 114 .

In this embodiment, the embedded device structure 100 further includes a second dielectric layer 160 . The second dielectric layer 160 and the second wiring layer 113 are disposed on the same side of the core layer 111 . The second dielectric layer 160 covers at least part of the second wiring layer 113 and at least part of the via hole 114 . The second dielectric layer 160 has at least one second dielectric opening 160 a exposing the second wiring layer 113 or the via hole 114 .

Based on the above, the electronic components 120 and the circuit board 110 are directly electrically connected through the connecting circuit layer 140 , and the via holes between the electronic components 120 and the circuit board 110 may not need to be formed or omitted (not shown because there are none). Therefore, the manufacturing method of the embedded element structure 100 can be relatively simple, and the thickness can be relatively thin. In addition, by connecting the circuit layer 140, the length of the circuit between the electronic component 120 and the circuit board 110 can be reduced, the signal transmission time can be reduced, and the transmission rate between different electronic components can be improved. Also, the circuit board 110 is not completely removed during the manufacturing method of the embedded device structure 100 . Therefore, in the manufacturing method of the embedded device structure 100 , the circuit board 110 needs to have good support (eg, the core layer 111 having a higher Young's modulus).

FIG. 2 is a schematic cross-sectional view of an embedded element structure according to a second embodiment of the present invention.

The manufacturing method of the embedded element structure 200 of the present embodiment is similar to the manufacturing method of the embedded element structure 100 of the first embodiment. , and the description is omitted. In terms of structure, the embedded element structure 200 of the present embodiment is similar to the embedded element structure 100 of the first embodiment, and the main difference is that the constituent material of the first dielectric layer 250 includes a solder resist material, and/or The constituent material of the second dielectric layer 260 includes a solder resist material.

In this embodiment, the first dielectric layer 250 may be a dry film solder mask (DFSM) or a liquid photoimageable solder mask (LPSM). The first dielectric layer 250 has a plurality of first dielectric openings 250a. The first dielectric opening 250a may expose a corresponding portion of the first wiring layer 112 , a portion of the connecting wiring layer 140 and/or a portion of the via hole 114 .

In this embodiment, the second dielectric layer 260 may be a dry film solder resist or a liquid photosensitive solder resist. The second dielectric layer 260 has at least one second dielectric opening 260a. The second dielectric opening 260a may expose a corresponding portion of the via hole 114 . In other embodiments, the second dielectric opening 260a may expose a corresponding portion of the second circuit layer 113 .

3A to 3E are schematic cross-sectional views of a method for fabricating an embedded device structure according to a third embodiment of the present invention.

The manufacturing method of the embedded element structure 300 of the present embodiment is similar to the manufacturing method of the embedded element structure 100 of the first embodiment. , and the description is omitted.

Referring to FIG. 3A, a circuit board 310' is provided. In terms of structure, the circuit board 310' in FIG. 3A is similar in structure to the circuit board 110 in FIG. 1A, and the main difference is that the circuit board 310' does not have vias (not shown because there are none).

Next, the circuit board 310' and the electronic components 120 may be placed on the carrier 10 through steps similar to those shown in FIG. 1A to FIG. 1D, and the electronic components 120 may be embedded in the through grooves 110c. Then, a dielectric material layer 130 is formed on the carrier 10 , and the dielectric material layer 130 is filled at least in the through grooves 110 c (shown in FIG. 3A ) to form the structure shown in FIG. 3B .

Referring to FIG. 3C , before or after removing the carrier 10 , the structure of FIG. 3B can be turned upside down, so that after removing the carrier 10 , etching, grinding drilling, laser drilling or other suitable processes can be used to make the circuit At least one through hole 310e is formed on the plate 310'. The through hole 310e penetrates through the core layer 111 , the first wiring layer 112 and the second wiring layer 113 .

It should be noted that, in this embodiment, the sequence of the foregoing steps of removing the carrier 10 , the foregoing step of turning upside down, and the foregoing step of forming at least the through hole 310e is not limited. That is to say, the aforementioned three steps can be adaptively adjusted in sequence according to the requirements of the manufacturing method.

In this embodiment, since the electronic components 120 have been embedded in the through grooves 110c (shown in FIG. 3A ) of the circuit board 310 ′, and the dielectric material layer 130 filled in the through grooves 110c can remove the electrons in the through grooves 110c The components 120 are fixed and provide good buffering between the electronic components 120 and the circuit board 310'. Therefore, in the process of forming the through hole 310e, the electronic component 120 or the circuit board 310' may be affected by stress (for example, the vibration during grinding and drilling may cause stress between the electronic component 120 or the circuit board 310'), but The deflection of the electronic components 120 can still be reduced.

Referring to FIG. 3D , after the carrier 10 (shown in FIG. 3B ) is removed and at least a through hole 310 e (shown in FIG. 3C ) is formed, the connection wiring layer 140 is formed. In addition, a conductive material is filled in the through hole 310 e by a method similar to the formation method of the connection circuit layer 140 to form the via hole 114 . For example, the via hole 114 and the connection circuit layer 140 can be formed in the same process. The seed layer for forming the connection circuit layer 140 or the conductive material covering the seed layer can be filled into the through hole 310 e to form the via hole 314 . The via hole 314 can be electrically connected to the first circuit layer 112 and the second circuit layer 113 . In this way, the circuit board 310 having the core layer 111 , the first circuit layer 112 , the second circuit layer 113 and the via holes 314 can be formed.

Referring to FIG. 3E , after the connection circuit layer 140 and the via hole 314 are formed, a first dielectric layer 350 may be formed on the first side 310 a of the circuit board 310 . The first dielectric layer 350 has at least one first dielectric opening 350a. The first dielectric opening 350a exposes a portion of the first wiring layer 112 , a portion of the connecting wiring layer 140 and/or a portion of the via hole 314 .

In this embodiment, the second dielectric layer 360 may be formed on the second side 310 b of the circuit board 310 . The second dielectric layer 360 has at least one second dielectric opening 360a. The second dielectric opening 360a exposes part of the second wiring layer 113 and/or part of the via hole 314 .

In other embodiments, the first dielectric layer 350 and/or the second dielectric layer 360 may be dry film solder resist or liquid photosensitive solder resist.

After the above process, the fabrication of the embedded device structure 300 of this embodiment can be substantially completed. The embedded device structure 300 of the present embodiment is similar to the embedded device structure 100 of the first embodiment, the difference lies in that the manufacturing method of the embedded device structure 300 of the present embodiment is to first embed the electronic device 120 into the non-conductive device. The circuit board 310 having the through holes 314 is formed in the through-hole 110c of the circuit board 310 ′.

FIG. 4A , FIG. 4B and FIG. 4D are schematic bottom views of a manufacturing method of an embedded device structure according to a fourth embodiment of the present invention. 4C, FIG. 4E to FIG. 4H are schematic cross-sectional views of a method for manufacturing an embedded element structure according to a fourth embodiment of the present invention.

The manufacturing method of the embedded element structure 400 of the present embodiment is similar to the manufacturing method of the embedded element structure 100 of the first embodiment. , and the description is omitted.

Referring to FIG. 4A, a circuit board 410' is provided. In terms of structure, the circuit board 410' in FIG. 4A is similar in structure to the circuit board 110 in FIG. 1A, and the main difference is that the circuit board 410' does not have a through slot (not shown because there is none).

Referring to FIG. 4B and FIG. 4C , a circuit board 410 having through-grooves 410c is formed. For example, a portion of the first wiring layer 112 and a portion of the first wiring layer 112 in the circuit board 410 ′ (shown in FIG. 4A ) may be removed by etching, grinding drilling, laser drilling, or other suitable processes. The core layer 111 is formed to form the circuit board 410 with the through-grooves 410c.

In this embodiment, the through-groove 410c and the at least one via hole 114 may be structurally connected to each other, but the present invention is not limited thereto. In other embodiments, the through-groove 410c and the via hole 114 may be separated from each other.

Next, the circuit board 410 having the through grooves 410 c is placed on the carrier 10 . Generally speaking, in order to reduce damage or unevenness of the carrier surface 10 a of the carrier 10 , the circuit board 410 with the through grooves 410 c may be formed first, and then the circuit board 410 with the through grooves 410 c is placed on the carrier 10 .

Referring to FIG. 4D and FIG. 4E , the electronic component 120 is placed on the carrier 10 .

In the present embodiment, the circuit board 410 may be placed on the carrier 10 first, then the electronic components 120 may be placed on the carrier 10, and the electronic components 120 may be embedded in the through grooves 410c of the circuit board 410, but the present invention does not limited to this. In other embodiments, the electronic component 120 may be placed on the carrier 10 first, and then the circuit board 410 may be placed on the carrier 10, and the through groove 410c of the circuit board 410 may be aligned with the electronic component 120, so that the electronic component 120 Embedded in the through groove 410c of the circuit board 410 .

In this embodiment, the through-slot 410c is located between the plurality of via holes 114', 114" and can be structurally connected with these via holes 114', 114", and the electronic component 120 is located in these via holes 114 ′, 114 ″. Therefore, the conductive holes 114 ′, 114 ″ corresponding to the plurality of connection pads 121 of the electronic component 120 need to be electrically separated from each other by the through grooves 410 c .

Referring to FIG. 4F , after the circuit board 410 and the electronic components 120 are placed on the carrier 10 and the electronic components 120 are embedded in the through grooves 410c, a dielectric material layer 130 is formed on the carrier 10, and the dielectric material layer 130 It is filled at least in the through-grooves 410c (shown in FIG. 4D ). The dielectric material layer 130 may include a cover part 131 . The covering portion 131 is located outside the through-groove 410c and covers the second circuit layer 113 . The cover portion 131 has at least one dielectric opening 131a. The dielectric opening 131a may expose the third electrical connection surface 113a of the second wiring layer 113 .

Referring to FIG. 4G , the structure of FIG. 4F may be turned upside down before or after the carrier 10 is removed. And, after the carrier 10 is removed, the connection wiring layer 140 is formed. The connection circuit layer 140 covers and contacts the first electrical connection surface 112a and each of the second electrical connection surfaces 121a. The connection circuit layer 140 is electrically connected to the second circuit layer 113 through the corresponding via holes 114 .

Referring to FIG. 4H , after the connection circuit layer 140 is formed, a first dielectric layer 450 is formed on the first side 410 a of the circuit board 410 . The first dielectric layer 450 has at least one first dielectric opening 450a. The first dielectric opening 450a exposes a portion of the connection line layer 140 .

In this embodiment, the second dielectric layer 460 may be formed on the second side 410 b of the circuit board 410 . The second dielectric layer 460 has at least one second dielectric opening 460a. The second dielectric opening 460a exposes a portion of the second wiring layer 113 .

In other embodiments, the first dielectric layer 450 and/or the second dielectric layer 460 may be dry film solder resist or liquid photosensitive solder resist.

After the above process, the fabrication of the embedded device structure 400 of this embodiment can be substantially completed. The embedded component structure 400 of the present embodiment is similar to the embedded component structure 100 of the first embodiment, except that the through-groove 410c of the circuit board 410 and the at least one via hole 114 can be structurally connected.

5A to 5F are schematic cross-sectional views of a method for manufacturing an embedded device structure according to a fifth embodiment of the present invention. 5G is a schematic top view of an embedded device structure according to the fifth embodiment of the present invention.

The manufacturing method of the embedded element structure 500 of the present embodiment is similar to the manufacturing method of the embedded element structure 300 of the third embodiment. , and the description is omitted.

Referring to FIG. 5A , the circuit board 310 ′ and the electronic components 520 can be placed on the carrier 10 through steps similar to FIGS. 1A to 1C , and the electronic components 520 can be embedded in the through grooves 110c.

In this embodiment, one side of the electronic component 520 may have a plurality of first connection pads 521 , and one side of the electronic component 520 may have the second connection pads 522 . The electronic component 520 is placed on the carrier 10 in such a manner that the second electrical connection surfaces 521a of the first connection pads 521 of the electronic component 520 face the carrier surface 10a of the carrier 10 . In this embodiment, the second electrical connection surfaces 521a of each of the first connection pads 521 may directly contact the carrier surface 10a of the carrier 10, but the invention is not limited thereto. In other embodiments, if there is an adhesive layer (not shown) between the electronic component 520 and the carrier 10 , the second electrical connection surface 521 a of each of the first connection pads 521 can indirectly contact the carrier 10 . Taking a vertical cavity surface emitting laser (VCSEL) die, a light emitting diode (LED) die or other active components as the electronic component 520 as an example, the thickness thereof is about micrometers to millimeters. Therefore, compared with the thickness of the electronic component 520, the thickness of the adhesive layer can be very thin. Therefore, even if there is an adhesive layer between the electronic component 520 and the carrier 10, the electronic component 520 can be regarded as being in contact with the naked eye. Vector 10.

In this embodiment, the circuit board 310 ′ can be placed on the carrier 10 first, then the electronic components 520 can be placed on the carrier 10 , and the electronic components 520 can be embedded in the through grooves 110 c of the circuit board 310 ′. The invention is not limited to this. In other embodiments, the electronic component 520 may be placed on the carrier 10 first, and then the circuit board 310' may be placed on the carrier 10, and the through groove 110c of the circuit board 310' may be aligned with the electronic component 520, so that the electronic The element 520 is embedded in the through groove 110c of the circuit board 310'.

In this embodiment, the thickness of the circuit board 310' and the thickness of the electronic component 520 may be the same or different, which is not limited in the present invention. However, it should be noted that the cross-sectional area of the through grooves 110c of the circuit board 310' needs to be larger than the cross-sectional area of the electronic components 520 on one side of the first connection pads 521, so that the electronic components 520 can be suitably embedded in the through grooves of the circuit board 310'. 110c, and the first connection pad 521 of the electronic component 520 is exposed outside the through-groove 110c.

Referring to FIG. 5B , after the circuit board 310 ′ and the electronic components 520 are placed on the carrier 10 and the electronic components 520 are embedded in the through grooves 110 c (shown in FIG. 5A ), a first dielectric material layer 530 is formed on On the carrier 10 , the first dielectric material layer 530 is filled at least in the through-grooves 110c. The first dielectric material layer 530 may include a cover part 531 . The covering portion 531 is located outside the through-groove 110c and covers the second circuit layer 113 . The cover portion 531 has a dielectric opening 531a thereon. The dielectric opening 531 a can expose the third electrical connection surface 113 a of the second circuit layer 113 and the second connection pad 522 of the electronic element 520 .

The material formation method of the first dielectric material layer 530 may be the same as or similar to the material formation method of the dielectric material layer 130 in the foregoing embodiments, and thus will not be repeated here. That is, the Young's modulus of the core layer 111 is greater than the Young's modulus of the first dielectric material layer 530 .

Referring to FIG. 5C , after the first dielectric material layer 530 is formed, the carrier 10 is removed to expose the second electrical connection between the first electrical connection surface 112 a of the first circuit layer 112 and each of the first connection pads 521 face 521a. Since both the circuit board 310 ′ and the electronic components 520 are placed on the carrier 10 and are in contact with the carrier 10 , the first electrical connection surface 112 a of the first circuit layer 112 is electrically connected to the second electrical connection of each of the first connection pads 521 Faces 521a may be substantially coplanar.

In this embodiment, if the first dielectric material layer 530 filled in the through groove 110 c contacts the carrier 10 , the dielectric surface 530 a of the first dielectric material layer 530 and the first electrical connection of the first circuit layer 112 are electrically connected The surface 112a and the second electrical connection surface 521a of each connection pad 121 may be substantially coplanar.

In addition, before or after the carrier 10 is removed, the structure shown in FIG. 5B can be turned upside down, so that after the carrier 10 is removed, the structure shown in FIG. 5C can be formed.

5C, after removing the carrier 10, a second dielectric material layer 535 is formed on the first side 310'a of the circuit board 310'. The second dielectric material layer 535 has dielectric openings 535a. The dielectric openings 535 a may expose the dielectric surface 530 a of the first dielectric material layer 530 , the first electrical connection surfaces 112 a of the first circuit layer 112 and the second electrical connection surfaces 521 a of each of the first connection pads 521 .

The material formation method of the second dielectric material layer 535 may be the same as or similar to the material formation method of the first dielectric material layer 530 , and thus will not be repeated here.

Referring to FIG. 5D , after the second dielectric material layer 535 is formed, at least through holes may be formed on the circuit board 310 ′ (shown in FIG. 5C ) by etching, grinding drilling, laser drilling or other suitable processes 310e. The through hole 310e penetrates through the core layer 111 , the first wiring layer 112 and the second wiring layer 113 .

In this embodiment, since the electronic element 520 has been embedded in the through groove 110c of the circuit board 310', and the first dielectric material layer 530 filled in the through groove 110c can fix the electronic element 520 in the through groove 110c, and Provides good buffering between the electronic components 520 and the circuit board 310'. Therefore, in the process of forming the through hole 310e, the electronic component 520 or the circuit board 310' may be affected by stress (for example, the vibration during grinding and drilling may cause stress between the electronic component 520 or the circuit board 310'), but The deflection of the electronic components 520 can still be reduced.

Referring to FIG. 5E , after the through holes 310e (shown in FIG. 5D ) are formed, the connection circuit layer 140 is formed. In addition, a conductive material is filled in the through hole 310 e by a method similar to the formation method of the connection circuit layer 140 to form the via hole 114 . In this way, the circuit board 310 having the core layer 111 , the first circuit layer 112 , the second circuit layer 113 and the via holes 314 can be formed.

In this embodiment, the circuit layer 590 may be formed on the second circuit layer 113 and/or the second connection pad 522 . The formation of the circuit layer 590 may be similar to that of the connection circuit layer 140 , so it will not be repeated here. In addition, the conductive material used to form the circuit layer 590 can be filled in the dielectric openings 531 a of the second dielectric material layer 535 , so that the circuit layer 590 can be electrically connected to the second circuit layer 113 and/or the via hole 314 .

Referring to FIG. 5F and FIG. 5G , after the connection circuit layer 140 and the via hole 314 are formed, a first dielectric layer 350 is formed on the first side 310 a of the circuit board 310 . The first dielectric layer 350 has at least one first dielectric opening 350a. The first dielectric opening 350a exposes a portion of the connection line layer 140 and/or a portion of the via hole 314 .

In this embodiment, the second dielectric layer 360 may be formed on the second side 310 b of the circuit board 310 . The second dielectric layer 360 has at least one second dielectric opening 360a. The second dielectric opening 360a exposes part of the second wiring layer 113 and/or part of the via hole 314 .

In terms of structure, the embedded device structure 500 of this embodiment is similar to the embedded device structure 300 of the third embodiment, and the main difference is that the connection pads 521 and 522 of the electronic device 520 have different arrangements.

6 is a schematic cross-sectional view of a buried element structure according to a sixth embodiment of the present invention.

The embedded element structure 600 of the present embodiment is similar to the embedded element structure 500 of the fifth embodiment, and the similar components are denoted by the same reference numerals, and have similar functions, materials or formation methods, and the description is omitted. In terms of structure, the embedded device structure 600 of this embodiment is similar to the embedded device structure 500 of the fifth embodiment, and the main difference is that the first dielectric layer 650 has a first dielectric layer exposing the electronic device 520 . Opening 650a.

7 is a schematic cross-sectional view of a buried element structure according to a seventh embodiment of the present invention.

The embedded element structure of this embodiment is similar to the embedded element structure 600 of the sixth embodiment, and similar components are denoted by the same reference numerals, and have similar functions, materials, or formation methods, and descriptions are omitted. In terms of structure, the embedded component structure 700 of this embodiment is similar to the embedded component structure 600 of the sixth embodiment, and the main difference is that in the embedded component structure 700 of this embodiment, the circuit board 410 has The through-groove 410c (shown in FIG. 4B ) and the at least one via hole 114 may structurally communicate with each other. For example, the circuit board 410 in which the through-grooves 410c and the vias 114 can be structurally communicated with each other can be formed by the manufacturing method as shown in FIG. 4A to FIG. 4C .

8 is a schematic cross-sectional view of an embedded device structure according to an eighth embodiment of the present invention.

The embedded element structure of this embodiment is similar to the embedded element structure 700 of the seventh embodiment, and similar components are denoted by the same reference numerals and have similar functions, materials, or formation methods, and descriptions thereof are omitted. In terms of structure, the embedded element structure 800 of this embodiment is similar to the embedded element structure 700 of the seventh embodiment, and the main difference is that the electronic element 820 in the embedded element structure 800 is, for example, a chip, has a chip package or other electronic components with active components.

Taking a chip as an example, the connection pads 821 of the electronic component 820 can be die pads, and the connection pads 821 are located on the active surface 820a. The first electrical connection surface 112a and the second electrical connection surface 821a of the connection pad 821 may be substantially coplanar. The connection circuit layer 140 covers and contacts the first electrical connection surface 112a and each of the second electrical connection surfaces 821a. The connection pads 821 are electrically connected to the first circuit layer 112 through the connection circuit layer 140 .

In this embodiment, the heat dissipation element 20 may be disposed on the back surface 820b of the electronic element 820 (ie, the surface opposite to the active surface 820a). The heat dissipation element 20 may include a heat dissipation plate, a heat dissipation fin, etc., but the present invention is not limited thereto. The heat generated by the electronic element 820 can be transferred to the outside through the heat dissipation element 20, so that the embedded element structure 800 can have a better heat dissipation effect, but the invention is not limited thereto.

In this embodiment, the heat dissipation element 20 may be in direct contact with the back surface 820b of the electronic element 820, but the present invention is not limited thereto. In a not-shown embodiment, there may be thermally conductive glue between the heat dissipation element 20 and the back surface 820b of the electronic element 820 .

In a not-shown embodiment, a heat dissipation element similar to the heat dissipation element 20 may also be disposed on the first dielectric layer 650 .

9 is a schematic cross-sectional view of an embedded element structure according to a ninth embodiment of the present invention.

The embedded element structure of this embodiment is similar to the embedded element structure 700 of the seventh embodiment, and similar components are denoted by the same reference numerals and have similar functions, materials, or formation methods, and descriptions thereof are omitted. In terms of structure, the embedded device structure 900 of this embodiment is similar to the embedded device structure 700 of the seventh embodiment, and the main difference is that the electronic device 920 in the embedded device structure 900 is, for example, an optical sensor chip (For example: a chip including a charge-coupled device (CCD)), an acoustic sensing chip, or other sensing chips suitable for receiving external signals. The electronic component 920 may have a sensor area 920a. The sensing area 920a is adapted to receive external signals.

In this embodiment, the sensing region 920a may have a cover layer 30 on it. The protective layer 30 can reduce damage that may be caused to the sensing region 920a. In one embodiment, the protective layer 30 is, for example, a hard coating layer, but the invention is not limited thereto. In one embodiment, the protective layer 30 may be a glass plate, a quartz plate, a rigid plastic plate or other similar rigid plate-like bodies.

To sum up, in the embedded component structure of the present invention, the electronic component and the circuit board are directly electrically connected by connecting the circuit layer, and the via hole between the electronic component and the circuit board may not need to be formed or omitted. Therefore, the manufacturing method of the embedded element structure can be relatively simple, and the thickness can be relatively thin. In addition, by connecting the circuit layers, the length of the circuit between the electronic component and the circuit board can be reduced, the signal transmission time can be reduced, and the transmission rate between different electronic components can be improved.

Although the present invention has been disclosed above with examples, it is not intended to limit the present invention. Any person skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be subject to what is defined in the claims.

Claims (19)

1. An embedded component structure, comprising:

a circuit board having a through slot, and the circuit board comprising:

a core layer;

a first circuit layer;

the second circuit layer and the first circuit layer are respectively positioned at two opposite sides of the core layer, and the through groove at least penetrates through the first circuit layer and the core layer; and

at least two via holes penetrating through the core layer to electrically connect the first circuit layer and the second circuit layer, wherein the through groove is communicated with the at least two via holes;

the electronic element is arranged in the through groove and comprises a plurality of connecting pads exposed outside the through groove, and a first electrical connection surface of the first circuit layer is coplanar with a second electrical connection surface of each connecting pad;

a dielectric material layer at least filled in the through groove, wherein the young modulus of the core layer is greater than or equal to 70 giga pascal, and the young modulus of the dielectric material layer is less than or equal to 10 giga pascal, so that the circuit board is suitable for bearing the film layer formed on the circuit board and the elements configured on the circuit board in the manufacturing process of the embedded element structure;

the connecting circuit layer covers and contacts the first electrical connection surface and each second electrical connection surface, and the connecting pads are electrically connected to the first circuit layer through the connecting circuit layer; and

a heat dissipation element disposed on a back surface of the electronic element and thermally coupled to the electronic element, wherein during a manufacturing process of the embedded element structure:

before forming the connection line layer, the electronic element is electrically separated from the at least two through holes; and is provided with

After the connection line layer is formed, the electronic component is electrically connected only through the connection line layer and the at least two via holes.

2. The embedded device structure of claim 1, wherein the dielectric material layer further fills between each of the plurality of connecting pads and the first circuit layer, and has a dielectric surface coplanar with the first electrical connection surface, and the connecting circuit layer covers and contacts the first electrical connection surface, the dielectric surface, and the second electrical connection surface.

3. The embedded component structure of claim 2, wherein a cross-sectional thickness of the connection line layer on the first electrical connection surface, the dielectric surface, and the second electrical connection surface is uniform in a cross-section perpendicular to the first electrical connection surface.

4. The embedded device structure as claimed in claim 1, wherein a cross-sectional area of the through-groove is larger than a surface area of the electronic device on the second electrical connection surface.

5. The embedded component structure of claim 1, further comprising:

the first dielectric layer and the first circuit layer are arranged on the same side of the core layer, at least part of the first circuit layer and at least part of the connecting circuit layer are covered, and the first dielectric layer is provided with at least one opening which exposes the first circuit layer or the connecting circuit layer.

6. The embedded component structure of claim 5, wherein a constituent material of the first dielectric layer comprises a solder resist material.

7. The embedded component structure as claimed in claim 1, wherein the dielectric material layer has a covering portion located outside the through-groove, covering a side of the core layer where the second circuit layer is located, and covering at least a portion of the second circuit layer.

8. The embedded component structure of claim 7, wherein the cover portion of the dielectric material layer has at least one dielectric opening exposing the second circuit layer or the via.

9. The embedded component structure of claim 7, further comprising:

the second dielectric layer covers the covering part of the dielectric material layer, and the second dielectric layer is provided with at least one opening exposing the second circuit layer or the through hole.

10. The embedded component structure of claim 9, wherein a constituent material of the second dielectric layer comprises a solder resist material.

11. A method of fabricating an embedded component structure, comprising:

providing a carrier;

placing a circuit board on the carrier, the circuit board having a through slot, and the circuit board comprising:

a core layer;

a first circuit layer, wherein the first circuit layer contacts the carrier;

the second circuit layer and the first circuit layer are respectively positioned at two opposite sides of the core layer, and the through groove at least penetrates through the first circuit layer and the core layer; and

at least two via holes penetrating through the core layer to electrically connect the first circuit layer and the second circuit layer, wherein the through groove and the at least two via holes are communicated with each other;

placing an electronic component on the carrier, the electronic component having a plurality of connection pads, wherein the plurality of connection pads contact the carrier;

after the circuit board and the electronic element are placed on the carrier and the electronic element is embedded in the through groove, forming a dielectric material layer on the carrier, wherein the dielectric material layer is at least filled in the through groove, the Young modulus of the core layer is greater than or equal to 70 giga pascal, and the Young modulus of the dielectric material layer is less than or equal to 10 giga pascal, so that the circuit board is suitable for bearing the film layer formed on the circuit board and the element configured on the circuit board in the manufacturing process of the embedded element structure;

removing the carrier to expose the first circuit layer and the plurality of connecting pads, wherein a first electrical connection surface of the first circuit layer is coplanar with a second electrical connection surface of each of the plurality of connecting pads;

after removing the carrier, forming a connection circuit layer, and the connection circuit layer covers and contacts the first electrical connection surface and each of the second electrical connection surfaces, wherein:

before forming the connection line layer, the electronic element is electrically separated from the at least two through holes; and is

After forming the connection line layer, the electronic component is electrically connected only through the connection line layer and the at least two via holes; and

the heat dissipation element is disposed on the back surface of the electronic element and thermally coupled to the electronic element.

12. The method of manufacturing an embedded component structure as claimed in claim 11, further comprising:

after forming the connection line layer, a first dielectric layer is formed, the first dielectric layer covering at least a portion of the first line layer and at least a portion of the connection line layer.

13. The method of claim 12, wherein a constituent material of the first dielectric layer comprises a solder mask material.

14. The method of manufacturing an embedded component structure of claim 11, further comprising:

after the dielectric material layer is formed, at least one through hole penetrating through the core layer, the first circuit layer and the second circuit layer is formed on the circuit board; and

and filling a conductive material into the at least one through hole to form at least two through holes penetrating through the core layer so as to electrically connect the first circuit layer and the second circuit layer.

15. The method for manufacturing an embedded component structure as claimed in claim 11, wherein the dielectric material layer has a covering portion located outside the through-groove, covers a side of the core layer where the second circuit layer is located, and covers at least a portion of the second circuit layer.

16. The method of manufacturing an embedded component structure as claimed in claim 15, further comprising:

at least one dielectric opening is formed on the covering portion of the dielectric material layer, and the second circuit layer is exposed out of the at least one dielectric opening.

17. The method of manufacturing an embedded component structure of claim 15, further comprising:

forming a second dielectric layer overlying the covering portion of the dielectric material layer.

18. The method of manufacturing a buried component structure of claim 17, further comprising:

at least one second opening is formed on the second dielectric layer, and the second circuit layer is exposed by the at least one second opening.

19. The method of manufacturing the embedded component structure as claimed in claim 17, wherein a constituent material of the second dielectric layer comprises a solder mask material.

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