TWI707615B - Embedded component structure and manufacturing method thereof - Google Patents

Abstract

An embedded component structure includes a circuit board, an electronic component, a dielectric layer and a connection circuit layer. The circuit board has through hole and includes a core layer, a first circuit layer, a second circuit layer, and a conductive via. The first circuit layer and the second circuit layer are located on opposite sides of the core layer. The through hole penetrate the first circuit layer and the core layer. The conductive via electrically connect the first circuit layer and the second circuit layer. The electronic component is disposed within the through hole and includes a plurality of connection pads. The first electrical connection surface of the first circuit layer is coplanar with the second electrical connection surfaces of the connection pads. The dielectric layer is filled in the through hole. The Young's modulus of the core layer is greater than the Young's modulus of the dielectric layer. The connection circuit layer contacts the first electrical connection surface and the second electrical connection surfaces. A manufacturing method of an embedded component structure is also provided.

Description

Embedded element structure and manufacturing method thereof

The present invention relates to an electronic component and a manufacturing method thereof, and more particularly to an embedded component structure and a manufacturing method thereof.

In a general embedded device structure, at least a conductive through via is used to connect the electronic device with a printed circuit board (PCB). However, the above-mentioned connection method will make the electrical transmission path between the electronic component and the printed circuit board long, which may cause the power and/or signal of the electronic product to be attenuated to a high degree, and it is also easy to generate noise (Noise), thus reducing the quality of electronic products. In addition, the manufacturing method of such an embedded element structure is more complicated and thick.

The present invention provides an embedded element structure and a manufacturing method thereof, the thickness of which can be thinner and the manufacturing method can be simpler.

The embedded component structure of the present invention includes a circuit board, an electronic component, a dielectric material layer and a connecting circuit layer. The circuit board has slots. The circuit board includes a core layer, a first circuit layer, a second circuit layer and at least one via. The first circuit layer and the second circuit layer are respectively located on opposite sides of the core layer. The through slot penetrates at least the first circuit layer and the core layer. The via hole penetrates the core layer to electrically connect the first circuit layer and the second circuit layer. The electronic component is arranged in the through slot. The electronic component includes a plurality of connection pads exposed outside the through groove. The first electrical connection surface of the first circuit layer and the second electrical connection surface of each connection pad are coplanar. The dielectric material layer is filled at least in the through groove. The Young's modulus of the core layer is greater than the Young's modulus of the dielectric material layer. The connection circuit layer covers and contacts the first electrical connection surface and each second electrical connection surface. The connection pad is electrically connected to the first circuit layer through the connection circuit layer.

In an embodiment of the present invention, the above-mentioned dielectric material layer is further filled between each connection pad and the first circuit layer. The dielectric material layer has a dielectric surface coplanar with the first electrical connection surface. The connection circuit layer covers and contacts the first electrical connection surface, the dielectric surface and the second electrical connection surface.

In an embodiment of the present invention, on a cross-section perpendicular to the first electrical connection surface, the cross-sectional thickness of the above-mentioned connection circuit layer on the first electrical connection surface, the dielectric surface, and the second electrical connection surface is uniform .

In an embodiment of the present invention, the cross-sectional area of the above-mentioned through slot is larger than the surface area of the electronic component on the second electrical connection surface.

In an embodiment of the present invention, the above-mentioned embedded device structure further includes a first dielectric layer. The first dielectric layer and the first circuit layer are arranged on the same side of the core layer. The first dielectric layer covers at least part of the first circuit layer and at least part of the connection circuit layer, and the first dielectric layer has at least one opening exposing the first circuit layer or the connection circuit layer.

In an embodiment of the present invention, the constituent material of the aforementioned first dielectric layer includes a solder mask material.

In an embodiment of the present invention, the above-mentioned dielectric material layer has a covering portion located outside the through groove. The covering part covers the side of the core layer where the second circuit layer is located, and the covering part covers at least part of the second circuit layer.

In an embodiment of the present invention, the covering portion of the above-mentioned dielectric material layer has at least one dielectric opening exposing the second circuit layer or the via hole.

In an embodiment of the present invention, the above-mentioned embedded device structure further includes a second dielectric layer. The second dielectric layer covers the covering portion of the dielectric material layer, and the second dielectric layer has at least one opening exposing the second circuit layer or the via hole.

In an embodiment of the present invention, the constituent material of the aforementioned second dielectric layer includes a solder mask material.

In an embodiment of the present invention, the above-mentioned through slot is communicated with at least one via hole.

The manufacturing method of the embedded element structure of the present invention includes the following steps. Provide a carrier. Place the circuit board on the carrier. The circuit board has slots. The circuit board includes a core layer, a first circuit layer and a second circuit layer. The first circuit layer contacts the carrier. The first circuit layer and the second circuit layer are respectively located on opposite sides of the core layer. The through slot penetrates at least the first circuit layer and the core layer. Place the electronic components on the carrier. The electronic component has multiple connection pads. These connection pads contact the carrier. After the circuit board and the electronic components are placed on the carrier and the electronic components are embedded in the through grooves, a dielectric material layer is formed on the carrier. The dielectric material layer is filled at least in the through groove. The Young's modulus of the core layer is greater than the Young's modulus of the dielectric material layer. The carrier is removed to expose the first circuit layer and the connection pads. The first electrical connection surface of the first circuit layer and the second electrical connection surface of each connection pad are coplanar. After removing the carrier, a connecting circuit layer is formed. The connection circuit layer covers and contacts the first electrical connection surface and each second electrical connection surface.

In an embodiment of the present invention, the aforementioned circuit board further includes at least one via hole. The via hole penetrates the core layer to electrically connect the first circuit layer and the second circuit layer.

In an embodiment of the present invention, the above-mentioned through slot and the through hole are in communication with each other.

In an embodiment of the present invention, the manufacturing method of the above-mentioned embedded element structure further includes the following steps. After forming the connecting circuit layer, a first dielectric layer is formed. The first dielectric layer covers at least part of the first circuit layer and at least part of the connection circuit layer.

In an embodiment of the present invention, the constituent material of the aforementioned first dielectric layer includes a solder mask material.

In an embodiment of the present invention, the manufacturing method of the above-mentioned embedded element structure further includes the following steps. After the dielectric material layer is formed, at least one through hole penetrating the core layer, the first circuit layer and the second circuit layer is formed on the circuit board. At least one through hole is filled with conductive material to form at least one through hole through the core layer. The via hole electrically connects the first circuit layer and the second circuit layer.

In an embodiment of the present invention, the above-mentioned dielectric material layer has a covering portion located outside the through groove. The covering part covers the side of the core layer where the second circuit layer is located, and covers at least part of the second circuit layer.

In an embodiment of the present invention, the manufacturing method of the above-mentioned embedded element structure further includes the following steps. At least one dielectric opening is formed on the covering part of the dielectric material layer. The dielectric opening exposes the second circuit layer.

In an embodiment of the present invention, the manufacturing method of the above-mentioned embedded element structure further includes the following steps. A second dielectric layer is formed. The second dielectric layer covers the covering portion of the dielectric material layer.

In an embodiment of the present invention, the manufacturing method of the above-mentioned embedded element structure further includes the following steps. At least one second opening is formed on the second dielectric layer. The second opening exposes the second circuit layer.

In an embodiment of the present invention, the constituent material of the aforementioned second dielectric layer includes a solder mask material.

Based on the above, in the embedded component structure of the present invention, the electronic component and the circuit board are directly electrically connected through the connection circuit layer, and the via hole between the electronic component and the circuit board can be eliminated or eliminated. Therefore, the manufacturing method of the embedded element structure can be simpler and the thickness can be thinner. In addition, by connecting the circuit layer, the length of the circuit between the electronic component and the circuit board can be reduced, the signal transmission time (ie, the delay time) can be reduced, and the transmission rate between different electronic components can be increased.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

The foregoing and other technical content, features and effects of the present invention will be clearly presented in the detailed description of each embodiment with reference to the drawings. The directional terms mentioned in the following embodiments, for example: "up", "down", "front", "rear", "left", "right", etc., are just directions for referring to the attached drawings. Therefore, the directional terms used are used to illustrate, but not to limit the present invention.

In the detailed description of each embodiment, terms such as "first", "second", "third", and "fourth" can be used to describe different elements. These terms are only used to distinguish elements from each other, but in the structure, these elements should not be limited by these terms. For example, the first element may be referred to as the second element, and, similarly, the second element may be referred to as the first element without departing from the protection scope of the inventive concept. In addition, in the manufacturing method, in addition to a specific manufacturing process, the formation of these elements or components should not be limited by these terms. For example, the first element may be formed before the second element. Alternatively, the first element may be formed after the second element. Or, the first element and the second element can be formed in the same manufacturing process or step.

In addition, the thickness of layers and regions in the drawings will be exaggerated for clarity. The same or similar reference numbers indicate the same or similar elements, and the following paragraphs will not repeat them one by one.

1A to 1H are schematic cross-sectional views of a method for manufacturing an embedded device structure according to a first embodiment of the present invention. FIG. 1I is a schematic top view of an embedded device structure according to the first embodiment of the present invention. Specifically, FIG. 1H is an enlarged view of the area R in FIG. 1G.

Please refer to FIG. 1A, a circuit board 110 is provided. The circuit board 110 includes a core layer 111, a first circuit layer 112 and a second circuit layer 113. The first circuit layer 112 is on the first side 110 a of the circuit board 110 and is located on the core layer 111, and the second circuit layer 113 is on the second side 110 b of the circuit board 110 and is located on the core layer 111. The first side 110a is opposite to the second side 110b. The wiring board 110 has a through hole 110c. The through groove 110 c penetrates at least the first circuit layer 112 and the core layer 111. In other words, the through groove 110c is formed at least by the sidewall 111d of the core layer 111 and the sidewall 112d of the first circuit layer 112. In addition, the two first circuit layers 112', 112" on both sides of the through groove 110c are separated from each other structurally and electrically.

In this embodiment, the through groove 110 c further penetrates the second circuit layer 113. That is to say, in this embodiment, the through groove 110c may be formed by the sidewall 111d of the core layer 111, the sidewall 112d of the first circuit layer 112, and the sidewall 113d of the second circuit layer 113.

In this embodiment, the core layer 111 may include a polymer glass fiber composite material substrate, a glass substrate, a ceramic substrate, an insulating silicon substrate, a polyimide (PI) glass fiber composite substrate, or other materials with higher (compared to Subsequent dielectric material layer 130) A substrate made of Young's modulus material. In this way, in the subsequent manufacturing process, the circuit board 110 can be suitable for carrying the film layer formed on it or the components disposed thereon.

In this embodiment, the core layer 111 of the circuit board 110 is made of a material with a higher Young's modulus. Therefore, during the manufacturing process of the embedded device structure 100 (marked in FIG. 1F, FIG. 1G or FIG. 1I), the core layer 111 can basically be used as a support during the manufacturing process or the final overall structure.

In an embodiment, the Young's modulus of the core layer 111 may be greater than or equal to 70 billion Pascal (Gigapascal, GPa).

In this embodiment, the core layer 111 may form a double sided wiring board with the first wiring layer 112 and the second wiring layer 113 on opposite sides thereof. For example, the circuit board 110 may be a copper clad laminate (CCL) or other suitable printed circuit boards, but the present invention is not limited thereto.

In an embodiment, the circuit board 110 may be referred to as a hard board (hard board PCB).

In some embodiments, the first circuit layer 112 and/or the second circuit layer 113 may be one or more conductive layers, and the present invention is not limited thereto. In addition, or the first circuit layer 112 and/or the second circuit layer 113 are multiple conductive layers, the conductive layers of the multiple layers can be separated from each other by an insulating layer, and can be made by conductive vias. Different conductive layers can be electrically connected to each other. The via hole is, for example, a Buried Via Hole (BVH), but the present invention is not limited thereto.

In this embodiment, the circuit board 110 may further include at least one via 114, so that the first circuit layer 112 on the first side 110a and the second circuit layer 113 on the second side 110b can be electrically connected to each other. In other embodiments, similar circuit boards may not have via holes.

In this embodiment, the via hole 114 may be a hollow plating through hole (PTH), but the present invention is not limited thereto. In some embodiments, the via 114 may be a solid conductive pillar. In some embodiments, the middle of the via 114 may also be plugged resin material or polymer glass ceramic mixed material, but it is not limited thereto.

Referring to FIG. 1B, a carrier 10 is provided. In addition, the first electrical connection surface 112a of the first circuit layer 112 on the core layer 111 (that is, the exposed surface of the first circuit layer 112 furthest away from the core layer 111) faces the carrier surface 10a of the carrier 10. The circuit board 110 is joined to the carrier 10. The carrier 10 may be a carrier tape, such as a blue tape, but the invention is not limited thereto. In other embodiments, the carrier 10 can be a metal substrate, a silicon substrate, a glass substrate, a ceramic substrate, or other suitable carrier plates that can be used to support some components (such as the electronic components 120 that will be placed on the carrier 10 later).

As shown in FIG. 1B, after the circuit board 110 and the carrier 10 are joined, the first circuit layer 112 contacts the carrier 10. In this embodiment, the first electrical connection surface 112a of the first circuit layer 112 may directly contact the carrier surface 10a of the carrier 10, but the present invention is not limited to this. In other embodiments, if there is an adhesive layer (such as a release film) between the circuit board 110 and the carrier 10, the first electrical connection surface 112 a of the first circuit layer 112 can indirectly contact the carrier 10. Generally speaking, the thickness of the carrier 10 or the circuit board 110 may be on the millimeter (mm) level or on the centimeter (cm) level, and the adhesive layer may be on the micrometer (μm) level. Therefore, compared to the thickness of the carrier 10 or the thickness of the circuit board 110, the thickness of the adhesive layer can be very thin. Therefore, in the general naked eye, even if there is an adhesive layer between the circuit board 110 and the carrier 10, it can be seen The first circuit layer 112 contacts the carrier 10.

In this embodiment, the size of the carrier 10 only needs to be larger than the size of the through slot 110c. In other words, the surface area of the carrier surface 10a of the carrier 10 only needs to be larger than the opening area of the through groove 110c. For example, the size of the carrier 10 may be smaller than or equal to the size of the circuit board 110, and larger than the size of the slot 110c. In this way, after the circuit board 110 is joined to the carrier 10, the carrier surface 10a of the carrier 10 can completely cover the opening of the through groove 110c.

1C, the electronic component 120 is placed on the carrier 10. Specifically, one side of the electronic component 120 may have a plurality of connection pads 121, and the second electrical connection surface 121a of each connection pad 121 of the electronic component 120 faces the carrier surface 10a of the carrier 10. Place on the carrier 10.

As shown in FIG. 1C, after the electronic component 120 is placed on the carrier 10, these connection pads 121 contact the carrier 10. In this embodiment, the second electrical connection surface 121a of each connection pad 121 may directly contact the carrier surface 10a of the carrier 10, but the present invention is not limited to this. In other embodiments, if there is an adhesive layer (such as a release film) between the electronic component 120 and the carrier 10, the second electrical connection surface 121 a of each connection pad 121 can indirectly contact the carrier 10. Taking a Multilayer Ceramic Capacitor (MLCC) as the electronic component 120 as an example, the thickness of the 0402 capacitor is about 500 microns, and the thickness of the 0603 capacitor is about 800 microns. Therefore, compared to the thickness of the electronic component 120, the thickness of the adhesive layer can be very thin. Therefore, in the general naked eye, even if there is an adhesive layer between the electronic component 120 and the carrier 10, it can be regarded as the electronic component 120 in contact. Carrier 10.

In this embodiment, the circuit board 110 and the carrier 10 may be first joined, and then the electronic component 120 is placed on the carrier 10, and the electronic component 120 is embedded in the slot 110c of the circuit board 110, but the present invention does not Limited to this. In other embodiments, the electronic component 120 may be placed on the carrier 10 first, and then the circuit board 110 is joined to the carrier 10, and the slot 110c of the circuit board 110 is aligned with the electronic component 120, so that the electronic component 120 It is embedded in the through slot 110c of the circuit board 110.

In this embodiment, the thickness of the circuit board 110 and the thickness of the electronic component 120 may be the same or different, which is not limited in the present invention. However, it should be noted that the cross-sectional area of the through groove 110c of the circuit board 110 needs to be larger than the cross-sectional area of the electronic component 120 on the side of the connection pads 121, so that the electronic component 120 is suitable for being embedded in the through groove 110c of the circuit board 110, and The connection pad 121 of the electronic component 120 is exposed outside the through groove 110c.

1D, after the circuit board 110 and the electronic component 120 are placed on the carrier 10, and the electronic component 120 is embedded in the slot 110c, a dielectric material layer 130 is formed on the carrier 10, and the dielectric material layer 130 It is filled at least in the through groove 110c (shown in FIG. 1C). In this embodiment, for example, resin (such as epoxy or other similar thermosetting crosslinking resins), silane (such as hexamethyldisiloxane (HMDSN), tetraethoxy Tetraethoxysilane (TEOS), bis(dimethylamino)dimethylsilane (BDMADMS) or other suitable dielectric materials are coated on the carrier 10 and cured to form a dielectric Material layer 130. Generally speaking, the aforementioned dielectric materials have better adhesion and may not need to have a higher Young's modulus. For example, the Young's modulus of epoxy can be less than 5 GPa, and the Young's modulus of silicone can be less than 1 GPa. In other words, in the structure shown in FIG. 1D, the core layer 111 can basically be used as a support for the overall structure.

In this embodiment, the dielectric material layer 130 may be filled in the through groove 110 c and located between the electronic component 120 and the circuit board 110 so that the electronic component 120 is fixed in the through groove 110 c of the circuit board 110. In addition, since the dielectric material layer 130 is made of a material with a lower Young's modulus (compared to the core layer 111), it can provide a good buffer between the electronic component 120 and the circuit board 110.

In an embodiment, the Young's modulus of the dielectric material layer 130 may be less than or equal to 10 Gigapascal (Gigapascal, GPa).

In this embodiment, the dielectric material layer 130 filled in the through groove 110c may contact the carrier 10, but the present invention is not limited thereto.

In this embodiment, the dielectric material layer 130 may include a covering part 131. The covering portion 131 is located outside the through groove 110 c and covers the second circuit layer 113.

In this embodiment, at least one dielectric opening 131a can be formed on the covering portion 131 by etching, grinding drilling, laser drilling or other suitable processes.

In this embodiment, the dielectric opening 131a may expose the via hole 114, but the invention is not limited thereto. In other embodiments, the dielectric opening 131a may expose the third electrical connection surface 113a of the second circuit layer 113 (ie, the exposed surface of the second circuit layer 113 furthest away from the core layer 111).

1E, after the dielectric material layer 130 is formed, the carrier 10 (shown in FIG. 1D) and the adhesive layer (if any) on the carrier 10 are removed to expose the first electrical properties of the first circuit layer 112 The connection surface 112a is connected to the second electrical connection surface 121a of each connection pad 121. Since the circuit board 110 and the electronic component 120 are both placed on the carrier 10 and in contact with the carrier 10, the first electrical connection surface 112a of the first circuit layer 112 and the second electrical connection surface 121a of each connection pad 121 are basically The upper can be coplanar.

In this embodiment, if the dielectric material layer 130 filled in the through groove 110c (shown in FIG. 1C) contacts the carrier 10, the dielectric surface 130a of the dielectric material layer 130 and the first circuit layer 112 are The electrical connection surface 112a and the second electrical connection surface 121a of each connection pad 121 may be substantially coplanar.

In addition, before or after the carrier 10 is removed, the structure of FIG. 1D can be upside down, so that after the carrier 10 is removed, the structure shown in FIG. 1E can be formed. In other words, in the structure shown in FIG. 1E, the core layer 111 can basically be used as a support for the overall structure.

Referring to FIG. 1F, a connecting circuit layer 140 is formed. The connection circuit layer 140 is a film layer covering and contacting the first electrical connection surface 112a and each of the second electrical connection surfaces 121a. The connecting circuit layer 140 may be formed by a redistribution layer process (RDL process) or other suitable patterned wire processes.

One exemplary formation method of the connection wiring layer 140 may be as follows. First, a seed layer (not shown) may be formed on the first side 110a of the circuit board 110 by sputtering. The seed layer is conformal to the first electrical connection surface 112 a of the first circuit layer 112, the second electrical connection surface 121 a of the connection pad 121 and the dielectric surface 130 a of the dielectric material layer 130. The common seed layer includes a titanium layer and/or a copper layer. However, the actual material of the seed layer depends on the conductive material that will be subsequently formed on the seed layer. Next, a photoresist layer (not shown) is formed on the seed layer. The photoresist layer covers the seed layer of the portion 131. The photoresist layer can be formed by a photolithography process. The photoresist layer has a plurality of openings corresponding to the first electrical connection surface 112a, the second electrical connection surface 121a and the dielectric surface 130a to expose the first electrical connection surface 112a and the second electrical connection surface 121a And part of the seed layer above the dielectric surface 130a. After forming the photoresist layer, a conductive material layer (not shown) is formed on the seed layer exposed by the opening. The conductive material layer may be formed on the seed layer by electroplating. The material of the conductive material layer can be similar to the material of the seed layer, but the invention is not limited to this. After the conductive material layer is formed, the photoresist layer and part of the conductive material layer on the photoresist layer are removed. Next, using the unremoved conductive material layer as a mask, remove part of the seed layer that is not covered by the conductive material layer. In this way, the unremoved seed layer and the unremoved conductive material layer can constitute the connecting circuit layer 140.

1G, after forming the connecting circuit layer 140, a first dielectric layer 150 is formed on the first side 110a of the circuit board 110. The first dielectric layer 150 may be formed by a deposition process or a coating process. Then, it can be patterned by a photolithography process and an etching process to form a first dielectric opening 150a exposing a part of the first circuit layer 112 and/or a part of the connecting circuit layer 140.

In this embodiment, the second dielectric layer 160 may be formed on the second side 110b of the circuit board 110. The second dielectric layer 160 may be formed by a deposition process or a coating process. Then, it can be patterned by a photolithography process and an etching process to form a second dielectric opening 160a exposing a part of the second circuit layer 113 and/or a part of the via hole 114.

In this embodiment, after the first dielectric layer 150 is formed, a third circuit layer 170 may be formed on the first dielectric layer 150. The formation method of the third circuit layer 170 can be similar to the connection circuit layer 140, so it will not be repeated here. In addition, the conductive material used to form the third circuit layer 170 can be filled in the first dielectric opening 150a of the first dielectric layer 150, so that the third circuit layer 170 can be connected to the first circuit layer 112 and/or the connection circuit layer. 140 electrical connection.

In this embodiment, after the second dielectric layer 160 is formed, a fourth circuit layer 180 may be formed on the second dielectric layer 160. The formation method of the fourth circuit layer 180 can be similar to that of the connection circuit layer 140, so it will not be repeated here. In addition, the conductive material used to form the fourth circuit layer 180 can be filled in the second dielectric opening 160a of the second dielectric layer 160, so that the fourth circuit layer 180 can interact with the second circuit layer 113 and/or the via 114 Electrical connection.

1G to FIG. 1I, after the above-mentioned manufacturing process, the fabrication of the embedded device structure 100 of this embodiment can be substantially completed. The above-mentioned embedded device structure 100 includes a circuit board 110, an electronic device 120, a dielectric material layer 130 and a connecting circuit layer 140. The circuit board 110 has a through groove 110c. The circuit board 110 includes a core layer 111, a first circuit layer 112, a second circuit layer 113 and at least one via 114. The first circuit layer 112 and the second circuit layer 113 are respectively located on opposite sides of the core layer 111. The through groove 110 c penetrates the first circuit layer 112, the core layer 111 and the second circuit layer 113. The via hole 114 penetrates the core layer 111 to electrically connect the first circuit layer 112 and the second circuit layer 113. The electronic component 120 is disposed in the through slot 110c. The electronic component 120 includes a plurality of connection pads 121. In the upper view, the plurality of connection pads 121 are exposed outside the through groove 110c. In the cross-sectional view, the first electrical connection surface 112 a of the first circuit layer 112 and the second electrical connection surface 121 a of each connection pad 121 are substantially coplanar. The dielectric material layer 130 is filled at least in the through groove 110c. The Young's modulus of the core layer 111 is greater than the Young's modulus of the dielectric material layer 130. The connection circuit layer 140 covers and contacts the first electrical connection surface 112a and each of the second electrical connection surfaces 121a. The connection pad 121 is electrically connected to the first circuit layer 112 through the connection circuit layer 140.

In this embodiment, the dielectric material layer 130 is further filled between each connection pad 121 and the first circuit layer 112. The dielectric material layer 130 has a dielectric surface 130a. The dielectric surface 130a and the first electrical connection surface 112a are substantially coplanar. The connection circuit layer 140 covers and contacts the first electrical connection surface 112a, the dielectric surface 130a, and the second electrical connection surface 121a.

In this embodiment, in the cross-sectional view, on a cross-section perpendicular to the first electrical connection surface 112a, the cross-sectional thickness of the connection circuit layer 140 on the first electrical connection surface 112a is 140h1, and the connection circuit layer 140 is in the dielectric The cross-sectional thickness 140h3 on the surface 130a is substantially the same as the cross-sectional thickness 140h2 of the connecting circuit layer 140 on the second electrical connection surface 121a.

In this embodiment, in the top view, the cross-sectional area of the through groove 110c is larger than the surface area of the second electrical connection surface 121a.

In this embodiment, the embedded device structure 100 further includes a first dielectric layer 150. The first dielectric layer 150 and the first circuit layer 112 are disposed on the same side of the core layer 111. The first dielectric layer 150 covers at least part of the first circuit layer 112 and at least part of the connection circuit layer 140. The first dielectric layer 150 has at least one first dielectric opening 150 a exposing the first circuit layer 112 or the connecting circuit layer 140.

In this embodiment, the dielectric material layer 130 has a covering portion 131 located outside the through groove 110c. The covering portion 131 covers the side of the core layer 111 where the second circuit layer 113 is located. The covering portion 131 covers at least a part of the second circuit layer 113.

In this embodiment, the covering portion 131 of the dielectric material layer 130 has at least one dielectric opening 131 a exposing the second circuit layer 113 or the via hole 114.

In this embodiment, the buried device structure 100 further includes a second dielectric layer 160. The second dielectric layer 160 and the second circuit layer 113 are disposed on the same side of the core layer 111. The second dielectric layer 160 covers at least part of the second circuit layer 113 and at least part of the via 114. The second dielectric layer 160 has at least one second dielectric opening 160 a exposing the second circuit layer 113 or the via 114.

Based on the above, the electronic component 120 and the circuit board 110 are directly electrically connected by the connection circuit layer 140, and the via hole between the electronic component 120 and the circuit board 110 may not be formed or omitted (it is not shown because it is not). Therefore, the manufacturing method of the embedded device structure 100 can be simpler, and the thickness can be thinner. In addition, by connecting the circuit layer 140, the length of the circuit between the electronic component 120 and the circuit board 110 can be reduced, the signal transmission time can be reduced, and the transmission rate between different electronic components can be increased. Moreover, the circuit board 110 is not completely removed during the manufacturing method of the embedded device structure 100. Therefore, in the manufacturing method of the embedded device structure 100, the circuit board 110 needs to have good support (for example, a core layer 111 with a relatively high Young's modulus).

2 is a schematic cross-sectional view of an embedded device structure according to a second embodiment of the present invention.

The manufacturing method of the embedded element structure 200 of this embodiment is similar to the manufacturing method of the embedded element structure 100 of the first embodiment, and similar components are denoted by the same reference numerals and have similar functions, materials, or formation methods. , And omit the description. In terms of structure, the buried device structure 200 of this embodiment is similar to the buried device structure 100 of the first embodiment. The main difference is that the constituent material of the first dielectric layer 250 includes a solder mask material, and/or The constituent material of the second dielectric layer 260 includes a solder mask material.

In this embodiment, the first dielectric layer 250 may be a dry film solder mask (DFSM) or a liquid photoimageable solder mask (LPSM). The first dielectric layer 250 has a plurality of first dielectric openings 250a. The first dielectric opening 250a may expose a corresponding part of the first circuit layer 112, a part of the connection circuit layer 140 and/or a part of the via 114.

In this embodiment, the second dielectric layer 260 may be a dry film solder resist or a liquid photosensitive solder resist. The second dielectric layer 260 has at least one second dielectric opening 260a. The second dielectric opening 260a may expose a corresponding portion of the via hole 114. In other embodiments, the second dielectric opening 260a may expose a corresponding portion of the second circuit layer 113.

3A to 3E are schematic cross-sectional views of a method for manufacturing an embedded device structure according to a third embodiment of the present invention.

The manufacturing method of the embedded element structure 300 of this embodiment is similar to the manufacturing method of the embedded element structure 100 of the first embodiment, and similar components are denoted by the same reference numerals, and have similar functions, materials, or formation methods. , And omit the description.

Please refer to FIG. 3A, a circuit board 310' is provided. In terms of structure, the circuit board 310' in FIG. 3A is similar in structure to the circuit board 110 in FIG. 1A, with the main difference being that the circuit board 310' does not have via holes (they are not shown).

Then, the circuit board 310' and the electronic component 120 can be placed on the carrier 10, and the electronic component 120 can be embedded in the through slot 110c by following the steps similar to those in FIG. 1A to FIG. 1D. Then, a dielectric material layer 130 is formed on the carrier 10, and the dielectric material layer 130 is at least filled in the through groove 110c (shown in FIG. 3A) to form the structure shown in FIG. 3B.

Referring to FIG. 3C, before or after removing the carrier 10, the structure of FIG. 3B can be turned upside down, so that after the carrier 10 is removed, etching, grinding, drilling, laser drilling or other suitable processes can be used to At least one through hole 310e is formed on the circuit board 310'. The through hole 310e penetrates the core layer 111, the first circuit layer 112, and the second circuit layer 113.

It is worth noting that, in this embodiment, the sequence of the step of removing the carrier 10, the step of turning up and down, and the step of forming at least one through hole 310e is not limited in this embodiment. That is to say, the aforementioned three steps can be adjusted in sequence according to the requirements of the manufacturing method.

In this embodiment, since the electronic component 120 has been embedded in the slot 110c (shown in FIG. 3A) of the circuit board 310', and the dielectric material layer 130 filled in the slot 110c can remove the electrons in the slot 110c The component 120 is fixed and provides a good buffer between the electronic component 120 and the circuit board 310'. Therefore, in the process of forming the through hole 310e, the electronic component 120 or the circuit board 310' may be affected by stress (for example, vibration during grinding and drilling causes stress between the electronic component 120 or the circuit board 310'), but The deviation of the electronic component 120 can still be reduced.

Referring to FIG. 3D, after the carrier 10 (shown in FIG. 3B) is removed and at least one through hole 310e (shown in FIG. 3C) is formed, the connecting circuit layer 140 is formed. In addition, a conductive material is filled in the through hole 310e by a method similar to the formation method of the connecting circuit layer 140 to form the via hole 114. For example, the via 114 and the connecting circuit layer 140 can be formed by the same process. The seed layer used to form the connecting circuit layer 140 or the conductive material covering the seed layer can be filled into the through hole 310 e to form the via hole 314. The via 314 may be electrically connected to the first circuit layer 112 and the second circuit layer 113. In this way, the circuit board 310 with the core layer 111, the first circuit layer 112, the second circuit layer 113 and the via 314 can be formed.

Referring to FIG. 3E, after the connecting circuit layer 140 and the via 314 are formed, a first dielectric layer 350 may be formed on the first side 310a of the circuit board 310. The first dielectric layer 350 has at least one first dielectric opening 350a. The first dielectric opening 350 a exposes a part of the first circuit layer 112, a part of the connection circuit layer 140 and/or a part of the via hole 314.

In this embodiment, the second dielectric layer 360 may be formed on the second side 310b of the circuit board 310. The second dielectric layer 360 has at least one second dielectric opening 360a. The second dielectric opening 360a exposes part of the second circuit layer 113 and/or part of the via 314.

In other embodiments, the first dielectric layer 350 and/or the second dielectric layer 360 may be dry film solder resist or liquid photosensitive solder resist.

After the above-mentioned manufacturing process, the fabrication of the embedded device structure 300 of this embodiment can be substantially completed. The embedded element structure 300 of this embodiment is similar to the embedded element structure 100 of the first embodiment, the difference is: the embedded element structure 300 of this embodiment is made by first embedding the electronic element 120 without conduction. In the through slot 110c of the circuit board 310' with a hole, a circuit board 310 with a via 314 is formed later.

4A, 4B, and 4D are schematic bottom views of a method for manufacturing an embedded device structure according to a fourth embodiment of the present invention. 4C, 4E to 4H are schematic cross-sectional views of a method for manufacturing an embedded device structure according to a fourth embodiment of the present invention.

The manufacturing method of the embedded element structure 400 of this embodiment is similar to the manufacturing method of the embedded element structure 100 of the first embodiment, and similar components are denoted by the same reference numerals and have similar functions, materials or formation methods. , And omit the description.

Please refer to FIG. 4A, a circuit board 410' is provided. In terms of structure, the circuit board 410' in FIG. 4A is similar in structure to the circuit board 110 in FIG. 1A. The main difference is that the circuit board 410' does not have a slot (there is no drawing because it is not).

Referring to FIG. 4B and FIG. 4C, a circuit board 410 having a through groove 410c is formed. For example, a part of the first circuit layer 112 and a part of the first circuit in the circuit board 410' (shown in FIG. 4A) can be removed by etching, grinding, drilling, laser drilling, or other suitable processes. The layer 112 is the core layer 111 to form a circuit board 410 with a through groove 410c.

In this embodiment, the through slot 410c and the at least one through hole 114 may be structurally connected to each other, but the present invention is not limited thereto. In other embodiments, the through groove 410c and the via hole 114 may be separated from each other.

Next, the circuit board 410 with the through groove 410c is placed on the carrier 10. Generally speaking, in order to reduce the damage or unevenness of the carrier surface 10a of the carrier 10, the circuit board 410 with the slot 410c can be formed first, and then the circuit board 410 with the slot 410c is placed on the carrier 10.

4D and 4E, the electronic component 120 is placed on the carrier 10.

In this embodiment, the circuit board 410 may be placed on the carrier 10 first, then the electronic component 120 is placed on the carrier 10, and the electronic component 120 is embedded in the through slot 410c of the circuit board 410, but the present invention does not Limited to this. In other embodiments, the electronic component 120 may be placed on the carrier 10 first, and then the circuit board 410 is placed on the carrier 10, and the slot 410c of the circuit board 410 is aligned with the electronic component 120, so that the electronic component 120 Embedded in the through slot 410c of the circuit board 410.

In this embodiment, the through slot 410c is located between the plurality of via holes 114', 114" and can be structurally connected to the via holes 114', 114", and the electronic component 120 is located in the via holes 114', 114". 114". Therefore, the through holes 114' and 114" of the plurality of connection pads 121 corresponding to the electronic component 120 need to be electrically separated from each other by the through slot 410c.

4F, after the circuit board 410 and the electronic component 120 are placed on the carrier 10, and the electronic component 120 is embedded in the slot 410c, a dielectric material layer 130 is formed on the carrier 10, and the dielectric material layer 130 At least fill in the through groove 410c (shown in FIG. 4D). The dielectric material layer 130 may include a covering part 131. The covering portion 131 is located outside the through groove 410 c and covers the second circuit layer 113. The covering portion 131 has at least one dielectric opening 131a. The dielectric opening 131 a may expose the third electrical connection surface 113 a of the second circuit layer 113.

Referring to FIG. 4G, before or after removing the carrier 10, the structure of FIG. 4F can be turned upside down. In addition, after the carrier 10 is removed, the connection wiring layer 140 is formed. The connection circuit layer 140 covers and contacts the first electrical connection surface 112a and each of the second electrical connection surfaces 121a. The connection circuit layer 140 is electrically connected to the second circuit layer 113 through the corresponding via 114.

Referring to FIG. 4H, after the connecting circuit layer 140 is formed, a first dielectric layer 450 is formed on the first side 410a of the circuit board 410. The first dielectric layer 450 has at least one first dielectric opening 450a. The first dielectric opening 450a exposes a part of the connection line layer 140.

In this embodiment, the second dielectric layer 460 may be formed on the second side 410b of the circuit board 410. The second dielectric layer 460 has at least one second dielectric opening 460a. The second dielectric opening 460a exposes part of the second circuit layer 113.

In other embodiments, the first dielectric layer 450 and/or the second dielectric layer 460 may be dry film solder resist or liquid photosensitive solder resist.

After the above-mentioned manufacturing process, the fabrication of the embedded device structure 400 of this embodiment can be substantially completed. The embedded component structure 400 of this embodiment is similar to the embedded component structure 100 of the first embodiment, except that the through slot 410c of the circuit board 410 and the at least one via 114 can be connected structurally.

5A to 5F are schematic cross-sectional views of a manufacturing method of an embedded device structure according to a fifth embodiment of the present invention. FIG. 5G is a schematic top view of an embedded device structure according to the fifth embodiment of the present invention.

The manufacturing method of the embedded element structure 500 of this embodiment is similar to the manufacturing method of the embedded element structure 300 of the third embodiment, and similar components are denoted by the same reference numerals, and have similar functions, materials, or formation methods. , And omit the description.

Referring to FIG. 5A, the circuit board 310' and the electronic component 520 can be placed on the carrier 10, and the electronic component 520 can be embedded in the slot 110c by following the steps similar to those in FIG. 1A to FIG. 1C.

In this embodiment, one side of the electronic component 520 may have a plurality of first connection pads 521, and one side of the electronic component 520 may have a second connection pad 522. The electronic component 520 is placed on the carrier 10 in such a manner that the second electrical connection surface 521 a of each first connection pad 521 of the electronic component 520 faces the carrier surface 10 a of the carrier 10. In this embodiment, the second electrical connection surface 521a of each first connection pad 521 may directly contact the carrier surface 10a of the carrier 10, but the present invention is not limited to this. In other embodiments, if there is an adhesive layer (not shown) between the electronic component 520 and the carrier 10, the second electrical connection surface 521 a of each first connection pad 521 can indirectly contact the carrier 10. Taking a vertical cavity surface emitting laser (VCSEL) die, a light emitting diode (LED) die or other active components as an example of the electronic component 520, the thickness of the electronic component 520 is about micrometers to millimeters. Therefore, compared to the thickness of the electronic component 520, the thickness of the adhesive layer can be very thin. Therefore, in the general naked eye, even if there is an adhesive layer between the electronic component 520 and the carrier 10, it can be regarded as the electronic component 520 contacting. Carrier 10.

In this embodiment, the circuit board 310' can be placed on the carrier 10 first, and then the electronic component 520 is placed on the carrier 10, and the electronic component 520 is embedded in the slot 110c of the circuit board 310'. The invention is not limited to this. In other embodiments, the electronic component 520 may be placed on the carrier 10 first, and then the circuit board 310' is placed on the carrier 10, and the through slot 110c of the circuit board 310' is aligned with the electronic component 520, so that the electronic The component 520 is embedded in the through slot 110c of the circuit board 310'.

In this embodiment, the thickness of the circuit board 310' and the thickness of the electronic component 520 may be the same or different, which is not limited in the present invention. However, it should be noted that the cross-sectional area of the slot 110c of the circuit board 310' needs to be larger than the cross-sectional area of the electronic component 520 on the side of the first connection pads 521, so that the electronic component 520 is suitable for being embedded in the slot of the circuit board 310' Inside 110c, the first connection pad 521 of the electronic component 520 is exposed outside the through groove 110c.

5B, after the circuit board 310' and the electronic component 520 are placed on the carrier 10, and the electronic component 520 is embedded in the slot 110c (shown in FIG. 5A), a first dielectric material layer 530 is formed On the carrier 10, the first dielectric material layer 530 is at least filled in the through groove 110c. The first dielectric material layer 530 may include a covering part 531. The covering portion 531 is located outside the through groove 110 c and covers the second circuit layer 113. The covering portion 531 has a dielectric opening 531a. The dielectric opening 531 a may expose the third electrical connection surface 113 a of the second circuit layer 113 and the second connection pad 522 of the electronic component 520.

The material formation method of the first dielectric material layer 530 can be the same or similar to the material formation method of the dielectric material layer 130 in the foregoing embodiment, so it will not be repeated here. That is, the Young's modulus of the core layer 111 is greater than the Young's modulus of the first dielectric material layer 530.

5C, after the first dielectric material layer 530 is formed, the carrier 10 is removed to expose the first electrical connection surface 112a of the first circuit layer 112 and the second electrical connection of each first connection pad 521面521a. Since the circuit board 310' and the electronic component 520 are both placed on the carrier 10 and in contact with the carrier 10, the first electrical connection surface 112a of the first circuit layer 112 is electrically connected to the second electrical connection of each first connection pad 521 The surface 521a may be substantially coplanar.

In this embodiment, if the first dielectric material layer 530 filled in the through groove 110c contacts the carrier 10, the dielectric surface 530a of the first dielectric material layer 530 and the first electrical connection of the first circuit layer 112 The surface 112a and the second electrical connection surface 521a of each connection pad 121 may be substantially coplanar.

In addition, before or after the carrier 10 is removed, the structure of FIG. 5B can be turned upside down, so that after the carrier 10 is removed, the structure shown in FIG. 5C can be formed.

Please continue to refer to FIG. 5C. After the carrier 10 is removed, a second dielectric material layer 535 is formed on the first side 310'a of the circuit board 310'. The second dielectric material layer 535 has a dielectric opening 535a. The dielectric opening 535a may expose the dielectric surface 530a of the first dielectric material layer 530, the first electrical connection surface 112a of the first circuit layer 112, and the second electrical connection surface 521a of each first connection pad 521.

The material forming method of the second dielectric material layer 535 can be the same or similar to the material forming method of the first dielectric material layer 530, so it will not be repeated here.

Referring to FIG. 5D, after the second dielectric material layer 535 is formed, etching, grinding, drilling, laser drilling, or other suitable processes may be used to form at least the circuit board 310' (shown in FIG. 5C). One through hole 310e. The through hole 310e penetrates the core layer 111, the first circuit layer 112, and the second circuit layer 113.

In this embodiment, since the electronic component 520 has been embedded in the through groove 110c of the circuit board 310', and the first dielectric material layer 530 filled in the through groove 110c can fix the electronic component 520 in the through groove 110c, and Provide a good buffer between the electronic component 520 and the circuit board 310'. Therefore, in the process of forming the through hole 310e, the electronic component 520 or the circuit board 310' may be affected by stress (for example, vibration during grinding and drilling causes stress between the electronic component 520 or the circuit board 310'), but The deviation of the electronic component 520 can still be reduced.

Referring to FIG. 5E, after forming the through hole 310e (shown in FIG. 5D), the connecting circuit layer 140 is formed. In addition, a conductive material is filled in the through hole 310e by a method similar to the formation method of the connecting circuit layer 140 to form the via hole 114. In this way, the circuit board 310 with the core layer 111, the first circuit layer 112, the second circuit layer 113 and the via 314 can be formed.

In this embodiment, the circuit layer 590 may be formed on the second circuit layer 113 and/or the second connection pad 522. The formation of the circuit layer 590 can be similar to the connection circuit layer 140, so it will not be described in detail here. In addition, the conductive material used to form the circuit layer 590 can be filled in the dielectric opening 531 a of the second dielectric material layer 535 so that the circuit layer 590 can be electrically connected to the second circuit layer 113 and/or the via 314.

5F and 5G, after forming the connecting circuit layer 140 and the via 314, a first dielectric layer 350 is formed on the first side 310a of the circuit board 310. The first dielectric layer 350 has at least one first dielectric opening 350a. The first dielectric opening 350a exposes part of the connection circuit layer 140 and/or part of the via 314.

In this embodiment, the second dielectric layer 360 may be formed on the second side 310b of the circuit board 310. The second dielectric layer 360 has at least one second dielectric opening 360a. The second dielectric opening 360a exposes part of the second circuit layer 113 and/or part of the via 314.

In terms of structure, the embedded device structure 500 of this embodiment is similar to the embedded device structure 300 of the third embodiment, with the main difference being that the connection pads 521 and 522 of the electronic device 520 have different configurations.

6 is a schematic cross-sectional view of an embedded device structure according to a sixth embodiment of the invention.

The embedded element structure 600 of this embodiment is similar to the embedded element structure 500 of the fifth embodiment, and similar components thereof are denoted by the same reference numerals, and have similar functions, materials or formation methods, and descriptions are omitted. In terms of structure, the buried device structure 600 of this embodiment is similar to the buried device structure 500 of the fifth embodiment. The main difference is that the first dielectric layer 650 has a first dielectric that exposes the electronic components 520. Opening 650a.

7 is a schematic cross-sectional view of an embedded device structure according to a seventh embodiment of the invention.

The embedded element structure of this embodiment is similar to the embedded element structure 600 of the sixth embodiment, and similar components are denoted by the same reference numerals, and have similar functions, materials, or formation methods, and descriptions are omitted. In terms of structure, the embedded element structure 700 of this embodiment is similar to the embedded element structure 600 of the sixth embodiment, with the main difference being: in the embedded element structure 700 of this embodiment, the circuit board 410 The through groove 410 c (shown in FIG. 4B) and the at least one through hole 114 may be structurally connected to each other. For example, the manufacturing method of FIGS. 4A to 4C can be used to form the circuit board 410 with the through slot 410c and the via 114 structurally connected to each other.

FIG. 8 is a schematic cross-sectional view of an embedded device structure according to an eighth embodiment of the present invention.

The embedded element structure of this embodiment is similar to the embedded element structure 700 of the seventh embodiment, and similar components are denoted by the same reference numerals, and have similar functions, materials or formation methods, and descriptions are omitted. In terms of structure, the embedded element structure 800 of this embodiment is similar to the embedded element structure 700 of the seventh embodiment, with the main difference being: the electronic element 820 in the embedded element structure 800 is, for example, a chip. The package or other electronic components with active components.

Taking a chip as an example, the connection pad 821 of the electronic component 820 may be a die pad, and the connection pad 821 is located on the active surface 820a. The first electrical connection surface 112a and the second electrical connection surface 821a of the connection pad 821 may be substantially coplanar. The connection circuit layer 140 covers and contacts the first electrical connection surface 112a and each of the second electrical connection surfaces 821a. The connection pad 821 is electrically connected to the first circuit layer 112 through the connection circuit layer 140.

In this embodiment, the heat dissipation element 20 may be disposed on the back surface 820b of the electronic element 820 (ie, the surface opposite to the active surface 820a). The heat dissipation element 20 may include a heat dissipation plate, a heat dissipation fin, etc., but the present invention is not limited thereto. The heat generated by the electronic element 820 can be transferred to the outside through the heat dissipation element 20, so that the embedded element structure 800 can have a better heat dissipation effect, but the present invention is not limited to this.

In this embodiment, the heat dissipation element 20 may directly contact the back surface 820b of the electronic element 820, but the present invention is not limited to this. In an unillustrated embodiment, a thermally conductive adhesive may be provided between the heat dissipation element 20 and the back surface 820b of the electronic element 820.

In an embodiment not shown, a heat dissipation element similar to the heat dissipation element 20 can also be disposed on the first dielectric layer 650.

9 is a schematic cross-sectional view of an embedded device structure according to a ninth embodiment of the present invention.

The embedded element structure of this embodiment is similar to the embedded element structure 700 of the seventh embodiment, and similar components are denoted by the same reference numerals, and have similar functions, materials or formation methods, and descriptions are omitted. In terms of structure, the embedded device structure 900 of this embodiment is similar to the embedded device structure 700 of the seventh embodiment. The main difference is that the electronic component 920 in the embedded device structure 900 is, for example, an optical sensor chip. (For example: chips including Charge-coupled Device (CCD)), acoustic sensor chips or other sensor chips suitable for receiving external signals. The electronic component 920 may have a sensor area 920a. The sensing area 920a is suitable for receiving external signals.

In this embodiment, a cover layer 30 may be provided on the sensing area 920a. The protective layer 30 can reduce possible damage to the sensing area 920a. In an embodiment, the protective layer 30 is, for example, a hard coating layer, but the invention is not limited thereto. In an embodiment, the protective layer 30 may be a glass plate, a quartz plate, a rigid plastic plate, or other similar rigid plate-shaped bodies.

In summary, in the embedded component structure of the present invention, the electronic component and the circuit board are directly electrically connected by the connection circuit layer, and the via hole between the electronic component and the circuit board can be eliminated or eliminated. Therefore, the manufacturing method of the embedded element structure can be simpler and the thickness can be thinner. In addition, by connecting the circuit layer, the length of the circuit between the electronic component and the circuit board can be reduced, the signal transmission time can be reduced, and the transmission rate between different electronic components can be increased.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be determined by the scope of the attached patent application.

100, 200, 300, 400, 500, 600, 700, 800, 900: embedded component structure 110, 310’, 310, 410’, 410: circuit board 110a, 310’a, 310a, 410a: first side 110b, 310b, 410b: second side 110c, 410c: through slot 310e: Through hole 111: core layer 111d: sidewall of the core layer 112, 112’, 112”: the first circuit layer 112a: The first electrical connection surface 112d: sidewall of the first circuit layer 113: second circuit layer 113a: The third electrical connection surface 113d: sidewall of the second circuit layer 114, 114’, 114”, 314: via 120, 520, 820, 920: electronic components 820a: active side 820b: back 920a: sensing area 121, 821: connecting pad 121a, 521a, 821a: the second electrical connection surface 521: first connection pad 522: second connection pad 130: Dielectric material layer 130a, 530a: Dielectric surface 530: first dielectric material layer 131, 531: Covering part 131a, 531a: Dielectric opening 535: second dielectric material layer 535a: Dielectric opening 140: connection line layer 140h1, 140h2, 140h3: thickness 150, 250, 350, 450, 650: first dielectric layer 150a, 250a, 350a, 450a, 650a: first dielectric opening 160, 260, 360, 460: second dielectric layer 160a, 260a, 360a, 460a: second dielectric opening 170: third circuit layer 180: fourth circuit layer 590: circuit layer 10: Carrier 20: Heat dissipation components 30: protective layer 10a: Carrier surface R: area

1A to 1H are schematic cross-sectional views of a method for manufacturing an embedded device structure according to a first embodiment of the present invention. FIG. 1I is a schematic top view of an embedded device structure according to the first embodiment of the present invention. 2 is a schematic cross-sectional view of an embedded device structure according to a second embodiment of the present invention. 3A to 3E are schematic cross-sectional views of a method for manufacturing an embedded device structure according to a third embodiment of the present invention. 4A, 4B, and 4D are schematic bottom views of a method for manufacturing an embedded device structure according to a fourth embodiment of the present invention. 4C, 4E to 4H are schematic cross-sectional views of a method for manufacturing an embedded device structure according to a fourth embodiment of the present invention. 5A to 5F are schematic cross-sectional views of a manufacturing method of an embedded device structure according to a fifth embodiment of the present invention. FIG. 5G is a schematic top view of an embedded device structure according to the fifth embodiment of the present invention. 6 is a schematic cross-sectional view of an embedded device structure according to a sixth embodiment of the invention. 7 is a schematic cross-sectional view of an embedded device structure according to a seventh embodiment of the invention. FIG. 8 is a schematic cross-sectional view of an embedded device structure according to an eighth embodiment of the present invention. 9 is a schematic cross-sectional view of an embedded device structure according to a ninth embodiment of the present invention.

100: Buried component structure

110: circuit board

110a: first side

110b: second side

110c: wear slot

111: core layer

112: first circuit layer

113: second circuit layer

114: Via

120: electronic components

121: connection pad

130: Dielectric material layer

131: Cover

131a: Dielectric opening

140: connection line layer

150: first dielectric layer

150a: first dielectric opening

160: second dielectric layer

160a: second dielectric opening

170: third circuit layer

180: fourth circuit layer

R: area

Claims (22)

A built-in component structure, including: A circuit board has a through slot, and the circuit board includes: A core layer A first circuit layer; A second circuit layer and the first circuit layer are respectively located on two opposite sides of the core layer, and the through slot penetrates at least the first circuit layer and the core layer; and At least one via hole penetrates the core layer to electrically connect the first circuit layer and the second circuit layer; An electronic component is disposed in the through groove, wherein the electronic component includes a plurality of connection pads exposed outside the through groove, and a first electrical connection surface of the first circuit layer and one of each of the connection pads The second electrical connection surface is coplanar; A dielectric material layer at least filled in the through groove, wherein the Young's modulus of the core layer is greater than the Young's modulus of the dielectric material layer; and A connection circuit layer covers and contacts the first electrical connection surface and each of the second electrical connection surfaces, and the connection pads are electrically connected to the first circuit layer through the connection circuit layer. In the embedded device structure described in claim 1, wherein the dielectric material layer is further filled between each of the connection pads and the first circuit layer, and has the same electrical connection surface as the first electrical connection surface. A flat dielectric surface, the connection line layer covers and contacts the first electrical connection surface, the dielectric surface and the second electrical connection surface. As described in item 2 of the scope of patent application, in the embedded device structure, in the cross section perpendicular to the first electrical connection surface, the connection circuit layer is on the first electrical connection surface, the dielectric surface and the The cross-sectional thickness of the second electrical connection surface is uniform. As described in the first item of the patent application, the cross-sectional area of the slot is larger than the surface area of the electronic component on the second electrical connection surface. The embedded component structure described in item 1 of the scope of patent application further includes: A first dielectric layer is disposed on the same side of the core layer as the first circuit layer, covering at least part of the first circuit layer and at least part of the connecting circuit layer, and the first dielectric layer has exposed At least one opening of the first circuit layer or the connecting circuit layer. According to the embedded device structure described in the 5th item of the scope of patent application, the constituent material of the first dielectric layer includes a solder mask material. As described in the first item of the scope of patent application, the embedded device structure, wherein the dielectric material layer has a covering portion located outside the through groove, covering the core layer on the side where the second circuit layer is located, and covering At least part of the second circuit layer. According to the embedded device structure described in claim 7, wherein the covering portion of the dielectric material layer has at least one dielectric opening exposing the second circuit layer or the via hole. The embedded component structure described in item 7 of the scope of patent application further includes: A second dielectric layer covers the covering portion of the dielectric material layer, and the second dielectric layer has at least one opening exposing the second circuit layer or the via hole. In the embedded device structure described in item 9 of the scope of patent application, the constituent material of the second dielectric layer includes a solder mask material. In the embedded device structure described in item 1 of the scope of the patent application, the through slot is communicated with the at least one via. A manufacturing method of an embedded element structure includes: Provide a carrier; Place a circuit board on the carrier, the circuit board has a through slot, and the circuit board includes: A core layer A first circuit layer, and the first circuit layer contacts the carrier; and A second circuit layer and the first circuit layer are respectively located on opposite sides of the core layer, and the through slot penetrates at least the first circuit layer and the core layer; Placing an electronic component on the carrier, the electronic component having a plurality of connection pads, wherein the connection pads contact the carrier; After placing the circuit board and the electronic component on the carrier and embedding the electronic component in the slot, a dielectric material layer is formed on the carrier, and the dielectric material layer is at least filled in the slot , And the Young's modulus of the core layer is greater than the Young's modulus of the dielectric material layer; Removing the carrier to expose the first circuit layer and the connection pads, and a first electrical connection surface of the first circuit layer and a second electrical connection surface of each of the connection pads are coplanar; After the carrier is removed, a connecting circuit layer is formed, and the connecting circuit layer covers and contacts the first electrical connection surface and each of the second electrical connection surfaces. As described in item 12 of the scope of patent application, the method for manufacturing an embedded component structure, wherein the circuit board further includes: At least one via hole penetrates the core layer to electrically connect the first circuit layer and the second circuit layer. According to the manufacturing method of the embedded device structure described in item 13 of the scope of the patent application, the through slot and the at least one via are connected to each other. The manufacturing method of the embedded component structure as described in item 12 of the scope of patent application further includes: After forming the connecting circuit layer, a first dielectric layer is formed, and the first dielectric layer covers at least part of the first circuit layer and at least part of the connecting circuit layer. According to the manufacturing method of the embedded device structure described in the scope of patent application, the constituent material of the first dielectric layer includes a solder mask material. The manufacturing method of the embedded component structure as described in item 12 of the scope of patent application further includes: After forming the dielectric material layer, forming at least one through hole penetrating the core layer, the first circuit layer and the second circuit layer on the circuit board; and A conductive material is filled in the at least one through hole to form at least one through hole penetrating the core layer to electrically connect the first circuit layer and the second circuit layer. The manufacturing method of the embedded device structure as described in item 12 of the scope of patent application, wherein the dielectric material layer has a covering portion located outside the through groove, covering the core layer on the side where the second circuit layer is located , And cover at least part of the second circuit layer. As described in item 18 of the scope of patent application, the manufacturing method of the embedded element structure further includes: At least one dielectric opening is formed on the covering portion of the dielectric material layer, and the at least one dielectric opening exposes the second circuit layer. As described in item 18 of the scope of patent application, the manufacturing method of the embedded element structure further includes: A second dielectric layer is formed to cover the covering portion of the dielectric material layer. The manufacturing method of the embedded component structure as described in item 20 of the scope of patent application further includes: At least one second opening is formed on the second dielectric layer, and the at least one second opening exposes the second circuit layer. According to the manufacturing method of the embedded device structure described in the scope of patent application item 20, the constituent material of the second dielectric layer includes a solder mask material.

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