1264051 16264twf.doc/m 九、發明說明： 【發明所屬之技術領域] 本發明是有關於一種基板製程，且特別是有關於一種 内埋元件（embedded component)之基板製程。 【先前技術】 ‘般而吕 、、來塔基板主要是由多層經過圖案化的線路 f (patterned circuit layer)以及介電層（didectric layer)交替1264051 16264twf.doc/m IX. Description of the Invention: [Technical Field of the Invention] The present invention relates to a substrate process, and more particularly to a substrate process for an embedded component. [Prior Art] ‘General Lv, and the tower substrate is mainly composed of a plurality of patterned circuit layers and a didectric layer.
受合所構成。其中’ ®案化線路層是由㈣層㈣—顏） 經過微影與㈣製程定義形成，而介f層配置於圖案化線 路層之間，用以隔離職錢路層。此外，相疊之圖案化 線路層之間是透過貫穿介電層的鑛通孔Th沙 I^ole，PTH)或導電孔道(c〇nductive心)而彼此電性連接。最 ί件配置㈣電子元難航件、被動 ielet.丨θ 。卩4路之魏設計耐料子訊號傳遞 (electncal S1gnal propagati〇n)之目的。 然而，隨著市場對於電子產品需 方便的需求，因此在目前的電子產 2幻且攜π 線路基板的電子元件設計為可埋 ^原'先焊接於 如此可以增加基板表面之佈==二 術中，於廢合線路層以及介電層以件的技 層經過高溫固化處理之後，多為不板蚪，由於介電 因此容易造成内埋元件與介電芦形文的固化態， 隙’這些空隙不但容易影響“時▲板與=== 5 1264051 16264twf.do〇/m 性 丄也έ影專壓合時内埋元件與接點的對位。此外，在單 曰W電層之線路基板中，介電層的厚度通常比内埋元件的 厚度為小，容易造成無法將元件内埋入基板之中等問題。 【發明内容】 口本發明的目的就是在提供一種内埋元件之基板製 程，以改善核心層與内埋元件之間的結合性。 ^本發明提出一種内埋元件之基板製程。首先，提供一 第一金屬層以及1埋元件，第—金屬層至少具有二凸 點、，其對應連接該件；接著，放置該内埋元件於_ ^層埋孔中，並壓合第—金屬層以及核心層；之後， 圖案化第一金屬層，w游士、_ & ,. . 性連接該第-線路層。 ▲路層，且内埋元件電 -内出ΓΓ埋元件之基板製程。首先，放置 屬γγ，：·層之—埋孔中；接著，提供-第一全 2 ;弟人:屬層至少具有二凸點，其對應該内埋元件: 金屬層以及核心層，以使該二凸點電性連 ί: 牛’以及圖案化第一金屬層，以形成-第一妗 路層，且該内埋元件電性連接該第一線路層。 、、泉 明的—實施例所述，上述之:心層至少包括 弟一；I电層、一第二介電層以及一第三介電声，一 ，二介電層呈固化態，而第二介電層呈半固化‘广 第二介電層於壓合第—金屬層以及核心層之步ς中，夕可 填入於埋孔中，並包覆於内埋元件之周圍表面。其 心層之埋孔例如為一貫孔，其貫穿第一、 丄核 ^—只卑二介電 1264051 16264twf.doc/m 箔’此二凸點112、114例如是電鑛所產生的銅凸點。 =;T2之屬層110之二凸點與内 2 124牢固接合。此外，第-全屬 ^ , Π9 11, 114刺牙弟四介電層130之 後凸點112、U4之頂端可突出於第四介電層13〇之上。 其中’第四介電層13〇例如是玻璃氧基樹脂(fr_4、fr^、 ，順丁烯二酸酸亞胺(B ismaleimide_Triazine，B T)或者環氧 樹脂(epoxy resin)等浸潰（preprag)介電材料。 义羊 接著，請參考圖2，提供-核心層14〇，此核心層14〇 =由多層介電層堆疊而成。其中，這些介電層例如是由預 先袭作的第-介電層142、第二介電層144以及第三介本 1=組合：成，第一、第三介電層142、146為固化態： ^k，而第一介電層144為半固化態之介電層，與第四 介電層130之材質相同。也就是說，第二介電層144於常 溫:同時具有流體的形㈣性以及固體陳子凝聚特性， 當第二介電層144受熱時’則不再有流體的形變特性 是熱固成^。_本實施例中，係以三層之介電層為例，Conformity is formed. The '® case circuit layer is formed by the (four) layer (four)-element) through the lithography and (4) process definition, and the f layer is disposed between the patterned line layers to isolate the job money layer. In addition, the intersecting patterned circuit layers are electrically connected to each other through a through-hole, a through hole, a through hole, or a conductive hole (c〇nductive core). The most configurable (four) electronic element difficult parts, passive ielet. 丨 θ. The purpose of the 卩4 road Wei design material resistance signal transmission (electncal S1gnal propagati〇n). However, with the demand for electronic products in the market, the electronic components of the current electronic production and π-line substrate are designed to be buried in the original 'first-welded' cloth that can increase the surface of the substrate. After the high-temperature curing treatment of the waste circuit layer and the dielectric layer of the dielectric layer, most of the layers are not plated, and the dielectric layer is easy to cause the solidified state of the embedded component and the dielectric aloe, and the gap Not only easy to affect the "time ▲ board and === 5 1264051 16264twf.do 〇 / m 丄 丄 专 专 专 专 专 专 专 内 内 内 内 内 内 内 内 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 The thickness of the dielectric layer is generally smaller than the thickness of the embedded component, which may cause problems in that the component cannot be buried in the substrate. [Invention] The object of the present invention is to provide a substrate process for embedding components to improve The bonding between the core layer and the embedded component. The present invention provides a substrate process for embedding components. First, a first metal layer and a buried component are provided. The first metal layer has at least two bumps, and the pair thereof The component should be connected; then, the buried component is placed in the buried hole of the layer, and the first metal layer and the core layer are pressed; after that, the first metal layer is patterned, w, _ & Sexually connected to the first-line layer. ▲The road layer, and the buried component is electrically-in-out the substrate process of the buried component. First, it is placed in the γγ,:· layer-buried hole; then, provides - first full 2 ; younger: the genus layer has at least two bumps, which correspond to the embedded components: the metal layer and the core layer, so that the two bumps are electrically connected to the 355: and the patterned first metal layer to form - a circuit layer, and the embedded component is electrically connected to the first circuit layer. According to the embodiment of the invention, the core layer includes at least one of the first layer; the first electrical layer and the second dielectric layer. And a third dielectric sound, the first and second dielectric layers are in a cured state, and the second dielectric layer is semi-cured and the second dielectric layer is in the step of pressing the first metal layer and the core layer. It can be filled in the buried hole and covered on the surrounding surface of the embedded component. The buried hole of the core layer is, for example, a consistent hole, which penetrates the first and the nucleus. Only the second dielectric 1264051 16264twf.doc/m foil 'The two bumps 112, 114 are, for example, copper bumps produced by the electric ore. =; the two bumps of the T2 layer 110 are firmly bonded to the inner 2 124. , the first dielectric layer 13 , the top of the bump 112 , the top of the U4 may protrude above the fourth dielectric layer 13 。. Wherein the fourth dielectric layer 13 〇 It is a preprag dielectric material such as glass epoxy resin (fr_4, fr^, , bemaleimide_Triazine, BT or epoxy resin). 2, a core layer 14 is provided, which is formed by stacking multiple dielectric layers. Wherein, the dielectric layers are, for example, a pre-existing first dielectric layer 142, a second dielectric layer 144, and a third dielectric 1 combination: the first and third dielectric layers 142, 146 are cured. The state: ^k, and the first dielectric layer 144 is a semi-cured dielectric layer, which is the same material as the fourth dielectric layer 130. That is to say, the second dielectric layer 144 is at normal temperature: it has both the shape of the fluid and the solid agglomeration property. When the second dielectric layer 144 is heated, the deforming property of the fluid is no longer thermoformed. . In this embodiment, a three-layer dielectric layer is taken as an example.
而半固化態之第二介電層144位於固化態之第—與第三公 電層142、146之中，但不以此為限。 I 承上所述^第一、笫一以及第三介電層142、144、 146堆疊之後，例如以機械鑽孔或雷射成孔等方式形成〜 1264051 l6264twf.doc/m 適當深度之埋孔148，此深度可依照圖丨之内埋元件12〇 之厚度來決定，埋孔148例如是一貫孔或—凹孔。舉例來 說，可用鑽頭貫穿核心層140以形成—貫孔，或是用雷射 來燒灼第一與第二介電層U2、144形成—凹孔。 接著’請參考圖3’將内埋元件12〇放置於核心層14〇 之-埋孔148中。在本實施例中，内埋元件⑽例如是電 晶體等絲元件，或是電阻、電料麵元件，而内埋元 件i2〇之電極m、m與其上方的第一金屬層11〇電性連 接。此外’核心層140的下方亦可選擇性地配置一第五介 電層150以及一第二金屬層16〇，第五介 斑第二 介電層144同樣是半固化介電4，而第二金^ 16〇例如 是-銅羯。在後續之壓合製程中，係以第一金屬層11〇、 ^四介電層120、核心層14()、第五介電層15()以及第二金 層160的基板結構為範例進行說明，但不以此為限。 睛參考圖4，壓合第-金屬層UG、第四介電層13〇、 内埋元件120、核心層14〇、第五介電層15〇以及第二金屬 層160。，於第四介電層13〇、核心層14〇之第二介電層 H4以及第五介電層15()均為半固化態之介電層，因此在 星合的過程中，核心層14〇之埋孔148被流動形變的半固The second dielectric layer 144 in the semi-cured state is located in the first and third public layers 142, 146 of the cured state, but is not limited thereto. I, after stacking the first, first and third dielectric layers 142, 144, 146, for example, by mechanical drilling or laser hole formation, etc. ~ 1264051 l6264twf.doc/m buried hole of appropriate depth 148, the depth can be determined according to the thickness of the buried component 12A of the figure, and the buried hole 148 is, for example, a uniform hole or a concave hole. For example, a drill bit may be used to penetrate the core layer 140 to form a through hole, or a laser may be used to cauterize the first and second dielectric layers U2, 144 to form a recessed hole. Next, please refer to Fig. 3' to place the embedded component 12'' in the buried hole 148 of the core layer 14''. In this embodiment, the embedded component (10) is, for example, a wire component such as a transistor, or a resistor or an electric component, and the electrodes m, m of the embedded component i2 are electrically connected to the first metal layer 11 above it. . In addition, a fifth dielectric layer 150 and a second metal layer 16 are selectively disposed under the core layer 140, and the fifth dielectric layer 144 is also a semi-cured dielectric 4, and the second Gold ^ 16 〇 is for example - copper enamel. In the subsequent pressing process, the substrate structure of the first metal layer 11 , the fourth dielectric layer 120 , the core layer 14 ( ), the fifth dielectric layer 15 ( ), and the second gold layer 160 is taken as an example. Description, but not limited to this. Referring to Fig. 4, the first metal layer UG, the fourth dielectric layer 13A, the buried device 120, the core layer 14A, the fifth dielectric layer 15A, and the second metal layer 160 are laminated. The second dielectric layer H4 and the fifth dielectric layer 15 are disposed on the fourth dielectric layer 13A, and the fifth dielectric layer 15 is a semi-cured dielectric layer. Therefore, during the star bonding process, the core layer 14 The buried hole 148 of the crucible is deformed by the flow of the semi-solid
化態介電層130、144、15〇所填滿，且包覆於内埋元件i2Q 之周圍表面，以加強核心層14〇與内埋元件12〇之接合性。 上述之[a過私例如是以熱壓合的方式具體實施，之後， ㈣，態之介電層13G、144，再以紫外光照射或加教 的方式予以固化成型。 … 9 1264051 16264twf.doc/m 4 接著，請參考圖5，第一金屬層110以及第二金屬層 160經過蝕刻之後，形成圖案化之第一線路層u〇a以及第 二線路層160a，以作為訊號傳輸之媒介。由於内埋元件12〇 透過二凸點112、114電性連接於圖案化後之第一線路層 ll〇a，因此不需再進行習知鑽孔、電鍍等鍍孔製程，以節 省基板製程的時間以及成本。此外，利用凸點丨12、工 作為第一線路層ll〇a連接内埋元件12()之導通結構，亦可 • 提高訊號傳遞間的電性以及可靠度，以避免訊號失真。 明苓考圖6〜圖1〇，其繪示本發明第二實施例之一種 内埋7L件之基板製程的示意圖。有關圖6之第一金屬層11〇 與内埋元件120的熱壓合步驟，請參考圖1之說明，相同 的t號代表相同的構件，在此不再贅述。在圖7之步驟中， 本實施例提供由多數個介電層242、244、246所堆疊之_ 核心層240，且這些介電層242、2私、2仏之至少一或全 部介電層係呈半固化態。也就是說，至少一介電層同時具 ㈣體的形㈣性以朗體的粒子凝聚特性即可。在本實 中，係以二層半固化態之介電層242、244、2牝為範 例说月但不以此為限。此外，核心層240例如以機械鑽 孔或雷射成孔等方式形成一適當深度之埋孔248，例如是 一貫孔，一凹孔二如第一實施例所述。 接著’在後續圖8之堆疊步驟、圖9之壓合步驟以及 圖10之圖案化之步驟，係以第一金屬層110、第四介電； 130、核心層240、第五介電層150以及第二金屬層160的 基板結構為範例進行說明，但不以此為限。請參考圖8之 1264051 16264twf.doc/m 堆疊步驟包括：將内埋元件丨2〇放置於核心層24〇之一埋 孔248巾’且内埋元件120與其上方之第一金屬層ιι〇電 性連接。此外，核心層240的下方還可配置一第五介電層 150以及一第二金屬層160。接著，如圖9所示，以熱壓^ 的方式壓合第-金屬層110、第四介電層13〇、内埋元件 120、核心層240、第五介電層15〇以及第二金屬層16〇。 由於第四介電層13〇、核心層240以及第五介電層15〇均 # 為半固化悲之介電層，因此在壓合的過程中，核心層240 之埋孔248被流動形變的半固化態介電層13〇、242、244、 246、150所填滿，且包覆於内埋元件12〇之周圍表面，以 加強核心層240與内埋元件120之接合性。之後，再將第 四’丨黾層130、核心層240以及第五介電層15〇固化成型。 最後，請參考圖10,圖案化第一金屬層11〇以及第二 金屬層160以形成第一與第二線路層u〇a、16〇a，且内埋 元件120與圖案化後之第一線路層11〇&電性導通，以構成 一基板。其中，内埋元件120例如是主動元件或被動元件。 請麥考圖11〜圖14,其繪示本發明第三實施例之一 種内埋元件之基板製程的示意圖，相同的標號代表相同的 構件。圖11之步驟包括提供一核心層14〇，並將一内埋元 件120放置於核心層140之一埋孔148中，而非如第一實 施例所述先將内埋元件12〇固定於第一金屬層n〇上。其 中，核心層140例如是由預先製作的第一介電層、第 二介電層144以及第三介電層146組合而成，第一、第三 "電層142、146為固化態之介電層，而第二介電層144 1264051 16264twf.doc/m 為半固化態之介電層，但不此為限。此外，埋孔148例如 是以機械鑽1¾雷射纽#方倾形成之 如第一實施例所述。 4凹孔 接著，請參考圖12，提供一第一金屬層11〇， ΐ屬！有ιΓ凸點112、114，其對應於内埋元件120 一迅，22、124。此外，核心層14〇的下方還可選 配置-第五介電層15G以及—第二金屬層16Q。 屬層110元成凸點112、114之對位之後，即可進行第一金 屬層110、第四介電層13〇、核心層14〇、第 5〇 2第3屬層⑽的堆疊步驟。之後，如圖13所二壓 i 屬層110、第四介電層130、内埋元件120、核心 一日、弟五介電層150以及第二金屬層160 第一金屬層110之凸點112、114電性連接内而 核心層M0之埋孔148被半固化態之第二介電層144、第 四介電層13仏及第五介電層15()所填滿，且包覆於内埋 之周圍表面’以加強核心層刚與内埋元件120 之接合性。 入严”考圖14 ’圖案化第一金屬層110以及第二 1層⑽以形成第-與第二線路層u〇a、l6〇a，且内埋 :L:2〇ir案化後之第一線路層u〇a電性導通，以構成 ’内埋元件12°例如是主航件或被動元件。 4考圖15〜圖18’其緣示本發明第四實施例之一 槿Γ里^^之基板製程的示意圖，㈣的標號代表相同的 構件。在圖15之步财，提供由多數個介電層242、244、 12 1264051 16264twf.doc/m 246所堆豎之一核心層240,並將_内埋元件12〇放置於核 心層240之一埋孔248中。其中，這些介電層242、2料、 246之至少一或全部介電層係呈半固化態。也就是說，至 > 一 η電層同時具有流體的形變特性以及固體的粒子凝聚 特性即可。在本實施例中，係以三層之介電層242、244、 246為範例。兒明，但不以此為限。此外，核心層24〇例如 以機械鑽孔或雷射成孔等方式形成一適當深度之埋孔，例 ⑩ 如是一貫孔或一凹孔。 接著，在後續圖16之堆疊以及凸點定位之步驟、圖 17之壓合步驟以及圖18之圖案化步驟均與第三實施例之 圖12〜圖η之步驟相同，内埋元件12〇最後被第四介電 層130、核心層14〇以及第五介電層15〇包覆，以加強核 心層140與内埋元件12〇之接合性。此外，内埋元件12〇 與其上方之第一線路層ll〇a電性導通，以構成一基板。 由以上第一〜第四實施例可知，本發明因採用凸點 (bump)作為一線路層連接内埋元件之導通結構，以提高 訊=傳遞間的電性以及可靠度，故能避免訊號失真。接著， 本發明再以至少一半固化態介電層將内埋元件加以包覆， 由於半固化態介電層同時具有流體的形變特性以及固體的 • 粒子凝XK特性，能充分地將核心層與内埋元件間的空隙填 滿，故能加強核心層與内埋元件之間的接合性。也由於内 埋兀件被埋入於基板之核心層中，不會佔用基板表面的空 間，故能減少基板表面的銲點數，並增加基板的空間利用 性0 13 1264051 16264twfdoc/m 148 :埋孔 150 :第五介電層 160 :第二金屬層 110a :第一線路層 160a :第二線路層 240 :核心層 242、244、246 :介電層 248 :埋孔The chemical dielectric layers 130, 144, and 15 are filled and covered on the peripheral surface of the embedded component i2Q to enhance the bonding of the core layer 14 and the embedded component 12A. The above-mentioned [a private operation is carried out, for example, by thermocompression bonding, and then, (iv), the dielectric layers 13G and 144 are cured by ultraviolet light irradiation or teaching. 9 1264051 16264twf.doc/m 4 Next, referring to FIG. 5, after the first metal layer 110 and the second metal layer 160 are etched, the patterned first wiring layer u〇a and the second wiring layer 160a are formed to As a medium for signal transmission. Since the embedded component 12 is electrically connected to the patterned first circuit layer 11a through the two bumps 112 and 114, it is not necessary to perform a conventional plating process such as drilling or plating to save the substrate process. Time and cost. In addition, by using the bump 丨12, the first wiring layer 11a is connected to the conductive structure of the buried component 12(), and the electrical connection between the signal transmission and the reliability can be improved to avoid signal distortion. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 6 to FIG. 1A are schematic diagrams showing a substrate process for embedding a 7L piece according to a second embodiment of the present invention. For the thermal compression bonding step of the first metal layer 11 图 of FIG. 6 and the embedded component 120, please refer to FIG. 1 , and the same t symbol represents the same component, and details are not described herein again. In the step of FIG. 7, the present embodiment provides a core layer 240 stacked by a plurality of dielectric layers 242, 244, 246, and at least one or all of the dielectric layers 242, 2, 2, and 2 It is semi-cured. That is to say, at least one dielectric layer has the shape (four) of the (four) body at the same time as the particle agglomeration characteristics of the body. In the present embodiment, the dielectric layers 242, 244, and 2 of the two-layer semi-cured state are taken as an example, but not limited thereto. In addition, the core layer 240 forms a buried hole 248 of a suitable depth, such as a mechanical drill hole or a laser hole, for example, a uniform hole, and a recessed hole 2 as described in the first embodiment. Then, in the subsequent stacking step of FIG. 8, the pressing step of FIG. 9, and the patterning step of FIG. 10, the first metal layer 110, the fourth dielectric layer; 130, the core layer 240, and the fifth dielectric layer 150 are used. The substrate structure of the second metal layer 160 is described as an example, but is not limited thereto. Please refer to FIG. 8 for 1264051 16264 twf.doc/m. The stacking step includes: placing the embedded component 丨2〇 in one of the core layer 24's buried hole 248, and the embedded component 120 and the first metal layer above it are electrically charged. Sexual connection. In addition, a fifth dielectric layer 150 and a second metal layer 160 may be disposed under the core layer 240. Next, as shown in FIG. 9, the first metal layer 110, the fourth dielectric layer 13A, the buried device 120, the core layer 240, the fifth dielectric layer 15A, and the second metal are press-bonded by heat pressing. Layer 16〇. Since the fourth dielectric layer 13, the core layer 240, and the fifth dielectric layer 15 are both semi-cured dielectric layers, the buried vias 248 of the core layer 240 are flow-deformed during the lamination process. The semi-cured dielectric layers 13A, 242, 244, 246, 150 are filled and coated around the surrounding surface of the embedded component 12A to enhance the bondability of the core layer 240 with the embedded component 120. Thereafter, the fourth 'deuterium layer 130, the core layer 240, and the fifth dielectric layer 15 are cured. Finally, referring to FIG. 10, the first metal layer 11 〇 and the second metal layer 160 are patterned to form first and second circuit layers u 〇 a, 16 〇 a, and the buried element 120 and the patterned first The circuit layer 11 is electrically conductive to form a substrate. The embedded component 120 is, for example, an active component or a passive component. Please refer to FIG. 14 to FIG. 14 for a schematic diagram of a substrate process for a buried component according to a third embodiment of the present invention, and the same reference numerals denote the same components. The step of FIG. 11 includes providing a core layer 14 and placing a buried component 120 in a buried via 148 of the core layer 140 instead of first fixing the embedded component 12 to the first embodiment as described in the first embodiment. A metal layer is n〇. The core layer 140 is formed, for example, by a combination of a first dielectric layer, a second dielectric layer 144, and a third dielectric layer 146. The first and third electrical layers 142 and 146 are in a cured state. The dielectric layer, and the second dielectric layer 144 1264051 16264twf.doc/m is a semi-cured dielectric layer, but not limited thereto. Further, the buried hole 148 is formed, for example, by a mechanical drill 13⁄4 laser neon # as described in the first embodiment. 4 recessed holes Next, please refer to Figure 12, providing a first metal layer 11〇, ΐ! There are Γ bumps 112, 114, which correspond to the embedded component 120, 22, 124. In addition, a fifth dielectric layer 15G and a second metal layer 16Q are optionally disposed under the core layer 14A. After the sub-layer 110 is formed into the alignment of the bumps 112 and 114, the stacking step of the first metal layer 110, the fourth dielectric layer 13A, the core layer 14〇, and the 5th 2rd 3rd layer (10) can be performed. Thereafter, as shown in FIG. 13, the second voltage layer 110, the fourth dielectric layer 130, the buried component 120, the core one day, the fifth dielectric layer 150, and the second metal layer 160 are bumps 112 of the first metal layer 110. The buried hole 148 of the core layer M0 is filled with the second dielectric layer 144, the fourth dielectric layer 13 and the fifth dielectric layer 15 () in a semi-cured state, and is covered by The buried surrounding surface 'to strengthen the bond of the core layer to the embedded element 120. The first metal layer 110 and the second layer (10) are patterned to form the first and second circuit layers u〇a, l6〇a, and embedded: L: 2〇ir The first circuit layer u〇a is electrically connected to form a 'buried element 12°, for example, a primary or passive element. 4 FIG. 15 to FIG. 18' shows a fourth embodiment of the present invention. The schematic diagram of the substrate process of (^), the reference numerals of (4) represent the same components. In the step of Fig. 15, a core layer 240 is provided which is stacked by a plurality of dielectric layers 242, 244, 12 1264051 16264twf.doc/m 246 And placing the _ buried component 12 埋 in a buried via 248 of the core layer 240. wherein at least one or all of the dielectric layers 242, 2, 246 are semi-cured. , to > an η electrical layer has both the deformation characteristics of the fluid and the particle agglomeration characteristics of the solid. In the present embodiment, the three-layer dielectric layers 242, 244, and 246 are taken as an example. In addition, the core layer 24, for example, is formed by mechanical drilling or laser drilling to form a buried hole of a suitable depth. Or a recessed hole. Next, the steps of stacking and bump positioning in FIG. 16 , the pressing step of FIG. 17 , and the patterning step of FIG. 18 are the same as the steps of FIG. 12 to FIG. 3 of the third embodiment. The buried component 12 is finally covered by the fourth dielectric layer 130, the core layer 14A, and the fifth dielectric layer 15 to strengthen the bond between the core layer 140 and the embedded component 12. Further, the buried component 12〇 The first circuit layer 11a is electrically connected to the upper circuit layer 11a to form a substrate. As can be seen from the above first to fourth embodiments, the present invention uses a bump as a wiring layer to connect the buried component to the conductive structure. In order to improve the electrical and reliability between the transmission and the transmission, the signal distortion can be avoided. Then, the present invention coats the embedded component with at least half of the cured dielectric layer, since the semi-cured dielectric layer has both The deformation characteristics of the fluid and the XK characteristics of the solid particles can fully fill the gap between the core layer and the embedded components, thus enhancing the bond between the core layer and the embedded components. Embedded in the core layer of the substrate It does not occupy the space on the surface of the substrate, so the number of solder joints on the surface of the substrate can be reduced, and the space utilization of the substrate can be increased. 0 13 1264051 16264twfdoc/m 148 : buried hole 150 : fifth dielectric layer 160 : second metal layer 110a : First circuit layer 160a: Second circuit layer 240: Core layer 242, 244, 246: Dielectric layer 248: buried hole
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