CN114203804A - HEMT chip made of silicon carbide-based graphene material and preparation method of HEMT chip - Google Patents
HEMT chip made of silicon carbide-based graphene material and preparation method of HEMT chip Download PDFInfo
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Abstract
本发明公开了一种碳化硅基石墨烯材料的HEMT芯片及其制备方法，该芯片包括：基底、石墨烯层、离子注入区、S/D电极区和G电极；石墨烯层位于所述基底上方，且与所述基底连接；离子注入区位于所述基底内部中心位置，且向上贯穿至所述石墨烯层上表面；S/D电极区位于所述石墨烯层上方且与所述石墨烯层连接；G电极位于所述离子注入区上方，且与所述离子注入区连接。本发明采用石墨烯材料作为导电通道代替传统的异质界面2DEG,实现超高速的电子迁移和导电速率，采用金属半导体接触的肖特基势垒作为栅电源控制整个晶体管的开关，采用SiC作为基底材料，通过半导体工艺现实不同材料的生长集成，构成全新的具有优良特性的晶体管。
The invention discloses a silicon carbide-based graphene material HEMT chip and a preparation method thereof. The chip comprises: a substrate, a graphene layer, an ion implantation area, an S/D electrode area and a G electrode; the graphene layer is located on the substrate above, and connected with the substrate; the ion implantation area is located at the inner center of the substrate, and penetrates upward to the upper surface of the graphene layer; the S/D electrode area is located above the graphene layer and is connected with the graphene layer connection; the G electrode is located above the ion implantation region and is connected to the ion implantation region. The invention uses graphene material as a conductive channel to replace the traditional heterogeneous interface 2DEG, realizes ultra-high-speed electron migration and conduction rate, uses the Schottky potential barrier of metal-semiconductor contact as the gate power supply to control the switch of the entire transistor, and uses SiC as the substrate Materials, through the semiconductor process to realize the growth and integration of different materials, constitute a new transistor with excellent characteristics.
Description
Technical Field
The invention relates to the technical field of semiconductor electronic information, in particular to an HEMT chip made of silicon carbide-based graphene materials and a preparation method thereof.
Background
A typical HEMT (or HFET, MODFET) uses two materials with different energy gaps to form a heterojunction and provide a channel for carriers, and a ternary compound semiconductor such as gaas and gaas is an optional material for forming the device, and may be combined in various ways according to specific applications. The third generation wide bandgap semiconductor represented by gallium nitride (GaN) developed in recent years has been widely applied in the semiconductor field due to its wide bandgap constant, higher electron mobility, strong radiation resistance, good breakdown field strength, high temperature resistance and other characteristics, and its chip has the characteristics of high reverse blocking voltage, low forward on resistance, high operating frequency and the like, but as the application goes deep, the requirements on the performance and function of the high electron mobility chip are higher and higher, and some traditional design structures and material performances face great challenges.
The traditional high electron mobility transistor adopts two heterojunction materials, generally compound semiconductors, two-dimensional electron gas (2DEG) is formed on one side, close to a narrow band, of an interface by utilizing energy band difference of the two materials, the two-dimensional electron gas is far away from scattering atoms of a depletion layer region and moves in a two-dimensional direction in a potential well with a deep interface, the high electron mobility is achieved, and the density and the moving conduction of the 2DEG can be controlled by manufacturing a source electrode, a grid electrode and a drain electrode on the surface of a device through the grid electrode. Thereby realizing the current and the switch of the whole device.
At present, the traditional HEMT is based on a heterojunction material, due to the difficulty of material growth, lattice defects can be caused, the performance of a device is influenced, particularly, the AlN/AlGaN/GaN is very difficult to realize higher material quality, and the voltage and current characteristics, cut-off frequency and reliability of the device are influenced;
in addition, although the mobility of the 2DEG of the traditional high electron mobility device is relatively high, the upper limit rate of the 2DEG is limited by the material and the transmission characteristic of the 2DEG, and the breakthrough from the material is a great solution.
In order to realize high voltage resistance and high mobility, a compound semiconductor with a large forbidden band width and different materials with large difference of the forbidden band widths must be used, more complex and fine growth methods and manufacturing cost and material cost are required, the mass production is not facilitated, and the larger application scenes and the market are limited.
The current research and application show that Graphene (Graphene) is sp2The new material which is formed by tightly stacking hybridized and connected carbon atoms into a single-layer two-dimensional honeycomb lattice structure has excellent optical, electrical and mechanical properties, and the carrier mobility of graphene at room temperature is about 15000cm2V. s, the carrier mobility of graphene can even be as high as 250000cm under certain specific conditions, such as low temperature2V · s. In addition, the electron mobility of the graphene is slightly influenced by temperature change, and the electron mobility of the single-layer graphene is 15000cm at any temperature between 50 and 500K2and/(V · s) or so. In addition, the half-integer quantum Hall effect of electron carriers and hole carriers in the graphene can be observed by changing chemical potential through the action of an electric field, the carriers in the graphene follow a special quantum tunneling effect, back scattering is not generated when the carriers meet impurities, and therefore high carrier mobility of the graphene is achieved.
Therefore, how to provide a HEMT chip of a silicon carbide-based graphene material capable of realizing ultra-high-speed electron mobility and conduction rate and a preparation method thereof are technical problems to be solved by those skilled in the art.
Disclosure of Invention
In view of the above, the present invention provides a HEMT chip of a silicon carbide-based graphene material and a method for manufacturing the HEMT chip, in which a graphene material is used as a conductive channel to replace a conventional hetero-interface 2DEG, so as to realize ultra-high speed electron mobility and a high conduction rate, a schottky barrier contacted by a metal semiconductor is used as a gate power supply to control the switching of the whole transistor, SiC is used as a substrate material, and a semiconductor process realizes the growth and integration of different materials, thereby forming a brand-new high electron mobility transistor with excellent characteristics.
In order to achieve the purpose, the invention adopts the following technical scheme:
a HEMT chip of silicon carbide-based graphene material, comprising: the device comprises a substrate, a graphene layer, an ion implantation region, an S/D electrode region and a G electrode;
the graphene layer is positioned above the substrate and is connected with the substrate;
the ion implantation region is positioned in the center of the inner part of the substrate and penetrates upwards to the upper surface of the graphene layer;
the S/D electrode region is positioned above the graphene layer and is connected with the graphene layer;
the G electrode is positioned above the ion implantation area and is connected with the ion implantation area.
Preferably, the HEMT chip of the silicon carbide based graphene material further includes: a protective layer;
the protective layer is arranged above the graphene layer and the ion injection region except the S/D electrode region and the G electrode.
Preferably, the ion implantation region comprises a heavily doped region and lightly doped regions positioned at two sides of the heavily doped region; the G electrode is positioned above the heavily doped region and is connected with the heavily doped region.
Preferably, the S/D electrode region includes an S electrode and a D electrode, and the S electrode and the D electrode are respectively located on two sides above the graphene layer and connected to the graphene layer.
Preferably, the substrate is SiC.
Preferably, the ion implantation region is an N-type semiconductor ion implantation region or a P-type semiconductor ion implantation region.
Preferably, the S electrode and the D electrode are both metal alloy layers combined by Ti/Al/Ni/Au, and the thicknesses of the layers are respectively Ti20-50 nm; al is 150-200 nm; ni80-120 nm; and Au is 100-150 nm.
Preferably, the G electrode is a metal alloy layer composed of Ni/Au, and each layer has a thickness of
Preferably, the doping concentration of the lightly doped region is 1012cm-3-1015cm-3(ii) a The heavily doped region has a doping concentration of 1019cm-3-1022cm-3。
Another object of the present invention is to provide a method for preparing an HEMT chip of the silicon carbide-based graphene material, including the following steps:
(1) removing photoresist in an injection region on the SiC substrate through a photoetching process, and manufacturing an opening for ion injection by protecting other regions by the photoresist;
(2) implanting required implantation doping element nitrogen ions or phosphorus ions into the open pore region by an ion implantation process to form an N-type semiconductor ion implantation region or implanting Al ions or B ions into the open pore region to form a P-type semiconductor ion implantation region;
wherein. The ion implantation area is divided into a light doping area and a heavy doping area, the light doping area is positioned in the middle, and the heavy doping area is positioned at two ends;
(3) removing the photoresist in the surface protection area during ion implantation, and plating a layer of SiO on the ion implantation area by using the photoetching process2Protective layer (SiO)2The area range of the protective layer is slightly smaller than the area range of the ion implantation area), no SiO2 layer is evaporated in other areas, the substrate is heated to 1200-1400 ℃, because the SiC material is carbonized at high temperature, silicon atoms on the surface can be evaporated and escaped when the silicon carbide substrate is heated to more than 1100 ℃, and stone is formedGraphene layer, then removing SiO with HF acid2The layer, the surface graphene layer formed at high temperature is connected with the edge of the heavily doped region and slightly covers the boundaries of two ends of the heavily doped region;
(4) manufacturing S and D electrodes by utilizing a photoetching process, respectively locating at two sides of a device, then evaporating a Ti/Al/Ni/Au metal or alloy layer by utilizing an evaporation process, and contacting the layer with surface graphene to form ohmic contact electrodes (an S electrode and a G electrode);
(5) utilizing photoetching and evaporation process to evaporate a metal Ni/Au layer on the upper surface of the ion-implanted semiconductor region, wherein the metal Ni/Au layer is in Schottky contact with the lower semiconductor region to form a G electrode;
(6) using photoetching technology, adopting chemical gas phase deposition PECVD method to grow a layer of SiO on the surface2The passivation layer protects the layer, all areas except S, D and the G electrode are covered.
Through the technical scheme, compared with the prior art, the invention has the following beneficial effects:
it can be known from the brief description of the background art that the traditional high electron mobility transistor limits the transmission rate of carriers due to the problems of the material itself, the higher background carrier concentration is determined by the complex growth characteristics of the material, so that the leakage channel is greatly increased, the complexity and instability of the process are increased by doping the deep acceptor impurities, and the control is difficult; in addition, high bandgap materials exhibit low thermal conductivity, and the more complex the structure, the more difficult and costly the fabrication becomes.
The graphene layer with extremely excellent conductivity is used as a conductive channel, and is used as a direct current flow channel of the source electrode S and the drain electrode D, the conventional 2DEG is replaced, the migration rate of electrons can be greatly improved, the more advanced frequency characteristic is realized, and the manufacturing process can be simplified by directly generating the graphene layer on SiC.
In the invention, because the SiC material is carbonized at high temperature, silicon atoms on the surface can evaporate and escape when the silicon carbide is heated to more than 1100 ℃ to form a graphene layer, and the graphene conducting layer material can be directly and conveniently obtained; the conduction of an S pole and a D pole is controlled by adopting a Schottky structure with metal and semiconductor contact as a G grid electrode, a body substrate SiC is a semiconductor formed by ion implantation, an ion implantation area is respectively a light doping area and a heavy doping area, the light doping area is positioned in the middle, the heavy doping areas are positioned at two ends, the light doping area is mainly used for easily forming a depletion area, the heavy doping areas are positioned at two ends and are in contact with a graphene layer conveniently, and ohmic contact is formed to reduce voltage; a Schottky structure is formed above the lightly doped region and metal of the coating, a Schottky depletion layer ranges within the width of the lightly doped region, penetrates through the ion injection region and extends into the substrate SiC region, the Schottky region is completely depleted under zero bias, channels of an S pole and a D pole are blocked by the depletion region and cannot be conducted, so that the enhanced high-electron-mobility transistor is formed, the Schottky barrier region becomes thin under certain forward voltage of a grid, and the S electrode and the D electrode are conducted through the doped SiC semiconductor region under the voltage; the traditional process of etching a large number of table tops deep into materials is not needed, the process of designing and manufacturing the transistor is simplified, the carrier migration rate is greatly improved, the on-resistance is reduced, the working frequency is improved, the heat dissipation effect is increased, and high-performance application is realized.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a structural view of a HEMT of a silicon carbide-based graphene material according to the present invention;
FIG. 2 is a diagram of a Schottky barrier layer under gate 0 bias;
FIG. 3 is a diagram of a Schottky barrier layer under gate forward bias;
fig. 4 is a structural diagram of a doped region of an ion implantation region.
Wherein, in the figure:
1-a substrate; 2-a graphene layer; 3-lightly doped region; 4-heavily doped region; 5-S electrode; a 6-D electrode; 7-G electrode; 8-protective layer.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example 1
A HEMT chip of silicon carbide-based graphene material, comprising: the graphene substrate comprises a substrate 1, a graphene layer 2, an ion implantation region, an S/D electrode region, a G electrode 7 and a protective layer 8;
the graphene layer 2 is positioned above the substrate 1 and is connected with the substrate 1;
the ion implantation region is positioned in the center of the inside of the substrate 1 and penetrates upwards to the upper surface of the graphene layer 2;
the S/D electrode area is positioned above the graphene layer 2 and is connected with the graphene layer 2;
the G electrode 7 is positioned above the ion implantation area and is connected with the ion implantation area;
the protective layer 8 is provided over the graphene layer 2 and the ion implantation region outside the S/D electrode region and the G electrode.
The ion implantation region comprises a heavily doped region 3 and lightly doped regions 4 positioned on two sides of the heavily doped region; the G electrode 7 is positioned above the heavily doped region 3 and is connected with the heavily doped region 3;
the S/D electrode area comprises an S electrode 5 and a D electrode 6, and the S electrode 5 and the D electrode 6 are respectively positioned on two sides above the graphene layer 2 and are connected with the graphene layer 2;
the substrate 2 is made of SiC;
the ion implantation area is an N-type semiconductor ion implantation area;
the S electrode and the D electrode are both metal alloy layers combined by Ti/Al/Ni/Au, and the thicknesses of the layers are respectively Ti20 nm; al150 nm; ni80 nm; au100 nm.
The G electrode is a metal alloy layer composed of Ni/Au, and the thicknesses of the layers are respectively
The lightly doped region has a doping concentration of 1012cm-3(ii) a The heavily doped region has a doping concentration of 1019cm-3。
Example 2
A HEMT chip of silicon carbide-based graphene material, comprising: the graphene substrate comprises a substrate 1, a graphene layer 2, an ion implantation region, an S/D electrode region, a G electrode 7 and a protective layer 8;
the graphene layer 2 is positioned above the substrate 1 and is connected with the substrate 1;
the ion implantation region is positioned in the center of the inside of the substrate 1 and penetrates upwards to the upper surface of the graphene layer 2;
the S/D electrode area is positioned above the graphene layer 2 and is connected with the graphene layer 2;
the G electrode 7 is positioned above the ion implantation area and is connected with the ion implantation area;
the protective layer 8 is provided over the graphene layer 2 and the ion implantation region outside the S/D electrode region and the G electrode.
The ion implantation region comprises a heavily doped region 3 and lightly doped regions 4 positioned on two sides of the heavily doped region; the G electrode 7 is positioned above the heavily doped region 3 and is connected with the heavily doped region 3;
the S/D electrode area comprises an S electrode 5 and a D electrode 6, and the S electrode 5 and the D electrode 6 are respectively positioned on two sides above the graphene layer 2 and are connected with the graphene layer 2;
the substrate 2 is made of SiC;
the ion implantation area is a P-type semiconductor ion implantation area;
the S electrode and the D electrode are both metal alloy layers combined by Ti/Al/Ni/Au, and the thicknesses of the layers are respectively Ti50 nm; al200 nm; ni120 nm; au150 nm.
The G electrode is a metal alloy layer composed of Ni/Au, and the thicknesses of the layers are respectively
The lightly doped region has a doping concentration of 1015cm-3(ii) a The heavily doped region has a doping concentration of 1022cm-3。
Example 3
A HEMT chip of silicon carbide-based graphene material, comprising: the graphene substrate comprises a substrate 1, a graphene layer 2, an ion implantation region, an S/D electrode region, a G electrode 7 and a protective layer 8;
the graphene layer 2 is positioned above the substrate 1 and is connected with the substrate 1;
the ion implantation region is positioned in the center of the inside of the substrate 1 and penetrates upwards to the upper surface of the graphene layer 2;
the S/D electrode area is positioned above the graphene layer 2 and is connected with the graphene layer 2;
the G electrode 7 is positioned above the ion implantation area and is connected with the ion implantation area;
the protective layer 8 is provided over the graphene layer 2 and the ion implantation region outside the S/D electrode region and the G electrode.
The ion implantation region comprises a heavily doped region 3 and lightly doped regions 4 positioned on two sides of the heavily doped region; the G electrode 7 is positioned above the heavily doped region 3 and is connected with the heavily doped region 3;
the S/D electrode area comprises an S electrode 5 and a D electrode 6, and the S electrode 5 and the D electrode 6 are respectively positioned on two sides above the graphene layer 2 and are connected with the graphene layer 2;
the substrate 2 is made of SiC;
the ion implantation area is a P-type semiconductor ion implantation area;
the S electrode and the D electrode are both metal alloy layers combined by Ti/Al/Ni/Au, and the thicknesses of the layers are respectively Ti35 nm; al175 nm; ni100 nm; au125 nm.
The G electrode is a metal alloy layer composed of Ni/Au, and the thicknesses of the layers are respectively
The lightly doped region has a doping concentration of 1014cm-3(ii) a The heavily doped region has a doping concentration of 1020cm-3。
Example 4
The method for preparing an HEMT chip of the silicon carbide based graphene material according to any one of embodiments 1 to 3 includes the steps of:
1. respectively carrying out ultrasonic cleaning on the SiC substrate in acetone and ethanol or other organic solvents for 5min, then cleaning the SiC substrate with deionized water, and drying the SiC substrate in an oven;
2. coating a layer of photoresist on the surface of the photoresist, forming an ion implantation area pattern by utilizing a photoetching plate with the ion implantation area pattern through a photoetching MESA process, then removing the photoresist on the ion implantation area through developing, cleaning, removing the photoresist on the ion implantation area, exposing the ion implantation area, and taking the photoresist in other areas as a shield to prevent ions from being implanted into the area;
3. implanting aluminum ions or boron ions into the upper surface of an ion implantation area which is not covered by the photoresist by utilizing an ion implantation technology, forming a P-type semiconductor ion implantation area in the area of the substrate, wherein the depth of the ion implantation area is 30nm, and forming a lightly doped area which is positioned in the middle of the ion implantation area;
4. forming an ion implantation area pattern by using a photoetching plate with the ion implantation area pattern through a photoetching MESA process, using photoresist as a shield, and implanting aluminum ions or boron ions into the upper surface of the ion implantation area which is not covered by the photoresist by using an ion implantation technology, wherein the depth of the ion implantation area is 25nm to form a heavily doped area which is positioned at two ends of the ion implantation area;
5. then removing the photoresist in the surface protection area during ion implantation, and utilizing the photoetching process to plate SiO in the process of no need of SiO2Coating photoresist on the area, and then coating a layer of 5nm SiO by PECVD (plasma enhanced chemical vapor deposition) coating process2Protective layer (SiO)2The area range of the protective layer is slightly smaller than that of the injection region);
6. then removing the photoresistance, heating the substrate to 1400 ℃, and evaporating and escaping silicon atoms on the surface to form a graphene layer as the SiC material is carbonized at high temperature;
7. removal of SiO by HF acid2The layer, the surface graphene layer formed at high temperature is connected with the edge of the ion-implanted doping layer and slightly covers the boundaries of two ends of the doping region;
8. manufacturing S and D electrodes by utilizing a photoetching process, respectively locating at two sides of the device, then evaporating a layer of Ti/Al/Ni/Au metal or alloy by utilizing an evaporation process, and contacting with surface graphene to form ohmic contact electrodes;
9. then, a photoetching plate with a G electrode pattern is combined with a photoetching MESA process to manufacture a G electrode pattern area on the doped area;
10. then, respectively evaporating metal Ni/Au by adopting an electron beam evaporation process method, and stripping the metal on other evaporation area layers by using a metal stripping technology to leave a G area metal to form a gate electrode G;
11. then combining with MESA process, growing a layer of SiO on the surface by adopting chemical vapor deposition PECVD2And a passivation layer protection layer covering all regions except the three electrode regions.
Example 5
The method for preparing an HEMT chip of the silicon carbide based graphene material according to any one of embodiments 1 to 3 includes the steps of:
1. respectively carrying out ultrasonic cleaning on the SiC substrate in acetone and ethanol or other organic solvents for 3min, then cleaning the SiC substrate with deionized water, and drying the SiC substrate in an oven;
2. coating a layer of photoresist on the surface of the photoresist, forming an ion implantation area pattern by utilizing a photoetching plate with the ion implantation area pattern through a photoetching MESA process, then removing the photoresist on the ion implantation area through developing, cleaning, removing the photoresist on the ion implantation area, exposing the ion implantation area, and taking the photoresist in other areas as a shield to prevent ions from being implanted into the area;
3. implanting nitrogen ions or phosphorus ions into the upper surface of an ion implantation area which is not covered by the photoresist by utilizing an ion implantation technology, forming an N-type semiconductor ion implantation area in the area of the substrate, wherein the depth of the ion implantation area is 10nm, and forming a lightly doped area which is positioned in the middle of the ion implantation area;
4. forming an ion implantation area pattern by using a photoetching plate with the ion implantation area pattern through a photoetching MESA process, using photoresist as a shield, and implanting nitrogen ions or phosphorus ions into the upper surface of the ion implantation area which is not covered by the photoresist by using an ion implantation technology, wherein the depth of the ion implantation area is 5nm to form a heavily doped area which is positioned at two ends of the ion implantation area;
5. then removing the ion implantationThe photoresist in the time-input surface protection area is not required to be coated with SiO by utilizing the photoetching process2Coating photoresist on the area, and then coating a layer of SiO 2nm by using PECVD (plasma enhanced chemical vapor deposition) coating process2Protective layer (SiO)2The area range of the protective layer is slightly smaller than that of the injection region);
6. then removing the photoresistance, heating the substrate to 1200 ℃, and evaporating and escaping silicon atoms on the surface to form a graphene layer as the SiC material is carbonized at high temperature;
7. removal of SiO by HF acid2The layer, the surface graphene layer formed at high temperature is connected with the edge of the ion-implanted doping layer and slightly covers the boundaries of two ends of the doping region;
8. manufacturing S and D electrodes by utilizing a photoetching process, respectively locating at two sides of the device, then evaporating a layer of Ti/Al/Ni/Au metal or alloy by utilizing an evaporation process, and contacting with surface graphene to form ohmic contact electrodes;
9. then, a photoetching plate with a G electrode pattern is combined with a photoetching MESA process to manufacture a G electrode pattern area on the doped area;
10. then, respectively evaporating metal Ni/Au by adopting an electron beam evaporation process method, and stripping the metal on other evaporation area layers by using a metal stripping technology to leave a G area metal to form a gate electrode G;
11. then combining with MESA process, growing a layer of SiO on the surface by adopting chemical vapor deposition PECVD2And a passivation layer protection layer covering all regions except the three electrode regions.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A silicon carbide based graphene materials HEMT chip, comprising: the device comprises a substrate, a graphene layer, an ion implantation region, an S/D electrode region and a G electrode;
the graphene layer is positioned above the substrate and is connected with the substrate;
the ion implantation region is positioned in the center of the inner part of the substrate and penetrates upwards to the upper surface of the graphene layer;
the S/D electrode region is positioned above the graphene layer and is connected with the graphene layer;
the G electrode is positioned above the ion implantation area and is connected with the ion implantation area.
2. The HEMT chip of claim 1, further comprising: a protective layer;
the protective layer is arranged above the graphene layer and the ion injection region except the S/D electrode region and the G electrode.
3. The HEMT chip of claim 2, wherein said ion implanted region comprises a heavily doped region and lightly doped regions on both sides thereof; the G electrode is positioned above the heavily doped region and is connected with the heavily doped region.
4. The HEMT chip made of silicon carbide-based graphene material according to claim 3, wherein the S/D electrode region comprises an S electrode and a D electrode, and the S electrode and the D electrode are respectively located on two sides above the graphene layer and are connected with the graphene layer.
5. The HEMT chip made of silicon carbide-based graphene material according to claim 4, wherein the substrate is SiC.
6. The HEMT chip made of silicon carbide-based graphene material according to claim 5, wherein the ion implantation region is an N-type semiconductor ion implantation region or a P-type semiconductor ion implantation region.
7. The HEMT chip made of silicon carbide-based graphene material according to claim 6, wherein the S electrode and the D electrode are both metal alloy layers composed of Ti/Al/Ni/Au, and the thicknesses of the layers are respectively Ti20-50 nm; al is 150-200 nm; ni80-120 nm; and Au is 100-150 nm.
8. The HEMT chip of silicon carbide-based graphene material according to claim 7, wherein the G electrode is a metal alloy layer composed of Ni/Au, and each layer has a thickness of Ni/Au
9. The HEMT chip made of silicon carbide-based graphene material according to claim 8, wherein the doping concentration of the lightly doped region is 1012cm-3-1015cm-3(ii) a The heavily doped region has a doping concentration of 1019cm-3-1022cm-3。
10. The method for preparing an HEMT chip of silicon carbide-based graphene material according to claim 9, comprising the steps of:
(1) removing photoresist in an injection region on a substrate through a photoetching process, and making an opening for ion injection in other regions under the protection of the photoresist;
(2) implanting the required implantation doping elements into the open hole region by an ion implantation process to form an ion implantation region;
(3) removing the photoresist in the surface protection area during ion implantation, and plating a layer of SiO on the ion implantation area by using the photoetching process2Protective layer, other region not evaporated with SiO2A layer;
(4) heating the substrate to 1200-1400 ℃, forming a graphene layer on the surface of the substrate, and removing SiO by HF acid2A layer;
(5) manufacturing graphs of an S electrode and a D electrode by a photoetching process, and then evaporating metal alloy layers on two sides above a graphene layer by an evaporation process to form the S electrode and the D electrode;
(6) in the same step (5), a metal alloy layer is evaporated above the ion implantation area through photoetching and evaporation processes to form a G electrode;
(7) and plating a protective layer on the graphene layer except the S electrode, the D electrode and the G electrode and above the ion injection region through photoetching and evaporation technology to obtain the HEMT chip.
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| US20150060881A1 (en) * | 2011-04-13 | 2015-03-05 | Friedrich-Alexander-Universitat Erlangen- Nurnberg | Semiconductor component |
| KR20170094814A (en) * | 2016-02-11 | 2017-08-22 | 한국전자통신연구원 | Method of manufacturing semiconductor device |
| CN107591444A (en) * | 2016-07-08 | 2018-01-16 | 中国科学院苏州纳米技术与纳米仿生研究所 | Enhancement transistor and preparation method thereof |
| US20190035907A1 (en) * | 2016-02-12 | 2019-01-31 | Centre National De La Recherche Scientifique - Cnrs | Method for obtaining a graphene-based fet, in particular a memory fet, equipped with an embedded dielectric element made by fluorination |
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| US20150060881A1 (en) * | 2011-04-13 | 2015-03-05 | Friedrich-Alexander-Universitat Erlangen- Nurnberg | Semiconductor component |
| KR20170094814A (en) * | 2016-02-11 | 2017-08-22 | 한국전자통신연구원 | Method of manufacturing semiconductor device |
| US20190035907A1 (en) * | 2016-02-12 | 2019-01-31 | Centre National De La Recherche Scientifique - Cnrs | Method for obtaining a graphene-based fet, in particular a memory fet, equipped with an embedded dielectric element made by fluorination |
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