CN111129166A - Gallium oxide-based semiconductor structure and preparation method thereof - Google Patents
Gallium oxide-based semiconductor structure and preparation method thereof Download PDFInfo
- Publication number
- CN111129166A CN111129166A CN201911283509.0A CN201911283509A CN111129166A CN 111129166 A CN111129166 A CN 111129166A CN 201911283509 A CN201911283509 A CN 201911283509A CN 111129166 A CN111129166 A CN 111129166A
- Authority
- CN
- China
- Prior art keywords
- gallium oxide
- barrier schottky
- low
- epitaxial layer
- channels
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 title claims abstract description 135
- 229910001195 gallium oxide Inorganic materials 0.000 title claims abstract description 135
- 239000004065 semiconductor Substances 0.000 title claims abstract description 55
- 238000002360 preparation method Methods 0.000 title abstract description 15
- 230000004888 barrier function Effects 0.000 claims abstract description 111
- 239000010410 layer Substances 0.000 claims description 103
- 238000000034 method Methods 0.000 claims description 21
- 229910052751 metal Inorganic materials 0.000 claims description 14
- 239000002184 metal Substances 0.000 claims description 14
- 239000000758 substrate Substances 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 9
- 229910044991 metal oxide Inorganic materials 0.000 claims description 9
- 150000004706 metal oxides Chemical class 0.000 claims description 9
- 239000011241 protective layer Substances 0.000 claims description 9
- 238000009616 inductively coupled plasma Methods 0.000 claims description 7
- 229910052737 gold Inorganic materials 0.000 claims description 6
- 238000001312 dry etching Methods 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 4
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 4
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 229910052750 molybdenum Inorganic materials 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 229910052697 platinum Inorganic materials 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 claims description 2
- 229910052709 silver Inorganic materials 0.000 claims description 2
- 229910052721 tungsten Inorganic materials 0.000 claims description 2
- 230000000694 effects Effects 0.000 abstract description 10
- 238000005036 potential barrier Methods 0.000 abstract 1
- 239000010931 gold Substances 0.000 description 9
- 230000008569 process Effects 0.000 description 6
- 239000000463 material Substances 0.000 description 5
- 238000002161 passivation Methods 0.000 description 5
- 239000010936 titanium Substances 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 3
- QZQVBEXLDFYHSR-UHFFFAOYSA-N gallium(III) oxide Inorganic materials O=[Ga]O[Ga]=O QZQVBEXLDFYHSR-UHFFFAOYSA-N 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 229910002842 PtOx Inorganic materials 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910003460 diamond Inorganic materials 0.000 description 2
- 239000010432 diamond Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- MUMZUERVLWJKNR-UHFFFAOYSA-N oxoplatinum Chemical compound [Pt]=O MUMZUERVLWJKNR-UHFFFAOYSA-N 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Substances [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 229910003446 platinum oxide Inorganic materials 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 229910015844 BCl3 Inorganic materials 0.000 description 1
- 229910003298 Ni-Ni Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D8/00—Diodes
- H10D8/60—Schottky-barrier diodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D8/00—Diodes
- H10D8/01—Manufacture or treatment
- H10D8/051—Manufacture or treatment of Schottky diodes
Landscapes
- Electrodes Of Semiconductors (AREA)
Abstract
本发明公开了一种氧化镓基半导体结构及其制备方法，该氧化镓基半导体结构包括：氧化镓基外延层，具有多个沟道，该多个沟道形成于该氧化镓基外延层上表面且相互间隔第一距离；多个低势垒肖特基电极，形成于所述多个沟道之间的氧化镓基外延层上表面；以及高势垒肖特基电极，形成于所述氧化镓基外延层上表面，且覆盖所述多个沟道及所述多个低势垒肖特基电极。该氧化镓基半导体结构同时结合了高、低势垒的优势，具有较低的开启电压的同时可以维持较小的反向漏电流的优势，能够保证开态电阻不会有明显增大，甚至会有降低的效果，能够使得双势垒肖特基能够有效应的用于高温领域。
The invention discloses a gallium oxide-based semiconductor structure and a preparation method thereof. The gallium oxide-based semiconductor structure comprises: a gallium oxide-based epitaxial layer with a plurality of channels, and the plurality of channels are formed on the gallium-oxide-based epitaxial layer surfaces and are spaced apart from each other by a first distance; a plurality of low barrier Schottky electrodes formed on the upper surface of the gallium oxide-based epitaxial layer between the plurality of channels; and a high barrier Schottky electrode formed on the The upper surface of the gallium oxide-based epitaxial layer covers the plurality of channels and the plurality of low-barrier Schottky electrodes. The gallium oxide-based semiconductor structure combines the advantages of high and low potential barriers at the same time, and has the advantage of low turn-on voltage while maintaining a small reverse leakage current, which can ensure that the on-state resistance will not increase significantly, even There will be a lowering effect, which enables the dual-barrier Schottky to be effectively used in high temperature fields.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a gallium oxide-based semiconductor structure and a preparation method thereof.
Background
Gallium oxide (Ga)2O3) As a new ultra-wide forbidden band semiconductor material which is very popular in the current research field, the ultra-wide forbidden band semiconductor material has the advantages of ultra-wide forbidden band width (4.8eV), large breakdown field intensity (8MV/cm), very good thermal stability and chemical stability, forbidden band width and breakdown field intensity which are second to diamond (which is an excellent substitute material for diamond in high-power and optical semiconductor devices), simple preparation method and the like; in addition, the gallium oxide power device has lower on-resistance, lower power consumption and higher high temperature resistance under the same voltage withstanding condition as GaN and SiC, and can greatly save the electric energy loss when the high-voltage device works. Therefore, with the progress of research, the gallium oxide-based semiconductor technology has been rapidly developed and is increasingly applied to practical semiconductor devices, such as various diodes, transistors, photodetectors and the like, which are prepared based on gallium oxide materials. However, the existing gallium oxide-based semiconductor device still has many defects, and specifically, the schottky diode semiconductor device can be described as an example:
schottky Barrier Diode (SBD) is widely used in circuit as a rectifying device. An ideal SBD should have zero turn-on voltage drop and zero reverse leakage current. However, in practical applications, the turn-on voltage drop and the reverse leakage current of the SBD are directly related to the SBH. The reverse leakage current of the Schottky diode can be effectively reduced by selecting a higher SBH (Schottky barrier junction, SBH for short, refers to the barrier height of a metal-semiconductor contact interface), but the higher forward turn-on voltage can be caused; while selecting a lower SBH results in a lower turn-on voltage but results in a higher reverse leakage current. Higher turn-on voltage and reverse leakage current mean more energy is lost, so a balance point is needed between reducing turn-on voltage and reducing reverse leakage current.
To solve the SBD heightThe problem of energy loss caused by turn-on voltage and high leakage current is that the prior art proposes an SBD of a trench MOS structure (MOS for short, referred to as a metal-oxide-semiconductor structure): peak electric field at diode reverse bias using trench MOS structure from metal-Ga2O3The interface is led to the bottom of the trench, so that reverse leakage current can be effectively reduced and breakdown voltage can be improved. But the area of Schottky contact is reduced while a groove MOS structure is introduced, so that the on-state resistance is sacrificed; in addition, because the depletion effect of the trench MOS structure is not obvious, the effect of reducing the leakage current is very limited; finally, according to the thermal field emission model, the reverse leakage current of the ordinary schottky diode is obviously degraded at high temperature.
Disclosure of Invention
Technical problem to be solved
The invention discloses a gallium oxide-based semiconductor structure and a preparation method thereof, aiming at solving the problem of energy loss caused by high opening voltage and high leakage current of a semiconductor device in the prior art and simultaneously not sacrificing good performances related to on-resistance, reverse leakage current and the like in the original device.
(II) technical scheme
One aspect of the present invention discloses a gallium oxide-based semiconductor structure, the semiconductor structure comprising: the gallium oxide-based epitaxial layer is provided with a plurality of channels, and the plurality of channels are formed on the upper surface of the gallium oxide-based epitaxial layer and are separated from each other by a first distance; a plurality of low barrier Schottky electrodes formed on the upper surface of the gallium oxide-based epitaxial layer between the plurality of channels; the high-barrier Schottky electrode is formed on the upper surface of the gallium oxide-based epitaxial layer and covers the plurality of channels and the plurality of low-barrier Schottky electrodes; the channels are sunken in the inner surface of the gallium oxide-based epitaxial layer to serve as high-barrier contact surfaces in contact with the high-barrier Schottky electrodes, and the upper surface of the gallium oxide-based epitaxial layer between every two adjacent channels serves as a low-barrier contact surface in contact with the low-barrier Schottky electrodes.
As an embodiment of the present invention, the high barrier schottky electrode is a metal oxide electrode; and the low barrier Schottky electrode is a metal electrode, and the metal is Ni, Au, Pt, Cu, Mo, Ag or W.
As an embodiment of the invention, the depth of the channel is h, and h is more than or equal to 1 mu m and less than or equal to 3 mu m; the width of the channel is k, and k is more than or equal to 1 mu m and less than or equal to 5 mu m; the first distance is d, and d is more than or equal to 1 mu m and less than or equal to 5 mu m.
As an embodiment of the present invention, a first protection layer is further included between the low barrier schottky electrode and the high barrier schottky electrode.
As an embodiment of the present invention, the semiconductor structure further includes: a gallium oxide-based substrate layer positioned below the gallium oxide-based epitaxial layer, and an ohmic electrode positioned below the gallium oxide-based substrate layer.
As an embodiment of the present invention, the outer surface of the ohmic electrode is covered with a second protective layer.
Another aspect of the present invention discloses a method for preparing a gallium oxide-based semiconductor structure, which is used to prepare the above gallium oxide-based semiconductor structure, and includes: forming a plurality of low-barrier Schottky electrodes on the upper surface of the gallium oxide-based epitaxial layer at intervals of a first distance; etching the upper surface of the gallium oxide-based epitaxial layer by taking the plurality of low-barrier Schottky electrodes as masks to form a plurality of channels, wherein the upper surface of the gallium oxide-based epitaxial layer between every two adjacent channels is used as a low-barrier contact surface which is in contact with the low-barrier Schottky electrodes; and forming a high barrier Schottky electrode on the upper surface of the gallium oxide-based epitaxial layer on which the plurality of channels are formed, the high barrier Schottky electrode simultaneously covering the plurality of channels and the plurality of low barrier Schottky electrodes, and an inner surface of the channel serving as a high barrier contact surface which is in contact with the high barrier Schottky electrode.
As an embodiment of the present invention, a lift-off method is used to form a plurality of low barrier schottky electrodes on the upper surface of the gallium oxide-based epitaxial layer at a first distance.
As an embodiment of the present invention, etching the upper surface of the gallium oxide-based epitaxial layer to form a plurality of channels by using a plurality of low-barrier schottky electrodes as a mask includes: and (3) taking the low-barrier Schottky electrode as a mask, and carrying out dry etching on the gallium oxide-based epitaxial layer by utilizing ICP (inductively coupled plasma) to recess the upper surface of the gallium oxide-based epitaxial layer to form a plurality of channels.
In one embodiment of the present invention, a high barrier schottky electrode is formed on an upper surface of a gallium oxide-based epitaxial layer on which a plurality of channels are formed, the high barrier schottky electrode including: and forming a high-barrier Schottky electrode which covers the low-barrier Schottky electrodes simultaneously on the inner surfaces of the channels by adopting a magnetron sputtering method or a pulse laser deposition method.
(III) advantageous effects
The invention discloses a gallium oxide-based semiconductor structure, which is characterized in that a plurality of channels are arranged on a gallium oxide-based epitaxial layer, low-barrier Schottky is formed between adjacent channels, a high-barrier Schottky electrode is directly formed on the basis of the structure, covers the low-barrier Schottky, and forms the high-barrier Schottky on the inner surface of the channel, so that a high-barrier Schottky oxide-based semiconductor structure and a low-barrier Schottky oxide-based semiconductor structure can be formed. In addition, the Schottky contact area can be increased by the high-low double-barrier contact, so that the on-state resistance can be ensured not to be obviously increased or even to be reduced. The metal oxide schottky has a large built-in potential, and can effectively exhaust and pinch off the reverse leakage of the low SBH schottky. The metal oxide schottky diode has relatively good working characteristics at high temperature, so that the double barrier schottky diode can be effectively used in the high-temperature field.
The invention also discloses a preparation method of the gallium oxide-based semiconductor structure, which is used for preparing the gallium oxide-based semiconductor structure with the high-low double-barrier Schottky structure, wherein the low-barrier Schottky metal deposited by lift-off ensures that the structure has lower turn-on voltage and good on-state resistance. The preparation process is simple, the preparation cost is low, and the industrial mass production is favorably realized.
Drawings
FIG. 1 is a schematic diagram of the composition of a gallium oxide-based semiconductor structure in an embodiment of the present invention;
FIG. 2 is a graph comparing I-V simulation curves of a high-low double barrier Schottky structure and a conventional SBD structure in an embodiment of the present invention;
FIG. 3 is a schematic flow chart of a method for fabricating a gallium oxide-based semiconductor structure according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of each preparation stage of the gallium oxide-based semiconductor structure in the embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to specific embodiments and the accompanying drawings.
One aspect of the present invention discloses a gallium oxide-based semiconductor structure, as shown in fig. 1, including: a gallium oxide-based epitaxial layer 130 having a plurality of channels 131, the plurality of channels 131 being formed on the upper surface of the gallium oxide-based epitaxial layer 130 and being spaced apart from each other by a first distance d; a plurality of low barrier schottky electrodes 120 formed on the upper surface of the gallium oxide-based epitaxial layer 130 between the plurality of channels 131; and a high barrier schottky electrode 110 formed on the upper surface of the gallium oxide-based epitaxial layer 130 and covering the plurality of channels 131 and the plurality of low barrier schottky electrodes 120; the channels 131 are recessed in the inner surface of the gallium oxide-based epitaxial layer 130 to serve as high-barrier contact surfaces contacting with the high-barrier schottky electrode 110, and the upper surface of the gallium oxide-based epitaxial layer 130 between two adjacent channels 131 serves as a low-barrier contact surface contacting with the low-barrier schottky electrode 120.
Specifically, as an embodiment of the present invention, a plurality of trenches 131 formed at intervals of the first distance recess (which may be implemented by a thin film etching process) are disposed on the upper surface of the gallium oxide-based epitaxial layer 130, and specifically, refer to the dashed line frame shown in fig. 1. It should be noted that the first distance is d, and d may be a variable of the distance value, that is, d is not a fixed distance value. In other words, the first distance d between the first adjacent two channels 131 and the first distance d' between the second adjacent two channels 131 may not be uniform. As shown in fig. 1, while the trenches 131 are formed, the mesas 132 having a width dimension of the first distance d are simultaneously formed between the adjacent trenches 131. It should be noted that, since fig. 1 is a transverse partial cross-sectional view of the gallium oxide-based semiconductor structure, only 3 mesas 132 and 4 trenches 131 spaced from each other by the mesas are shown, the first distance d and the width dimension mentioned herein can be understood as the dimension that can be shown by the partial cross-sectional view.
As an embodiment of the present invention, the mesa 132 of the gallium oxide-based epitaxial layer 130 is covered with a low barrier schottky electrode 120, the low barrier schottky electrode 120 is formed only on the upper surface of the mesa 132, and the low barrier schottky electrode 120 is in contact with only the upper surface of the mesa 132 to form the low barrier schottky contact at the interface therebetween. In addition, on the gallium oxide-based epitaxial layer 130 on which the low barrier schottky electrode 120 is formed, a layer of high barrier schottky electrode 110 is further covered, the high barrier schottky electrode 110 is mainly formed on the inner surface of the channel 131 (as shown by the dotted frame in fig. 1), and the high barrier schottky electrode 110 is in contact with the inner surface of the channel 131 to form the high barrier schottky contact on the interface therebetween. In addition, the high barrier schottky electrode 110 has a thickness much greater than the sum of the depth of the channel 131 and the thickness of the low barrier schottky electrode 120 and masks the low barrier schottky electrode 120.
In summary, the gallium oxide-based semiconductor structure of the present invention realizes high-low double barrier schottky contact, and increases schottky contact area, so that it can be ensured that on-state resistance is not increased significantly. The technical effects corresponding to the technical features are explained by taking a high-low double-barrier schottky diode which can be applied to the invention as an example: when the high-low double barrier schottky diode is forward biased, the low barrier schottky is turned on at a lower voltage, and therefore the turn-on voltage of the structure will be substantially the same as the low barrier schottky diode. When the turn-on voltage of the high barrier is reached, the high and low double barrier Schottky are simultaneously conducted, so that the on-state resistance is not obviously reduced. When the high-low double-barrier Schottky diode is reversely biased, the reverse leakage of the low-barrier Schottky is pinched off due to the depletion effect of the channel in the high-barrier Schottky. The reverse leakage of the high and low double barrier schottky diode will be an order of magnitude with the high barrier schottky diode.
As an embodiment of the invention, as shown in FIG. 1, the depth of the trench is h, and h is greater than or equal to 1 μm and less than or equal to 3 μm; the width of the channel is k, and k is more than or equal to 1 mu m and less than or equal to 5 mu m; the first distance is d, and d is more than or equal to 1 mu m and less than or equal to 5 mu m. The h, k and d can form a structural size proportional relationship according to the size range. Specifically, the size of the structure can be correspondingly adjusted along with the change of the doping concentration of the gallium oxide-based epitaxial layer. Because the double-barrier Schottky structure is introduced by arranging the channel in the single structure, the contact area between the high and low Schottky electrodes and the gallium oxide-based epitaxial layer is increased, and the interface junction resistance is reduced, so that when the Schottky diode is applied to a Schottky diode, the Schottky diode device with the high and low double barriers can have smaller on-state resistance. As shown in FIG. 2, when the depth h and the width k of the trench are set to 2 μm, the doping concentration of the gallium oxide-based epitaxial layer is 3X 1016cm-3When the voltage of the high-low double-barrier Schottky diode device is fully opened, VanodeWith > 2V, the slope increases significantly. Therefore, the depth h and the width k of the groove corresponding to the doping concentration of the gallium oxide-based epitaxial layer can be controlled, so that the effect of increasing the contact area of the Schottky electrode and ensuring that the on-state resistance cannot be increased can be achieved, and the effect of reducing the on-state resistance can be even achieved.
As an embodiment of the present invention, the high barrier schottky electrode is a metal oxide electrode, such as platinum oxide PtOx; the metal oxide schottky has a large built-in potential, and can effectively exhaust and pinch off the reverse leakage of the low SBH (SBH: the abbreviation of schottky barrier height refers to the barrier height of a metal-semiconductor contact interface) schottky. Meanwhile, the high-barrier Schottky structure is prepared from metal oxide, so that relatively high Schottky Barrier Height (SBH) can be formed in a stepping mode (the SBH can reach more than 2.0 eV), and the high-temperature working characteristic can be very good, so that the double-barrier Schottky gallium oxide semiconductor structure has a good application prospect at high temperature.
As an embodiment of the present invention, the low barrier schottky electrode is a metal electrode, which can better realize low barrier schottky contact with the gallium oxide-based epitaxial layer, and has a cross-bottom Schottky Barrier Height (SBH), and specifically, the metal electrode may adopt Ni, Au, Pt, Cu, Mo, Ag, W, or the like.
As an embodiment of the present invention, as shown in fig. 1, a first passivation layer 160 is further included between the low-barrier schottky electrode 120 and the high-barrier schottky electrode 110, and the first passivation layer is used to isolate the low-barrier schottky electrode 120 from the high-barrier schottky electrode 110, so that the low-barrier schottky electrode 120 and the high-barrier schottky electrode 110 cannot be in direct contact with each other, and at the same time, the low-barrier schottky electrode 120 mainly made of a metal material is protected from being oxidized on the surface to become a metal oxide during the preparation process of the gallium oxide based semiconductor structure. Therefore, the first protective layer 160 completely covers the upper surface and the side surfaces of the low barrier schottky electrode 120, so that the low barrier schottky electrode 120 contacts the upper surfaces of the mesas 132 of the gallium oxide based epitaxial layer 130 only through the lower surface to form the low barrier schottky. Therefore, the width of the first passivation layer is equal to the first distance d, which is a passivation layer covering the outer surface of the low barrier schottky electrode 120. Generally, the first passivation layer can be made of gold Au, which is a stable metal.
As an embodiment of the present invention, as shown in fig. 1, the semiconductor structure further includes: the gallium oxide-based epitaxial layer is located below the gallium oxide-based epitaxial layer 130, the gallium oxide-based substrate layer 140 is configured to provide a substrate function for the gallium oxide-based semiconductor structure, and the ohmic electrode 150 is located below the gallium oxide-based substrate layer 140 and is configured to serve as a back electrode of the gallium oxide-based semiconductor structure and form ohmic contact with the lower surface of the gallium oxide-based substrate layer, and specifically, the ohmic electrode 150 may be made of metal, such as Ti. As an embodiment of the present invention, the outer surface of the ohmic electrode 150 is covered with a second protection layer 170, as shown in fig. 1, to protect the ohmic electrode 150, which is mainly made of a metal material, from oxidation reaction on the surface to become a metal oxide in the preparation process of the gallium oxide-based semiconductor structure. Therefore, the second protective layer 170 completely covers the lower surface and the side surface of the ohmic electrode 150, so that the ohmic electrode 150 is in contact with the lower surface of the gallium oxide-based substrate layer 140 only through the upper surface to form ohmic contact.
Another aspect of the present invention discloses a method for preparing a gallium oxide-based semiconductor structure, which is used for preparing the above gallium oxide-based semiconductor structure, and as shown in fig. 3, the method comprises the following steps:
s210, forming a plurality of low-barrier Schottky electrodes on the upper surface of the gallium oxide-based epitaxial layer at intervals of a first distance;
s220, etching the upper surface of the gallium oxide-based epitaxial layer by taking the low-barrier Schottky electrodes as masks to form a plurality of channels, wherein the upper surface of the gallium oxide-based epitaxial layer between every two adjacent channels is used as a low-barrier contact surface which is in contact with the low-barrier Schottky electrodes; and
and S230, forming a high barrier Schottky electrode on the upper surface of the gallium oxide-based epitaxial layer with the plurality of channels, wherein the high barrier Schottky electrode covers the plurality of channels and the plurality of low barrier Schottky electrodes at the same time, and the inner surface of the channel is used as a high barrier contact surface which is in contact with the high barrier Schottky electrode.
Specifically, as an embodiment of the present invention, a plurality of trenches 131 may be formed on the upper surface of the gallium oxide-based epitaxial layer 130 by etching, and may be specifically referred to as a dashed box shown in fig. 1. At the same time when the trenches 131 are formed, the mesas 132 having a width dimension of the first distance d are simultaneously formed between the adjacent trenches 131. In addition, the low barrier schottky electrode 120 is correspondingly formed on the mesa 132 of the gallium oxide based epitaxial layer 130, the low barrier schottky electrode 120 is formed only on the upper surface of the mesa 132, and the low barrier schottky electrode 120 is in contact with only the upper surface of the mesa 132 to form the low barrier schottky contact on the interface therebetween. In addition, a high barrier schottky electrode 110 is directly formed on the gallium oxide-based epitaxial layer 130 on which the low barrier schottky electrode 120 is formed, the high barrier schottky electrode 110 is mainly formed on the inner surface of the channel 131 (as shown by the dotted frame in fig. 1), and the high barrier schottky electrode 110 is in contact with the inner surface of the channel 131 to form the high barrier schottky contact at the interface therebetween. In addition, the high barrier schottky electrode 110 has a thickness much greater than the sum of the depth of the channel 131 and the thickness of the low barrier schottky electrode 120 and masks the low barrier schottky electrode 120 (i.e., the low barrier schottky electrode 120 cannot be directly shown from a top view).
In summary, the gallium oxide-based semiconductor structure of the present invention realizes high-low double barrier schottky contact, and increases schottky contact area, so that it can be ensured that on-state resistance is not increased significantly. The technical effects corresponding to the technical features are explained by taking a high-low double-barrier schottky diode which can be applied to the invention as an example: when the high-low double barrier schottky diode is forward biased, the low barrier schottky is turned on at a lower voltage, and therefore the turn-on voltage of the structure will be substantially the same as the low barrier schottky diode. When the turn-on voltage of the high barrier is reached, the high and low double barrier Schottky are simultaneously conducted, so that the on-state resistance is not obviously reduced. When the high-low double-barrier Schottky diode is reversely biased, the reverse leakage of the low-barrier Schottky is pinched off due to the depletion effect of the channel in the high-barrier Schottky. The reverse leakage of the high and low double barrier schottky diode will be an order of magnitude with the high barrier schottky diode.
As an embodiment of the present invention, a lift-off method is used to form a plurality of low barrier schottky electrodes on the upper surface of the gallium oxide-based epitaxial layer at a first distance. The Lift-off process is a stripping process commonly used in the microelectronic technical field. Generally, photoresist is used for photoresist homogenizing, photoetching and developing for patterning, and then, the subsequent electrode deposition or etching and other related processes are performed on the semiconductor according to the patterning result. In the embodiment of the invention, the patterning treatment on the upper surface of the gallium oxide-based epitaxial layer is realized by adopting a Lift-off process, and then a plurality of low-barrier Schottky electrodes are formed on the upper surface of the gallium oxide-based epitaxial layer at a first distance from each other, wherein the first distance is d. Meanwhile, when a plurality of low-barrier Schottky electrodes are formed, a first protective layer covering the outer surfaces of the low-barrier Schottky electrodes is formed to prevent the surfaces of the low-barrier Schottky electrodes from being oxidized. The low barrier schottky electrode forms a low barrier schottky contact on the contact surface of the gallium oxide based epitaxial layer.
As an embodiment of the present invention, a method for forming a plurality of channels on an upper surface of a gallium oxide-based epitaxial layer by recessing based on a plurality of low barrier schottky electrodes, includes: and (3) taking the low-barrier Schottky electrode as a mask, and carrying out dry etching on the gallium oxide-based epitaxial layer by utilizing ICP (inductively coupled plasma) to recess the upper surface of the gallium oxide-based epitaxial layer to form a plurality of channels. On the upper surface of the gallium oxide-based epitaxial layer where the low-barrier Schottky electrodes are formed, dry etching is performed on the exposed upper surface of the gallium oxide-based epitaxial layer by using the low-barrier Schottky electrodes as a mask, so that a plurality of channels based on the upper surface depression can be formed.
In one embodiment of the present invention, a high barrier schottky electrode formed on an inner surface of a plurality of channels to cover a plurality of low barrier schottky electrodes at the same time includes: and forming a high-barrier Schottky electrode which covers the low-barrier Schottky electrodes simultaneously on the inner surfaces of the channels by adopting a magnetron sputtering method or a pulse laser deposition method. On the basis of forming a plurality of channels and a gallium oxide-based epitaxial layer structure of a plurality of low-barrier Schottky electrodes formed by spacing the channels, the preparation of the high-barrier Schottky electrode is directly carried out to cover the low-barrier Schottky electrodes and the channels. The high barrier schottky electrode forms a high barrier schottky contact at the interface within the channel of the gallium oxide based epitaxial layer.
To further clarify the description of the above preparation method, the present invention specifically refers to the following examples, which are more specifically illustrated and explained in conjunction with fig. 4 a-4 e:
in an embodiment of the present invention, gallium oxide-based substrate layer 140 is gallium oxide Ga2O3The wafer, the gallium oxide-based epitaxial layer 130 is an epitaxial layer structure of the gallium oxide wafer, the metal of the low-barrier schottky electrode is Ni-Ni, the first protective layer is Au, the oxide metal of the high-barrier schottky electrode is pt oxide, the ohmic electrode is Ti-Ti, and the second protective layer is Au.
The preparation method in the embodiment of the invention is shown in fig. 4 a-4 e;
ga with gallium oxide epitaxial layer 1302O3Wafer, Ga2O3The wafer may simultaneously serve as substrate layer 140. The thickness of the gallium oxide epitaxial layer 130 can reach more than 5 μm, as shown in fig. 4 a;
a lift-off process is adopted on the upper surface of the gallium oxide epitaxial layer 130, a plurality of low barrier metals with equal intervals are directly grown to serve as the low barrier schottky electrodes 120, and the plurality of low barrier schottky electrodes 120 are arranged on the upper surface of the gallium oxide epitaxial layer 130 at equal intervals by taking the first distance d as an interval and are in contact with the upper surface of the gallium oxide epitaxial layer 130 to form low barrier schottky contact. Then, a first protection layer 160 is formed on the outer surface of the formed low barrier schottky electrode 120 to cover the low barrier schottky electrode 120, wherein the low barrier metal may be Ni and the first protection layer 160 may be Au, as shown in fig. 4 b;
with the low barrier schottky electrode 120 and the first protection layer 160 on the upper surface of the gallium oxide epitaxial layer 130 shown in fig. 4b as a mask, dry etching is performed on the upper surface of the exposed gallium oxide epitaxial layer 130 by using ICP to form a plurality of channels 131 (shown by a dashed box in fig. 4 c) which are staggered corresponding to the low barrier schottky electrode 120 and the first protection layer 160 and a plurality of boss 132 structures corresponding to the channels 131. Wherein, the etching gas can be BCl3+ Ar to ensure better etch verticality, as shown in FIG. 4 c;
on the upper surface of the gallium oxide epitaxial layer 130 where the channel 131 and the low barrier schottky electrode 120 and the first protection layer 160 are formed as shown in fig. 4c, the high barrier schottky electrode 110 is grown by magnetron sputtering using platinum oxide PtOxThe electrode forming material fills the trench while covering the low barrier schottky electrode 120 and its first protection layer 160, as shown in fig. 4 d;
on the basis of the structure shown in fig. 4d, a metal back electrode titanium Ti is grown on the back surface of the structure by an electron beam evaporation method to serve as an ohmic electrode 150, and finally, a second protective layer gold Au is covered on the outer surface of the ohmic electrode 150 to prevent the titanium electrode from being oxidized. Wherein the ohmic electrode 150 forms an ohmic contact with the back side contact of the gallium oxide substrate layer.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are only exemplary embodiments of the present invention, and are not intended to limit the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A gallium oxide-based semiconductor structure, comprising:
the gallium oxide-based epitaxial layer is provided with a plurality of channels, and the plurality of channels are formed on the upper surface of the gallium oxide-based epitaxial layer and are separated from each other by a first distance;
a plurality of low barrier Schottky electrodes formed on the upper surface of the gallium oxide-based epitaxial layer between the plurality of channels; and
the high-barrier Schottky electrode is formed on the upper surface of the gallium oxide-based epitaxial layer and covers the channels and the low-barrier Schottky electrodes;
the channels are sunken in the inner surface of the gallium oxide-based epitaxial layer to serve as high-barrier contact surfaces in contact with the high-barrier Schottky electrodes, and the upper surface of the gallium oxide-based epitaxial layer between every two adjacent channels serves as low-barrier contact surfaces in contact with the low-barrier Schottky electrodes.
2. The gallium oxide-based semiconductor structure of claim 1,
the high-barrier Schottky electrode is a metal oxide electrode; and
the low-barrier Schottky electrode is a metal electrode, and the metal is Ni, Au, Pt, Cu, Mo, Ag or W.
3. The gallium oxide-based semiconductor structure of claim 1, wherein the trench has a depth h, 1 μ ι η ≦ h ≦ 3 μ ι η; the width of the channel is k, and k is more than or equal to 1 mu m and less than or equal to 5 mu m; the first distance is d, and d is more than or equal to 1 mu m and less than or equal to 5 mu m.
4. The gallium oxide-based semiconductor structure of claim 1, wherein a first protective layer is further included between the low barrier schottky electrode and the high barrier schottky electrode.
5. The gallium oxide-based semiconductor structure of claim 1, further comprising:
a gallium oxide-based substrate layer located under the gallium oxide-based epitaxial layer,
and an ohmic electrode located under the gallium oxide-based substrate layer.
6. The gallium oxide-based semiconductor structure of claim 5,
the outer surface of the ohmic electrode is covered with a second protective layer.
7. A method of fabricating a gallium oxide-based semiconductor structure, for fabricating the gallium oxide-based semiconductor structure of any one of claims 1-6, comprising:
forming a plurality of low-barrier Schottky electrodes on the upper surface of the gallium oxide-based epitaxial layer at intervals of a first distance;
etching the upper surface of the gallium oxide-based epitaxial layer by taking the low-barrier Schottky electrodes as a mask to form a plurality of channels, wherein the upper surface of the gallium oxide-based epitaxial layer between two adjacent channels is taken as a low-barrier contact surface which is in contact with the low-barrier Schottky electrodes; and
and forming a high barrier Schottky electrode on the upper surface of the gallium oxide-based epitaxial layer on which the plurality of channels are formed, wherein the high barrier Schottky electrode covers the plurality of channels and the plurality of low barrier Schottky electrodes at the same time, and the inner surface of each channel is used as a high barrier contact surface which is in contact with the high barrier Schottky electrode.
8. The method for fabricating a gallium oxide-based semiconductor structure according to claim 7,
and forming a plurality of low-barrier Schottky electrodes on the upper surface of the gallium oxide-based epitaxial layer at intervals of a first distance by adopting a lift-off method.
9. The method according to claim 7, wherein the etching the upper surface of the gallium oxide-based epitaxial layer to form a plurality of channels using the plurality of low barrier schottky electrodes as a mask comprises:
and carrying out dry etching on the gallium oxide base epitaxial layer by using the low-barrier Schottky electrode as a mask and utilizing ICP (inductively coupled plasma), and forming a plurality of channels on the upper surface of the gallium oxide base epitaxial layer in a concave mode.
10. The method for preparing a gallium oxide-based semiconductor structure according to claim 7, wherein the forming of the high barrier schottky electrode on the upper surface of the gallium oxide-based epitaxial layer on which the plurality of channels are formed comprises:
and forming a high-barrier Schottky electrode which covers the low-barrier Schottky electrodes simultaneously on the inner surfaces of the channels by adopting a magnetron sputtering method or a pulse laser deposition method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911283509.0A CN111129166B (en) | 2019-12-13 | 2019-12-13 | Gallium oxide-based semiconductor structure and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911283509.0A CN111129166B (en) | 2019-12-13 | 2019-12-13 | Gallium oxide-based semiconductor structure and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111129166A true CN111129166A (en) | 2020-05-08 |
| CN111129166B CN111129166B (en) | 2023-02-07 |
Family
ID=70498716
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911283509.0A Active CN111129166B (en) | 2019-12-13 | 2019-12-13 | Gallium oxide-based semiconductor structure and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111129166B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113436970A (en) * | 2021-06-24 | 2021-09-24 | 中国科学技术大学 | Preparation method of double-barrier Schottky diode |
| CN113964210A (en) * | 2021-09-13 | 2022-01-21 | 西安电子科技大学 | Low-turn-on voltage gallium oxide power diode and preparation method thereof |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08116072A (en) * | 1994-10-17 | 1996-05-07 | Murata Mfg Co Ltd | Schottky barrier semiconductor device |
| JPH11251605A (en) * | 1998-02-27 | 1999-09-17 | Hitachi Ltd | Schottky barrier semiconductor device |
| US6362495B1 (en) * | 1998-03-05 | 2002-03-26 | Purdue Research Foundation | Dual-metal-trench silicon carbide Schottky pinch rectifier |
| WO2013125421A1 (en) * | 2012-02-21 | 2013-08-29 | 株式会社村田製作所 | Resistance switching device and method for manufacturing same |
| CN106935661A (en) * | 2017-01-23 | 2017-07-07 | 西安电子科技大学 | Vertical-type Schottky diode and preparation method thereof |
| CN107369720A (en) * | 2017-07-05 | 2017-11-21 | 西安交通大学 | A kind of p-type diamond height barrier Schottky diode and preparation method thereof |
| CN108369964A (en) * | 2015-12-25 | 2018-08-03 | 出光兴产株式会社 | Laminated body |
| CN108475702A (en) * | 2015-12-25 | 2018-08-31 | 出光兴产株式会社 | Laminated body |
| CN109449214A (en) * | 2018-12-05 | 2019-03-08 | 山东大学 | A kind of gallium oxide semiconductor Schottky diode and preparation method thereof |
-
2019
- 2019-12-13 CN CN201911283509.0A patent/CN111129166B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08116072A (en) * | 1994-10-17 | 1996-05-07 | Murata Mfg Co Ltd | Schottky barrier semiconductor device |
| JPH11251605A (en) * | 1998-02-27 | 1999-09-17 | Hitachi Ltd | Schottky barrier semiconductor device |
| US6362495B1 (en) * | 1998-03-05 | 2002-03-26 | Purdue Research Foundation | Dual-metal-trench silicon carbide Schottky pinch rectifier |
| WO2013125421A1 (en) * | 2012-02-21 | 2013-08-29 | 株式会社村田製作所 | Resistance switching device and method for manufacturing same |
| CN108369964A (en) * | 2015-12-25 | 2018-08-03 | 出光兴产株式会社 | Laminated body |
| CN108475702A (en) * | 2015-12-25 | 2018-08-31 | 出光兴产株式会社 | Laminated body |
| CN106935661A (en) * | 2017-01-23 | 2017-07-07 | 西安电子科技大学 | Vertical-type Schottky diode and preparation method thereof |
| CN107369720A (en) * | 2017-07-05 | 2017-11-21 | 西安交通大学 | A kind of p-type diamond height barrier Schottky diode and preparation method thereof |
| CN109449214A (en) * | 2018-12-05 | 2019-03-08 | 山东大学 | A kind of gallium oxide semiconductor Schottky diode and preparation method thereof |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113436970A (en) * | 2021-06-24 | 2021-09-24 | 中国科学技术大学 | Preparation method of double-barrier Schottky diode |
| CN113436970B (en) * | 2021-06-24 | 2024-03-29 | 中国科学技术大学 | Preparation method of double barrier Schottky diode |
| CN113964210A (en) * | 2021-09-13 | 2022-01-21 | 西安电子科技大学 | Low-turn-on voltage gallium oxide power diode and preparation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111129166B (en) | 2023-02-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP6930197B2 (en) | Semiconductor devices and manufacturing methods for semiconductor devices | |
| JP6580267B2 (en) | Semiconductor device and manufacturing method of semiconductor device | |
| US7132699B2 (en) | Compound semiconductor device and its manufacture | |
| US9793392B2 (en) | Semiconductor device | |
| US20180358463A1 (en) | Semiconductor device and method of manufacturing a semiconductor device | |
| JP6104575B2 (en) | Semiconductor device | |
| JP6477106B2 (en) | Semiconductor device | |
| US10453954B2 (en) | Semiconductor device having trenches in termination structure region thereof and method for manufacturing the same | |
| JP5636752B2 (en) | Semiconductor device and manufacturing method thereof | |
| CN111129166A (en) | Gallium oxide-based semiconductor structure and preparation method thereof | |
| WO2017187856A1 (en) | Semiconductor device | |
| US10269952B2 (en) | Semiconductor device having steps in a termination region and manufacturing method thereof | |
| US11424357B2 (en) | Semiconductor device | |
| US11322593B2 (en) | Silicon carbide semiconductor device and method of manufacturing silicon carbide semiconductor device | |
| JP5757746B2 (en) | Nitride semiconductor device | |
| JP2009182217A (en) | Semiconductor device and manufacturing method thereof | |
| CN116417520A (en) | Gallium oxide field effect transistor and preparation method thereof | |
| US11411105B2 (en) | Silicon carbide semiconductor device | |
| WO2020021298A1 (en) | Semiconductor device and manufacturing method therefor | |
| US6855983B1 (en) | Semiconductor device having reduced on resistance | |
| JP4925596B2 (en) | Nitride semiconductor device | |
| CN114203804B (en) | A HEMT chip of silicon carbide-based graphene material and preparation method thereof | |
| CN222621488U (en) | HEMT Devices | |
| JP6256008B2 (en) | Semiconductor device and manufacturing method of semiconductor device | |
| CN113990920B (en) | A nitride power semiconductor device with a core-shell structure and a method for preparing the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| TA01 | Transfer of patent application right | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20211224 Address after: 230000 China (Anhui) pilot Free Trade Zone, Hefei, Anhui Province a1205-a1208, future center, Institute of advanced technology, University of science and technology of China, No. 5089, Wangjiang West Road, high tech Zone, Hefei Applicant after: Hefei Zhongke microelectronics Innovation Center Co.,Ltd. Address before: 230026 Jinzhai Road, Baohe District, Hefei, Anhui Province, No. 96 Applicant before: University of Science and Technology of China |
|
| GR01 | Patent grant | ||
| GR01 | Patent grant |