CN111509037A - Silicon carbide MOS device with groove type JFET and preparation process thereof - Google Patents

Abstract

The invention discloses a silicon carbide MOS device with a grooved JFET and a preparation process thereof, wherein a silicon carbide MOS device with a grooved JFET comprises: a silicon carbide substrate, and the material of the silicon carbide substrate is The doping type is the first conductivity type; the front and back surfaces of the silicon carbide substrate are respectively provided with a first conductivity type semiconductor epitaxial layer and a drain electrode; a JFET region is provided on the active region of the first conductivity type semiconductor epitaxial layer, The JFET region is provided with a first surface, a second surface and a third surface, wherein the first surface and the second surface are respectively provided with a first conductive type source region and a second conductive type base region from outside to inside; above the first surface There is a source electrode, a gate dielectric and a gate electrode are arranged above the third surface, a second conductivity type implantation body region is arranged between the second conductivity type base region and the source electrode, and an inter-electrode isolation is arranged between the source electrode and the gate electrode medium.

Description

A silicon carbide MOS device with grooved JFET and its preparation process

technical field

The invention belongs to the technical field of semiconductors, and in particular relates to a silicon carbide MOS device with a grooved JFET and a preparation process thereof.

Background technique

MOS field effect transistor power devices made of silicon carbide (SiC) can withstand higher voltages and faster switching speeds than Si devices. Because silicon carbide is often used in high-voltage applications, its epitaxial layer doping concentration is relatively low, so that the JFET resistance in the MOSFET accounts for a larger proportion of the total on-resistance, which increases the on-resistance and conduction loss of the MOS device. Not only that, due to the high manufacturing cost of SiC MOS and the difficulty in defining the channel, how to obtain a narrower channel under the condition of reducing the number of lithography has become a difficulty in mass production of SiC MOS devices at this stage.

Since silicon carbide MOS devices have low channel mobility, it is often necessary to reduce the size of their cells, and increase the channel density to reduce the proportion of the channel resistance of the device in the on state. However, while reducing the cell size, the proportion of on-resistance in the JFET region of the device is also increasing. At the same time, the higher channel density also makes the device have higher saturation current, resulting in poor short-circuit characteristics of the device. Therefore, if the saturation current when a short circuit occurs can be effectively reduced, the short circuit withstand capability of the device can be improved.

SUMMARY OF THE INVENTION

In view of the above existing technical problems, the present invention is used to provide a silicon carbide MOS device with a grooved JFET and a preparation process thereof. The current is added to the active region to strengthen the injection region, so as to reduce the problems caused by the low epitaxial doping concentration. The problem of excessive JFET resistance.

In order to solve the above-mentioned technical problems, the present invention adopts the following technical scheme:

An aspect of the embodiments of the present invention provides a silicon carbide MOS device with a trench JFET, including:

a silicon carbide substrate, the doping type of the silicon carbide substrate material is the first conductivity type;

A first conductive type semiconductor epitaxial layer and a drain are respectively provided on the front and back surfaces of the silicon carbide substrate;

A first conductive type JFET region is provided on the active region of the first conductive type semiconductor epitaxial layer, and a first surface, a second surface and a third surface are provided on the first conductive type JFET region, wherein the first surface and the second surface The surface is respectively provided with a first conductive type source region and a second conductive type base region from the outside to the inside; a source electrode is arranged above the first surface, a gate dielectric and a gate electrode are arranged above the third surface, and the second conductive type base region and An implanted body region of the second conductivity type is arranged between the source electrodes, and an inter-electrode isolation medium is arranged between the source electrode and the gate electrode.

Preferably, the concentration of the first conductive type JFET region is 1.2 to 1000 times higher than the concentration of the first conductive type epitaxial layer.

Preferably, the first conductivity type is N type, and the second conductivity type is P type.

Preferably, the first conductivity type is P type, and the second conductivity type is N type.

Another aspect of the embodiments of the present invention provides a process for fabricating a silicon carbide MOS device with a trench JFET, including the following steps:

(a) A first conductivity type semiconductor epitaxial layer is respectively provided on the front and back of the silicon carbide substrate, wherein the doping type of the silicon carbide substrate material is the first conductivity type; implanting the first conductivity type epitaxial layer on the first conductivity type epitaxial layer conductivity type ions form a first conductivity type JFET region;

(b) masking part of the surface with a mask material, and etching the silicon carbide mesa with ICP;

(c) using the same layer of mask for ion implantation;

(d) using thermal oxidation to grow 10-100nm _SiO2 on the surface of the first conductive type semiconductor epitaxial layer and performing NO annealing to improve the reliability of the gate oxide, using chemical vapor deposition to deposit and grow 300-1000nm polysilicon on _SiO2 , Using the same lithography plate, photolithography and etching retain the gate oxide and polysilicon of the gate part, and form a P-type doped gate;

(e) Using chemical vapor deposition of BPSG as the gate isolation medium, exposing the source electrode region by photolithography, evaporating Ni on the front and back sides of the silicon carbide epitaxial wafer as an ohmic contact metal, and annealing in a nitrogen atmosphere to form an ohmic contact , Ti and Al are evaporated on the front as the source metal;

(f) chemical vapor deposition of SiN and spin-coated polyimide are used as passivation layers on the front metal, and source metal is exposed by photolithography and etching;

(g) Deposition Ti/Ni/Ag on the backside to form backside drain metal.

Preferably, the step (c) further comprises:

(c.1) The second conductive type base region is implanted obliquely, and the implantation angle and the wafer plane angle are 0 to 90 degrees;

(c.2) using vertical implantation to form a second conductive type body region;

(c.3) adopting the oblique implantation of the first conductivity type ions to form the first conductivity type source region, and the implantation angle and the wafer plane angle are 0 to 90 degrees;

(c.4) After removing the mask, high temperature activation annealing is performed in an inert gas to activate the implanted impurities.

Preferably, in step (a), the concentration of the first conductive type JFET region is 1.2 to 1000 times higher than the concentration of the first conductive type epitaxial layer.

Preferably, in step (b), the etching depth is 0.1 to 4um.

Preferably, the first conductivity type is N type, and the second conductivity type is P type.

Preferably, the first conductivity type is P type, and the second conductivity type is N type.

Adopting the present invention has the following beneficial effects:

(1) Adding a current to the active area to strengthen the injection area to reduce the problem of excessive JFET resistance caused by too low epitaxial doping concentration;

(2) Use the same lithography plate to define the mesa etching, gate dielectric, gate electrode, body region, base region and source region, which greatly reduces the number of lithography of MOS devices, reduces the mass production cycle, and effectively reduces chip costs ;

(3) While ensuring that the device has a smaller cell size, the channel resistance is reduced while maintaining a lower JFET resistance and a lower saturation current. This is due to the fact that the electric field of the gate oxide under reverse bias is very low after the doping of the JFET region is increased, and the trench JFET region will be pinch-off, ensuring a lower saturation current. Although the traditional MOSFET also has a JFET area, this JFET area will not be pinch-off during short-circuit operation, resulting in high short-circuit current and poor short-circuit characteristics of the device. Therefore, the present invention can reduce the overall on-resistance of the device while ensuring its strong short-circuit characteristics.

Description of drawings

1 is a schematic structural diagram of a silicon carbide substrate provided with a first conductive type semiconductor epitaxial layer on the front side in the fabrication process of a silicon carbide MOS device with a trench JFET according to an embodiment of the present invention;

FIG. 2 is a schematic structural diagram of forming a first conductive type JFET region in a manufacturing process of a silicon carbide MOS device with a trench JFET according to an embodiment of the present invention;

3 is a schematic structural diagram of a silicon carbide mesa etched by ICP in the preparation process of a silicon carbide MOS device with a grooved JFET according to an embodiment of the present invention;

4 is a schematic structural diagram of a base region of a second conductivity type using oblique implantation in a process for preparing a silicon carbide MOS device with a trench JFET according to an embodiment of the present invention;

5 is a schematic structural diagram of forming a second conductivity type implanted body region by vertical implantation in the fabrication process of a silicon carbide MOS device with a trench JFET according to an embodiment of the present invention;

6 is a schematic structural diagram of forming a source region of a first conductivity type in a manufacturing process of a silicon carbide MOS device with a trench JFET according to an embodiment of the present invention;

7 is a schematic structural diagram of forming a gate in a manufacturing process of a silicon carbide MOS device with a trench JFET according to an embodiment of the present invention;

8 is a schematic structural diagram of a silicon carbide MOS device with a trench JFET formed by a fabrication process of a silicon carbide MOS device with a trench JFET according to an embodiment of the present invention.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

The embodiment of the present invention discloses a step flow chart of a preparation process of a silicon carbide MOS device with a grooved JFET, including the following steps:

(a) Referring to FIG. 1 and FIG. 2, a first conductivity type semiconductor epitaxial layer 002 is provided on the front surface of the silicon carbide substrate 001, wherein the doping type of the material of the silicon carbide substrate 001 is the first conductivity type; The first conductive type ions are implanted on the type epitaxial layer 002 to form a first conductive type JFET region 009;

The advantages of adding the JFET (Junction Field-Effect Transistor, Junction Field Effect Transistor) region are: First, the current enhancement injection region is added to the active region to reduce the problem of excessive JFET resistance caused by the low epitaxial doping concentration. ; In addition, the embodiments of the present invention reduce the channel resistance while ensuring that the device has a smaller cell size, while maintaining a lower JFET resistance and a lower saturation current. This is due to the fact that the electric field of the gate oxide under reverse bias is very low after the doping of the JFET region is increased, and the trench JFET region will be pinch-off, ensuring a lower saturation current. Although the traditional MOSFET also has a JFET area, the JFET area of the traditional MOSFET will not be pinch-off during short-circuit operation, resulting in high short-circuit current and poor short-circuit characteristics of the device. Therefore, the embodiments of the present invention can reduce the overall on-resistance of the device while ensuring its strong short-circuit characteristics.

(b) Referring to Fig. 3, a part of the surface is covered with a mask material, and a silicon carbide mesa is etched by ICP;

(c) Use the same layer of mask for ion implantation; the advantage of using the same mask is that the same lithography is used to define the mesa etching, gate dielectric, gate electrode, body region, base region and source region, which greatly reduces MOS The number of lithography of the device reduces the mass production cycle and effectively reduces the cost of chip manufacturing.

Specifically, step (c) further comprises:

Specifically include the following steps:

(c.1) Referring to FIG. 4, the second conductive type base region 005 is implanted obliquely, and the implantation angle and the wafer plane angle are 0 to 90 degrees;

(c.2) Referring to FIG. 5, vertical implantation is used to form the implanted body region 010 of the second conductivity type;

(c.3) Referring to FIG. 6, the first conductivity type source region 004 is formed by obliquely implanting the first conductivity type ions, and the implantation angle and the wafer plane angle are in the range of 0 to 90 degrees;

(c.4) After removing the mask, high temperature activation annealing is performed in an inert gas to activate the implanted impurities.

(d) Referring to FIG. 7, a gate dielectric 007 of 10-100 nm is grown on the surface of the first conductive type semiconductor epitaxial layer 002 by thermal oxidation and NO annealing is performed to improve the reliability of the gate oxide, and chemical vapor deposition is used to deposit on the gate dielectric 007 growing the gate 008 of 300-1000 nm, using the same lithography plate, photolithography and etching to retain the gate oxide and polysilicon of the gate part, and form the P-type doped gate 008;

(e) Using chemical vapor deposition BPSG as the gate isolation medium 011, exposing the source electrode 006 region by photolithography, evaporating Ni on the front and back sides of the silicon carbide epitaxial wafer as an ohmic contact metal, and annealing in a nitrogen atmosphere to form Ohmic contact, Ti and Al are evaporated on the front as source metal;

(f) chemical vapor deposition of SiN and spin-coated polyimide are used as passivation layers on the front metal, and source metal is exposed by photolithography and etching;

(g) Deposition Ti/Ni/Ag on the backside to form backside drain metal 003.

The structure of the silicon carbide MOS device with a grooved JFET prepared by the above process is shown in FIG. 8 , that is, a silicon carbide MOS device with a grooved JFET according to another embodiment of the present invention, including:

Silicon carbide substrate 001, the doping type of the material of the silicon carbide substrate 001 is the first conductivity type;

A first conductive type semiconductor epitaxial layer 002 and a drain 003 are respectively provided on the front and back of the silicon carbide substrate 001;

A JFET region 009 is provided on the active region of the first conductive type semiconductor epitaxial layer 002, and a first surface, a second surface and a third surface are provided on the JFET region 009, wherein the first surface and the second surface are from outside to inside A first conductive type source region 004 and a second conductive type base region 005 are respectively provided; a source electrode 006 is provided above the first surface, a gate dielectric 007 and a gate 008 are provided above the third surface, and the second conductive type base region 005 Between the source electrode 006 and the source electrode 006 , an implanted body region 010 of the second conductivity type is arranged, and an inter-electrode isolation medium 011 is arranged between the source electrode 006 and the gate electrode 008 .

In order to enable those skilled in the art to better understand the implementation process of the embodiment of the present invention, in a specific application example, the first conductivity type is N-type and the second conductivity type is P-type to further illustrate the implementation of the embodiment of the present invention The process of preparing a silicon carbide MOS device with a trench JFET includes the following steps:

(a) First, N ions are implanted on the silicon carbide N-type epitaxial layer to form an N-type JFET region, and the concentration of the current enhancement region is 1.2 to 1000 times higher than that of the epitaxial layer.

(b) Part of the surface is masked with a mask material, and the silicon carbide mesa is etched by ICP, and the etching depth is 0.1 to 4um.

(c) Using the same layer of mask for ion implantation, the specific process includes:

(c.1) A P-type base region is formed by implanting Al ions obliquely, and the implantation angle and the wafer plane angle are 0 to 90 degrees.

(c.2) A P+ type body region is formed by vertically implanting Al ions.

(c.3) The N+ type source region is formed by obliquely implanting N ions, and the implantation angle and the wafer plane angle are 0 to 90 degrees.

(c.4) After removing the mask, high temperature activation annealing is performed in an inert gas to activate the implanted impurities.

(d) Use thermal oxidation to grow 10-100 nm SiO ₂ on the surface of the SiC epitaxial layer and perform NO annealing to improve the reliability of the gate oxide. The polysilicon of 300-1000nm is deposited and grown on _SiO2 by chemical vapor deposition, and the same lithography plate is used to photolithography and etch the gate oxide and polysilicon of the reserved gate part, and form a P-type doped gate.

(e) Using chemical vapor deposition of BPSG as the isolation medium, the source electrode region was exposed by photolithography. Ni was evaporated on both sides of the silicon carbide epitaxial wafer as an ohmic contact metal, and annealed in a nitrogen atmosphere to form an ohmic contact. Since Ni reacts with SiC, part of the N+ type source region will be reacted. Ti and Al are evaporated on the front side as source metals.

In other application examples, the first conductivity type may be N-type and the second conductivity type may be P-type depending on the choice of materials.

It should be understood that the exemplary embodiments described herein are illustrative and not restrictive. Although one or more embodiments of the invention have been described in conjunction with the accompanying drawings, those of ordinary skill in the art will appreciate that various changes can be made without departing from the spirit and scope of the invention as defined by the appended claims. Changes in form and detail.

Claims (10)

1. a silicon carbide MOS device with grooved JFET, is characterized in that, comprises: a silicon carbide substrate (001), the doping type of the material of the silicon carbide substrate (001) is the first conductivity type; A first conductive type semiconductor epitaxial layer (002) and a drain electrode (003) are respectively provided on the front and back surfaces of the silicon carbide substrate (001); A first conductive type JFET region (009) is provided on the active region of the first conductive type semiconductor epitaxial layer (002), and a first surface, a second surface and a third surface are provided on the first conductive type JFET region (009). surface, wherein the first surface and the second surface are respectively provided with a first conductivity type source region (004) and a second conductivity type base region (005) from outside to inside; a source electrode (006) is arranged above the first surface, and the first A gate dielectric (007) and a gate electrode (008) are arranged above the three surfaces, a second conductivity type implant region (010) is arranged between the second conductivity type base region (005) and the source electrode (006), and the source electrode ( An inter-electrode isolation medium (011) is arranged between the gate electrode (006) and the gate electrode (008). 2. The silicon carbide MOS device with trench JFET according to claim 1, characterized in that the concentration of the first conductive type JFET region (009) is higher than the concentration of the first conductive type epitaxial layer (002) by 1.2-1000 times. 3 . The silicon carbide MOS device with trench JFET according to claim 1 , wherein the first conductivity type is N type, and the second conductivity type is P type. 4 . 4 . The silicon carbide MOS device with trench JFET according to claim 1 , wherein the first conductivity type is P-type, and the second conductivity type is N-type. 5 . 5. A silicon carbide MOS device preparation process with grooved JFET, characterized in that, comprising the following steps: (a) A first conductivity type semiconductor epitaxial layer (002) is respectively provided on the front and back sides of the silicon carbide substrate (001), wherein the doping type of the material of the silicon carbide substrate (001) is the first conductivity type; A conductive type epitaxial layer (002) is implanted with first conductive type ions to form a first conductive type JFET region (009); (b) masking part of the surface with a mask material, and etching the silicon carbide mesa with ICP; (c) using the same layer of mask for ion implantation; (d) A gate dielectric (007) with a thickness of 10-100 nm is grown on the surface of the first conductive type semiconductor epitaxial layer (002) by thermal oxidation and NO annealing is performed to improve the reliability of the gate oxide, and chemical vapor deposition is used on the gate dielectric (007) A gate electrode (008) of 300-1000 nm is deposited and grown on the top, and the same lithography plate is used to photolithography and etch the gate oxide and polysilicon of the reserved gate part, and form a P-type doped gate gate (008); (e) Chemical vapor deposition of BPSG is used as the inter-gate isolation medium (011), the source electrode region is exposed by photolithography, Ni is evaporated on both sides of the silicon carbide epitaxial wafer as ohmic contact metal, and annealed in nitrogen atmosphere An ohmic contact is formed, and Ti and Al are evaporated on the front as the source metal; (f) using chemical vapor deposition of SiN and spin-coated polyimide as a passivation layer on the front metal, and exposing the source metal by photolithography and etching; (g) Deposition of Ti/Ni/Ag on the backside to form backside drain metal (003). 6. The process for preparing a silicon carbide MOS device with a trench JFET as claimed in claim 5, wherein the step (c) further comprises: (c.1) The second conductive type base region is implanted obliquely, and the implantation angle and the wafer plane angle are 0 to 90 degrees; (c.2) using vertical implantation to form a body region of the second conductivity type; (c.3) adopting the oblique implantation of the first conductivity type ions to form the first conductivity type source region, and the implantation angle and the wafer plane angle are 0 to 90 degrees; (c.4) After removing the mask, high temperature activation annealing is performed in an inert gas to activate the implanted impurities. 7. The fabrication process of a silicon carbide MOS device with a trench JFET according to claim 5 or 6, wherein in step (a), the concentration of the first conductive type JFET region (009) is higher than that of the first conductive type 1.2 to 1000 times the concentration of the epitaxial layer (002). 8 . The fabrication process of a silicon carbide MOS device with a trench JFET according to claim 3 or 4 , wherein, in step (b), the etching depth is 0.1 to 4 μm. 9 . 9 . The fabrication process of the silicon carbide MOS device with trench JFET according to claim 5 , wherein the first conductivity type is N type, and the second conductivity type is P type. 10 . 10 . The fabrication process of a silicon carbide MOS device with a trench JFET according to claim 5 , wherein the first conductivity type is P-type, and the second conductivity type is N-type. 11 .

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