CN118538774B - Silicon carbide planar gate power MOSFET and manufacturing method - Google Patents

Abstract

The present invention provides a silicon carbide planar gate power MOSFET and a manufacturing method, belonging to the field of power semiconductor technology. The device has an ohmic contact formed by different metals in the p+ region and the n+ region, and uses a spacer thin dielectric layer to achieve channel self-alignment of the n+ source region, thereby ensuring the reliability of the device and reducing the resistance of the channel region, thereby reducing the overall specific on-resistance of the device. In the process, ion implantation in the p+ region is first performed, and nitrogen ions in the n+ region are implanted into the p+ region after being blocked by a metal layer. The metal layer finally forms an ohmic contact in the p+ region at the same time as the silicon carbide wafer is thermally annealed after implantation. The present invention optimizes the process flow of the device, simplifies the manufacturing process steps of the silicon carbide planar gate MOSFET, reduces the process time and production cost of the silicon carbide planar gate MOSFET, and realizes ohmic contacts of different metals in the n+ region and the p+ region respectively.

Description

A silicon carbide planar gate power MOSFET and manufacturing method thereof

Technical Field

The invention relates to a novel silicon carbide (SiC) planar gate power MOSFET and a manufacturing method thereof, belonging to the technical field of power semiconductors.

Background Art

A power MOSFET can carry a large current in the on state and withstand a large breakdown voltage in the off state. The current between the source and drain regions in the semiconductor substrate is controlled by a voltage applied to the gate, which is isolated from the semiconductor surface by an insulator (usually silicon dioxide). For example, in an n-type enhancement MOSFET, a positive bias on the gate causes a surface inversion layer or channel to form in the p-type region under the gate oxide, forming a conductive path between the source and drain. Current is generated between the positive drain and source. Over the years, lateral and vertical power MOSFET structures in silicon have been explored, with the former having the drain, gate, and source on the same surface of the silicon wafer and the latter having the source and drain on opposite surfaces of the silicon wafer. Several different types of vertical power MOSFETs have been proposed, including DMOSFET and UMOSFET.

The structures of DMOSFET and UMOSFET are still valid for SiC MOSFET. The D in DMOSFET refers to double-implanted MOSFET in SiC MOSFET. The p-base region and n+ source region are produced by ion implantation rather than thermal diffusion. Because the diffusion coefficient of impurities in SiC is very low, it is not practical to apply diffusion process in SiC. SiC is the third generation wide bandgap semiconductor material. Compared with Si-based MOSFET, SiC-based MOSFET has higher breakdown voltage, lower on-resistance and lower conduction loss. In the field of power devices, the market share of SiC power devices is increasing year by year.

Nevertheless, the potential advantages of SiC as a power MOSFET have not yet been fully realized, including optimizing the manufacturing process of SiC MOSFET devices, simplifying the process flow of SiC MOSFET, and saving costs and process time.

Summary of the invention

In view of the shortcomings of the prior art, the present invention provides a power semiconductor device and a method for manufacturing the same. The silicon carbide power MOSFET has an ohmic contact formed by different metals in the p+ region and the n+ region, and uses a spacer thin dielectric layer to achieve self-alignment of the channel in the n+ source region, thereby ensuring the reliability of the device and achieving a shorter channel with a length of less than 0.5um, reducing the resistance of the channel region, and thus reducing the overall specific on-resistance of the device. In the process of the silicon carbide power MOSFET, ion implantation in the p+ region is first performed, and nitrogen ions in the n+ region are implanted into the p+ region after being blocked by a layer (or multiple layers) of metal layers. The metal layer finally forms an ohmic contact in the p+ region at the same time as the silicon carbide wafer is thermally annealed after implantation.

The technical solution of the present invention is as follows:

A silicon carbide planar gate power MOSFET comprises, from bottom to top, a substrate, an epitaxial layer, and a CSL layer, a p-well region is formed by implantation on the CSL layer, a p+ region and a p+ region metal layer are provided in the middle of the p-well region from bottom to top, n+ regions are implanted on the upper surface of the p-well region on both sides of the p+ region, a junction terminal region is implanted on the CSL layer next to the p-well region, and the junction terminal region is connected to one side of the p-well region;

A gate oxide layer and a gate polysilicon are arranged in sequence above the CSL layer on the p+ region side, and the two cover part of the CSL layer, part of the p-well region, and part of the n+ region; a dielectric layer is arranged above and on the side of the gate polysilicon, and a source metal is arranged next to the dielectric layer, and the source metal covers part of the n+ region and part of the p+ region metal layer; a dielectric layer is arranged next to the source metal, and the dielectric layer covers part of the p+ region metal layer, the n+ region, part of the p-well region, and the junction terminal region;

A top metal layer is disposed above the dielectric layer and the source metal.

Preferably, a marking groove is etched on the CSL layer beside the junction termination region, and the marking groove is not covered by any material.

A method for manufacturing a silicon carbide planar gate power MOSFET comprises the following steps:

(1) Grow an n-type epitaxial layer and a CSL layer on the substrate; then etch a marking groove on the surface of the wafer;

Preferably, the substrate is a 4H-SiC n-type heavily doped low resistivity substrate with a resistivity of 0.015-0.025Ω·cm; the n-type epitaxial layer is lightly doped with a doping concentration of 1×10 ¹⁵ cm ^-3 -1×10 ¹⁶ cm ^-3 ; and the CSL layer doping concentration is 2×10 ¹⁶ -1×10 ¹⁷ cm ^-3 .

(2) A first hard mask layer of sufficient thickness is formed on the surface of the wafer, and the first hard mask layer is etched using a mask to expose a window for ion implantation in the p+ region; the marking groove is self-aligned with the injection window in the p+ region, thereby saving a 1μm alignment tolerance; and p-type (e.g., aluminum ion) implantation is performed to form the p+ region.

Preferably, in step (2), the composition of the first hard mask layer from bottom to top includes the following selections:

a. Ion implantation barrier layer (e.g. silicon dioxide layer), oxide layer (e.g. silicon dioxide);

b. Ion implantation barrier layer (e.g. silicon dioxide layer), polysilicon layer;

c. Ion implantation barrier layer (e.g. silicon dioxide layer), polysilicon layer, metal layer (e.g. nickel, titanium, gold, copper, chromium, aluminum);

d. ion implantation barrier layer (e.g. silicon dioxide layer), polysilicon layer, oxide layer (e.g. silicon dioxide layer);

e. Ion implantation barrier layer (such as silicon dioxide layer), polysilicon layer, oxide layer (such as silicon dioxide layer), metal layer (such as nickel, titanium, gold, copper, chromium, aluminum).

Preferably, in step (2), the ions used to make the p+ region are aluminum ions, and the doping concentration of the p+ region should have a peak concentration of 1×10 ¹⁹ -5×10 ¹⁹ cm ^-3 to ensure the formation of a good ohmic contact.

(3) After the p+ region injection is completed, a p+ region metal layer is sputtered, annealed, and the unreacted metal is washed away with a dilute sulfuric acid and hydrogen peroxide solution.

Preferably, in step (3), the composition of the p+ region metal layer includes: nickel, titanium, tungsten, tantalum, molybdenum or alloys thereof.

Preferably, in step (3), annealing is performed at a temperature above 450° C. for at least 30 seconds. The thickness of the metal layer should be sufficient to block nitrogen ions injected into the n+ region and should be no less than 0.5 μm.

(4) Remove the first hard mask layer in step (3) on the surface, then make a second hard mask layer of sufficient thickness, and use a mask to etch a p-well area window; perform p-type implantation to make the p-well area. The thickness of the ion implantation barrier layer is generally the same, and the implantation height of the p-well area is flush with the CSL layer and lower than the metal layer.

Preferably, in step (4), the second hard mask layer is composed from bottom to top of the following:

a. Ion implantation barrier layer (e.g. silicon dioxide layer), oxide layer (e.g. silicon dioxide);

b. Ion implantation barrier layer (e.g. silicon dioxide layer), polysilicon layer;

c. Ion implantation barrier layer (e.g. silicon dioxide layer), polysilicon layer, metal layer (e.g. nickel, titanium, gold, copper, chromium, aluminum);

d. ion implantation barrier layer (e.g. silicon dioxide layer), polysilicon layer, oxide layer (e.g. silicon dioxide layer);

e. Ion implantation barrier layer (such as silicon dioxide layer), polysilicon layer, oxide layer (such as silicon dioxide layer), metal layer (such as nickel, titanium, gold, copper, chromium, aluminum).

Further preferably, the window only needs to be etched to the ion implantation barrier layer of the second hard mask layer.

Preferably, in step (4), the ions used to make the p-well region are aluminum ions; in order to achieve a sufficient breakdown voltage, the doping concentration of the p-well region is 1×10 ¹⁸ -3×10 ¹⁸ cm ^-3 . The doping concentration at this level is high enough so that the potential barrier at the source end of the channel will not be reduced due to the voltage applied to the drain.

Further preferably, in order to avoid the threshold voltage being too high, the p-well region adopts a reverse doping distribution, with a low surface doping concentration and a high doping concentration deep below. Since silicon carbide is a wide bandgap semiconductor material, it has a larger PN junction built-in electric field. Silicon carbide can be used to make a normally-off accumulation channel MOSFET. Therefore, the doping concentration of the channel region is between 2×10 ¹⁶ cm ^-3 for n-type doping and 5×10 ¹⁶ cm ^-3 for p-type doping.

(5) Next, a uniform thin dielectric silicon nitride layer is deposited and carpet-etched to the same thickness to form a uniform thin dielectric silicon nitride spacer on the sidewall of the second hard mask layer in the p-well region in this step; the dielectric silicon nitride spacer is used to realize the self-aligned channel of the MOSFET; n-type implantation is performed to form the n+ region; the p+ region metal layer is above the p+ region and can block ions from entering the p+ region when the n-type ion implantation is performed in the n+ region. This is because the doping concentration of the n+ region is about ten times higher than the doping concentration of the p+ region.

Preferably, in step (5), the ions used to make the n+ region are nitrogen ions; the peak concentration of the n+ region should be above 1×10 ²⁰ cm ^-3 ; the thickness of the dielectric silicon nitride spacer layer should not exceed 0.5 μm to form a shorter channel not exceeding 0.5 μm, thereby reducing the resistance of the channel region and thereby reducing the on-resistance of the device.

(6) removing the dielectric silicon nitride spacer layer and the second hard mask layer in step (5) on the surface of the wafer, and then forming a third hard mask layer of sufficient thickness, and using a mask to etch a junction termination area window; performing p-type ion implantation to form the junction termination area, and removing the third hard mask layer of this step on the surface of the wafer after the implantation is completed.

Preferably, in step (6), the composition of the third hard mask layer from bottom to top includes the following selections:

a. Ion implantation barrier layer (e.g. silicon dioxide layer), oxide layer (e.g. silicon dioxide);

b. Ion implantation barrier layer (e.g. silicon dioxide layer), polysilicon layer;

c. Ion implantation barrier layer (e.g. silicon dioxide layer), polysilicon layer, metal layer (e.g. nickel, titanium, gold, copper, chromium, aluminum);

d. ion implantation barrier layer (e.g. silicon dioxide layer), polysilicon layer, oxide layer (e.g. silicon dioxide layer);

e. Ion implantation barrier layer (such as silicon dioxide layer), polysilicon layer, oxide layer (such as silicon dioxide layer), metal layer (such as nickel, titanium, gold, copper, chromium, aluminum).

Preferably, in step (6), the ions used to make the junction termination region are aluminum ions.

(7) Next, a cap layer is deposited and annealed in an inert gas atmosphere to activate the implanted ions and enable the p+ region metal layer to form an ohmic contact with the p+ region; after the annealing is completed, the cap layer is removed.

Preferably, in step (7), the cap layer component is carbon; the inert gas is nitrogen or argon; the annealing temperature is between 1500° C. and 1900° C., and the annealing time is between 8 and 15 minutes.

(8) The standard MOSFET manufacturing process is then used for subsequent manufacturing. First, the wafer surface after the above steps is cleaned; a gate oxide layer is formed by thermally oxidizing silicon carbide and annealing; a layer of n-type doped gate polysilicon is deposited, and the gate region is etched out using a mask; a layer of dielectric layer is deposited, and a window for the source region is etched out using a mask; a layer of source metal is sputtered and annealed to form an ohmic contact between the source metal layer and the n+ region; the top metal layer is evaporated and the source region is etched out using a mask; back-side scribing, cleaning, and substrate thinning processes are performed, and an ohmic contact and electrode are formed on the back side.

Preferably, in step (8), the source metal includes nickel, titanium, tungsten, tantalum, molybdenum, aluminum or alloys thereof; and the top metal layer is composed of aluminum.

The beneficial effects of the present invention are:

The present invention first implants a p+ region and forms a metal hard mask in the p+ region for blocking nitrogen ion implantation, and uses a channel self-alignment process to form an n+ region. During the process of annealing to activate the implanted ions, the metal hard mask above the p+ region forms an ohmic contact on the silicon carbide surface. The present invention simplifies the process steps of silicon carbide planar gate MOSFET, reduces the use of masks in the process, and saves process costs and time costs in the manufacturing process.

BRIEF DESCRIPTION OF THE DRAWINGS

1 is a schematic cross-sectional view of a complete semiconductor device formed by a method according to an embodiment of the present invention;

FIG2 is a schematic cross-sectional view of a starting wafer;

3 is a schematic cross-sectional view of a semiconductor device after a p+ region is formed according to a method of an embodiment;

4 is a schematic cross-sectional view of a semiconductor device after the metal layer is formed according to the method of an embodiment;

5 is a schematic cross-sectional view of a semiconductor device after a p-well region is formed according to a method of an embodiment;

6 is a schematic cross-sectional view of a semiconductor device after an n+ region is formed according to a method of an embodiment;

7 is a schematic cross-sectional view of a semiconductor device after a junction termination region is formed according to a method of an embodiment;

Wherein: 1. substrate, 2. epitaxial layer, 3. CSL layer, 4. mark groove, 5. first hard mask layer, 6. p+ region injection window, 7. p+ region, 8. p+ region metal layer, 9. second hard mask layer, 10. p well region window, 11. p well region, 12. dielectric silicon nitride spacer layer, 13. n+ region, 14. third hard mask layer, 15. junction termination region window, 16. junction termination region, 17. gate oxide layer, 18. gate polysilicon, 19. dielectric layer, 20. source metal, 21. top metal layer.

DETAILED DESCRIPTION

The present invention will be further described below by way of embodiments in conjunction with the accompanying drawings, but is not limited thereto.

Figure 1 shows a cross-sectional view of a silicon carbide MOSFET according to the manufacturing method of the present invention. Figures 2-7 describe the various steps of the manufacturing process of a MOSFET with different ohmic contacts of the present invention.

In order to promote the understanding of the principles of the present invention, reference will now be made to the embodiments shown in the accompanying drawings, and specific language will be used to describe them. However, it should be understood that the following description of the embodiments is only intended to provide a better understanding of the present application by illustrating examples of the present application. In the drawings and the following description, at least some of the well-known structures and technologies are not shown in order to avoid unnecessary ambiguity in the present application; and, for clarity, the sizes of some structures may be exaggerated. In addition, the features, structures, or characteristics described below may be combined in one or more embodiments in any suitable manner.

Embodiment 1:

A silicon carbide planar gate power MOSFET, as shown in FIG1 , comprises, from bottom to top, a substrate 1, an epitaxial layer 2, and a CSL layer 3, a p-well region 11 is produced by implantation on the CSL layer, a p+ region 7 and a p+ region metal layer 8 are provided in the middle of the p-well region from bottom to top, n+ regions 13 are implanted on the upper surface of the p-well region on both sides of the p+ region, a junction termination region 16 is implanted on the CSL layer next to the p-well region, and the junction termination region is connected to one side of the p-well region.

A gate oxide layer 17 and a gate polysilicon 18 are arranged in sequence above the CSL layer on the p+ region side (as shown on the left side in Figure 1), and the two cover part of the CSL layer, part of the p-well region, and part of the n+ region; a dielectric layer 19 is arranged above and on the side of the gate polysilicon, and a source metal 20 is arranged next to the dielectric layer, and the source metal covers part of the n+ region and part of the p+ region metal layer; a dielectric layer 19 is arranged next to the source metal, and the dielectric layer covers part of the p+ region metal layer, the n+ region, part of the p-well region, and the junction terminal region.

A top metal layer 21 is disposed above the dielectric layer 19 and the source metal 20 on both sides.

A marking groove 4 is etched on the CSL layer beside the junction termination region 16 , and the marking groove is not covered by any material.

The present invention optimizes the manufacturing process of silicon carbide MOSFET by first performing p+ implantation, and provides a DMOS manufacturing process in which n+ source implantation and p base implantation are self-aligned, eliminating the need for such alignment tolerance. The p+ region 7 is ohmically contacted by the first metal 8. The n+ region 13 is ohmically contacted by the second source metal 20. As shown in the figure, the first additional p-well region 11 and the junction termination region (JTE) 16 are formed at the edge of the device.

Embodiment 2:

A method for preparing the silicon carbide planar gate power MOSFET described in Example 1 comprises the following steps:

(1) As shown in FIG. 2 , an n-type epitaxial layer 2 and a CSL layer 3 are grown on a substrate 1; then a marking groove 4 is etched on the surface of the wafer.

The substrate is a 4H-SiC n-type heavily doped low resistivity substrate with a resistivity of 0.015~0.025Ω·cm; the n-type epitaxial layer is lightly doped with a doping concentration of 1×10 ¹⁵ cm ^-3 ~1×10 ¹⁶ cm ^-3 ; and the CSL layer doping concentration is 2×10 ¹⁶ -1×10 ¹⁷ cm ^-3 .

(2) As shown in FIG3 , a first hard mask layer 5 of sufficient thickness is formed on the surface of the wafer, and the first hard mask layer is etched using a mask to expose a window for ion implantation in the p+ region. The marking groove 4 is self-aligned with the p+ region implantation window 6, thereby saving a 1 μm registration tolerance; p-type (e.g., aluminum ion) implantation is performed to form the p+ region 7.

The composition of the first hard mask layer from bottom to top includes the following options:

a. Ion implantation barrier layer (e.g. silicon dioxide layer), oxide layer (e.g. silicon dioxide);

b. Ion implantation barrier layer (e.g. silicon dioxide layer), polysilicon layer;

c. Ion implantation barrier layer (e.g. silicon dioxide layer), polysilicon layer, metal layer (e.g. nickel, titanium, gold, copper, chromium, aluminum);

d. ion implantation barrier layer (e.g. silicon dioxide layer), polysilicon layer, oxide layer (e.g. silicon dioxide layer);

e. Ion implantation barrier layer (such as silicon dioxide layer), polysilicon layer, oxide layer (such as silicon dioxide layer), metal layer (such as nickel, titanium, gold, copper, chromium, aluminum).

The ions used to make the p+ region are aluminum ions, and the doping concentration of the p+ region should have a peak concentration of 1×10 ¹⁹ -5×10 ¹⁹ cm ^-3 to ensure the formation of a good ohmic contact.

(3) As shown in FIG. 4 , after the implantation of the p+ region 7 is completed, a p+ region metal layer 8 is sputtered, annealed, and the unreacted metal is washed away using a dilute sulfuric acid-hydrogen peroxide solution.

The composition of the p+ region metal layer may include nickel, titanium, tungsten, tantalum, molybdenum or alloys thereof.

Annealing is performed at a temperature above 450° C. for at least 30 seconds. The thickness of the metal layer should be sufficient to block nitrogen ions injected into the n+ region and should not be less than 0.5 μm.

(4) As shown in FIG. 5 , the first hard mask layer 5 in step (3) is removed from the surface, and a second hard mask layer 9 of sufficient thickness is formed, and a mask is used to etch a p-well region window 10, and the ion implantation barrier layer of the second hard mask layer is etched. P-type implantation is performed to form a p-well region 11. The thickness of the ion implantation barrier layer is generally the same, and the implantation height of the p-well region is flush with the CSL layer and lower than the metal layer.

Similar to step (2), the second hard mask layer comprises the following from bottom to top:

a. Ion implantation barrier layer (e.g. silicon dioxide layer), oxide layer (e.g. silicon dioxide);

b. Ion implantation barrier layer (e.g. silicon dioxide layer), polysilicon layer;

c. Ion implantation barrier layer (e.g. silicon dioxide layer), polysilicon layer, metal layer (e.g. nickel, titanium, gold, copper, chromium, aluminum);

d. ion implantation barrier layer (e.g. silicon dioxide layer), polysilicon layer, oxide layer (e.g. silicon dioxide layer);

e. Ion implantation barrier layer (such as silicon dioxide layer), polysilicon layer, oxide layer (such as silicon dioxide layer), metal layer (such as nickel, titanium, gold, copper, chromium, aluminum).

The ions used to make the p-well region are aluminum ions; in order to achieve a sufficient breakdown voltage, the doping concentration of the p-well region is 1×10 ¹⁸ -3×10 ¹⁸ cm ^-3 . The doping concentration at this order of magnitude is high enough so that the potential barrier at the source end of the channel will not be reduced by the voltage applied to the drain.

In order to avoid the threshold voltage being too high, the p-well region adopts a reverse doping distribution, with low surface doping concentration and high doping concentration deep below. Since silicon carbide is a wide bandgap semiconductor material, it has a larger PN junction built-in electric field. Silicon carbide can be used to make normally-off accumulation-channel MOSFETs. Therefore, the doping concentration of the channel region is between 2×10 ¹⁶ cm ^-3 for n-type doping and 5×10 ¹⁶ cm ^-3 for p-type doping.

(5) Next, as shown in FIG6 , a uniform thin dielectric silicon nitride layer is deposited, and carpet etching is performed to the same thickness to form a uniform thin dielectric silicon nitride spacer 12 on the sidewall of the second hard mask layer 9 in the p-well region in this step; the dielectric silicon nitride spacer is used to realize the self-aligned channel of the MOSFET; n-type implantation is performed to form the n+ region 13; the p+ region metal layer is above the p+ region, which can block the ions from entering the p+ region when the n-type ion implantation is performed in the n+ region. This is because the doping concentration of the n+ region is about ten times higher than the doping concentration of the p+ region.

The ions used to make the n+ region are nitrogen ions; the peak concentration of the n+ region should be above 1×10 ²⁰ cm ^-3 ; the thickness of the dielectric silicon nitride spacer should not exceed 0.5 μm to form a shorter channel not exceeding 0.5 μm, reduce the resistance of the channel region, and further reduce the on-resistance of the device.

(6) The dielectric silicon nitride spacer layer 12 and the second hard mask layer 9 in step (5) are removed from the wafer surface, as shown in FIG. 7 , and a third hard mask layer 14 of sufficient thickness is formed, and a junction termination region window 15 is etched using a mask; p-type ion implantation is performed to form a junction termination region 16, and after the implantation is completed, the third hard mask layer 14 of this step on the wafer surface is removed.

Similar to steps (2) and (4), the composition of the third hard mask layer from bottom to top includes the following options:

a. Ion implantation barrier layer (e.g. silicon dioxide layer), oxide layer (e.g. silicon dioxide);

b. Ion implantation barrier layer (e.g. silicon dioxide layer), polysilicon layer;

c. Ion implantation barrier layer (e.g. silicon dioxide layer), polysilicon layer, metal layer (e.g. nickel, titanium, gold, copper, chromium, aluminum);

d. ion implantation barrier layer (e.g. silicon dioxide layer), polysilicon layer, oxide layer (e.g. silicon dioxide layer);

e. Ion implantation barrier layer (such as silicon dioxide layer), polysilicon layer, oxide layer (such as silicon dioxide layer), metal layer (such as nickel, titanium, gold, copper, chromium, aluminum).

The ions used to make the junction termination region are aluminum ions.

(7) Next, a cap layer is deposited and annealed in an inert gas atmosphere to activate the implanted ions and enable the p+ region metal layer to form an ohmic contact with the p+ region; after the annealing is completed, the cap layer is removed.

The cap layer is composed of carbon; the inert gas is nitrogen or argon; the annealing temperature is between 1500°C and 1900°C, and the time is between 8 and 15 minutes.

(8) As shown in FIG1 , the subsequent manufacturing is carried out through the standard MOSFET manufacturing process. First, the wafer surface after the above steps is cleaned; a gate oxide layer 17 is formed by thermally oxidizing silicon carbide and annealing; a layer of n-type doped gate polysilicon 18 is deposited, and the gate region is etched out using a mask; a layer of dielectric layer (PMD) 19 is deposited, and a window of the source region is etched out using a mask; a layer of source metal 20 is sputtered and annealed to form an ohmic contact between the source metal layer and the n+ region; the top metal layer 21 is evaporated and the source region is etched out using a mask; back side scribing, cleaning and substrate thinning processes are performed, and ohmic contacts and electrodes are formed on the back side.

The source metal options include: nickel, titanium, tungsten, tantalum, molybdenum, aluminum or their alloys; the top metal layer is composed of aluminum.

Claims (10)

1. The silicon carbide planar gate power MOSFET is characterized in that a p-well region is manufactured by injecting the substrate, an epitaxial layer and a CSL layer from bottom to top, a p+ region and a p+ region metal layer are arranged in the middle of the p-well region from bottom to top, an n+ region is manufactured by injecting the upper surfaces of the p-well regions at two sides of the p+ region, a junction terminal region is manufactured by injecting the CSL layer beside the p-well region, and the junction terminal region is connected with one side of the p-well region;

A grid oxide layer and grid polysilicon are sequentially arranged above the CSL layer at one side of the p+ region, and cover part of the CSL layer, part of the p-well region and part of the n+ region; dielectric layers are arranged above and on the side surfaces of the grid polycrystalline silicon, source metal is arranged beside the dielectric layers, and the source metal covers part of the n+ region and part of the p+ region metal layer; a dielectric layer is arranged beside the source electrode metal, and covers part of the p+ region metal layer, the n+ region, part of the p well region and the junction terminal region;

a top metal layer is arranged above the dielectric layer and the source metal;

the CSL layer beside the junction termination region is etched with a marker trench that is not covered by any material.

2. The manufacturing method of the silicon carbide planar gate power MOSFET is characterized by comprising the following steps:

(1) Growing an n-type epitaxial layer and a CSL layer on a substrate; then etching a marking groove on the surface of the wafer;

(2) Manufacturing a first hard mask layer on the surface of the wafer, and etching the first hard mask layer by using a mask plate to expose a window for p+ region ion implantation; self-aligning with the p+ region implantation window through the mark slot; p-type implantation is carried out to manufacture a p+ region;

(3) After the injection of the p+ region is completed, sputtering a metal layer of the p+ region, annealing, and washing off unreacted metal by using a dilute sulfuric acid hydrogen peroxide solution;

(4) Removing the first hard mask layer in the step (3) on the surface, manufacturing a second hard mask layer, and etching a p-well region window by using a mask plate; p-type implantation is carried out to manufacture a p-well region;

(5) Depositing a uniform dielectric silicon nitride layer, and performing carpet etching with the same thickness to form a uniform dielectric silicon nitride spacer layer on the side wall of the second hard mask layer of the p-well region in the step; the dielectric silicon nitride spacer layer is used for realizing a self-aligned channel of the MOSFET; performing n-type implantation to manufacture an n+ region;

(6) Removing the dielectric silicon nitride spacer layer and the second hard mask layer in the step (5) on the surface of the wafer, then manufacturing a third hard mask layer, and etching a junction terminal area window by using a mask plate; performing p-type ion implantation to manufacture a junction terminal region, and removing the third hard mask layer of the step on the surface of the wafer after the implantation is finished;

(7) Next, depositing a cap layer, and annealing in an inert gas atmosphere to activate the implanted ions and enable the p+ region metal layer to form ohmic contact with the p+ region; removing the cap layer after the annealing is finished;

(8) The subsequent manufacturing is carried out through a standard MOSFET manufacturing process; firstly, cleaning the surface of the wafer after the steps; forming a gate oxide layer by thermally oxidizing silicon carbide and annealing; depositing a layer of n-type doped gate polysilicon and etching a gate region by using a mask plate; depositing a dielectric layer and etching a window of the source region by using a mask; sputtering a layer of source metal and annealing to form ohmic contact between the source metal layer and the n+ region; evaporating the top metal layer and etching the source electrode region by using a mask plate; and ohmic contacts and electrodes are formed on the back side.

3. The method of fabricating a silicon carbide planar gate power MOSFET according to claim 2, wherein in steps (2), (4), and (6), the composition of the first hard mask layer, the second hard mask layer, and the third hard mask layer from bottom to top comprises the following selection:

a. ion implantation barrier layer, oxide layer;

b. ion implantation barrier layer, polycrystalline silicon layer;

c. Ion implantation barrier layer, polysilicon layer, metal layer;

d. an ion implantation barrier layer, a polysilicon layer, and an oxide layer;

e. Ion implantation barrier layer, polysilicon layer, oxide layer, and metal layer.

4. The method of fabricating a silicon carbide planar gate power MOSFET according to claim 3, wherein in steps (2) and (4), the p+ region implantation window and the p-well region window are etched into the ion implantation barrier layers of the first hard mask layer and the second hard mask layer; the ion implantation barrier layer is a silicon dioxide layer, the oxide layer is a silicon dioxide layer, and the metal layer is made of nickel, titanium, gold, copper, chromium and aluminum.

5. The method of fabricating a silicon carbide planar gate power MOSFET according to claim 2, wherein in step (1), the substrate is a 4H-SiC n-type heavily doped low resistivity substrate having a doping concentration of 1 x 10 ¹⁹cm^-3; lightly doping the n-type epitaxial layer, wherein the doping concentration is 1 multiplied by 10 ¹⁶cm^-3; the CSL layer doping concentration was 2×10 ¹⁶-1×10¹⁷cm^-3.

6. The method of fabricating a silicon carbide planar gate power MOSFET according to claim 2, wherein in step (2), the ions forming the p+ region are aluminum ions, and the doping concentration of the p+ region is 1 x 10 ¹⁹-5×10¹⁹cm^-3; in the step (4), the ions for manufacturing the p-well region are aluminum ions, the p-well region adopts counter doping distribution, the surface doping concentration is low, and the deep doping concentration below is high; the doping concentration of the p-well region is 1×10 ¹⁸-3×10¹⁸cm ^-3; in the step (6), the ion forming the junction termination region is aluminum ion.

7. The method of fabricating a silicon carbide planar gate power MOSFET according to claim 2, wherein in step (3), the composition selection of the p+ region metal layer comprises: nickel, titanium, tungsten, tantalum, molybdenum or alloys thereof; in step (8), the selecting of the source metal includes: nickel, titanium, tungsten, tantalum, molybdenum, aluminum or alloys thereof; the top metal layer is made of aluminum.

8. The method of fabricating a silicon carbide planar gate power MOSFET according to claim 2, wherein in step (3), the annealing is performed at a temperature of 450 ℃ or higher for at least 30 seconds, and the thickness of the metal layer is not less than 0.5 μm.

9. The method of fabricating a silicon carbide planar gate power MOSFET according to claim 2, wherein in step (5), the ions forming the n+ region are nitrogen ions; the peak concentration of the n+ region is more than 1×10 ²⁰cm^-3; the thickness of the dielectric silicon nitride spacer is no more than 0.5 μm.

10. The method of fabricating a silicon carbide planar gate power MOSFET according to claim 2, wherein in step (7), the cap layer composition is carbon; the inert gas is nitrogen or argon; the annealing temperature is 1500-1900 ℃ and the annealing time is 8-15 minutes.