CN114002577B - Chip testing method, device, equipment and readable storage medium - Google Patents
Chip testing method, device, equipment and readable storage medium Download PDFInfo
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Abstract
The application discloses a chip testing method, a device, equipment and a readable storage medium. The application divides the chip to be tested into a plurality of subsystems, divides each subsystem into a plurality of modules and divides all the modules into a plurality of sets, selects test pins for each module in the set nearby based on the physical position of each module in the set in the chip to be tested, and tests each module in the set in parallel based on the selected test pins, thereby testing the module with smaller granularity, having shorter scanning path, reducing the difficulty of physical wiring, realizing the time-sharing multiplexing of the chip pins and reducing the test cost. Correspondingly, the chip testing device, the chip testing equipment and the readable storage medium have the technical effects.
Description
Technical Field
The present application relates to the field of computer chip testing technologies, and in particular, to a chip testing method, device, apparatus, and readable storage medium.
Background
Currently, the number of transistors integrated on a single chip ranges from millions to tens of millions, up to billions, and the chip functions more and more, so too does the number of modules to be tested.
Thousands of scan chains in a chip can be currently compressed into several or tens of scan chains based on the EDT compression scan chain technology to alleviate the shortfall of chip test pins. However, in one scan chain, the input test pins and the output test pins span multiple modules, so that the scan path is long, which not only brings great challenges to the convergence of the test timing, but also reduces the test efficiency, and makes the physical wiring required by the test difficult.
Therefore, how to shorten the scan path and reduce the physical wiring difficulty is a problem that needs to be solved by those skilled in the art.
Disclosure of Invention
In view of the above, the present application is directed to a method, an apparatus, a device and a readable storage medium for chip testing, which can shorten a scan path and reduce a physical wiring difficulty. The specific scheme is as follows:
in a first aspect, the present application provides a chip testing method, including:
dividing a chip to be tested into a plurality of subsystems;
dividing each subsystem into a plurality of modules, and dividing all the modules into a plurality of sets;
selecting test pins for each module in any set nearby based on the physical position of each module in the set in the chip to be tested, and testing each module in the set in parallel based on the selected test pins;
wherein the total number of test pins required by all modules in any one set is not greater than the total number of pins of the chip to be tested.
Preferably, the chip under test and each subsystem are partitioned according to logic independence.
Preferably, the testing each module in the set based on the selected test pins in parallel includes:
If the modules with the same functions exist in the set, the same test stimulus is input to the modules with the same functions in parallel.
Preferably, the parallel input of the same test stimulus to the modules of the same function comprises:
and the same test stimulus is input to the modules with the same functions in parallel by adopting a broadcast structure.
Preferably, before the parallel testing of each module in the set based on the selected test pin, the method further comprises:
the interface registers of each module are configured based on WRAPPER CHAIN's internal test patterns to isolate the different modules.
Preferably, the testing each module in the set based on the selected test pins in parallel includes:
the selected test pins are controlled by a multiplexer selector to test the modules in the set in parallel.
Preferably, after selecting a test pin for each module in any set nearby based on the physical position of each module in the set in the chip to be tested, and testing each module in the set in parallel based on the selected test pin, the method further includes:
Determining at least two modules requiring testing module connection boundaries in the set, and configuring interface registers of the at least two modules by adopting an external test mode of WRAPPER CHAIN so as to communicate the at least two modules;
The module connection boundary is tested based on any one of the at least two modules that are connected.
In a second aspect, the present application provides a chip testing apparatus, comprising:
the first dividing module is used for dividing the chip to be detected into a plurality of subsystems;
the second dividing module is used for dividing each subsystem into a plurality of modules and dividing all the modules into a plurality of sets;
The testing module is used for aiming at any set, selecting testing pins for each module in the set nearby based on the physical position of each module in the set in the chip to be tested, and testing each module in the set in parallel based on the selected testing pins;
wherein the total number of test pins required by all modules in any one set is not greater than the total number of pins of the chip to be tested.
In a third aspect, the present application provides an electronic device, comprising:
a memory for storing a computer program;
and a processor for executing the computer program to implement the chip testing method disclosed above.
In a fourth aspect, the present application provides a readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the previously disclosed chip test method.
According to the scheme, the chip testing method comprises the steps of dividing a chip to be tested into a plurality of subsystems, dividing each subsystem into a plurality of modules and dividing all the modules into a plurality of sets, aiming at any set, selecting test pins for each module in the set nearby based on the physical position of each module in the set in the chip to be tested, and testing each module in the set in parallel based on the selected test pins, wherein the total number of the test pins required by all the modules in any set is not more than the total number of pins of the chip to be tested.
The application divides the chip to be tested into a plurality of subsystems, divides each subsystem into a plurality of modules and divides all the modules into a plurality of sets, and aiming at any set, based on the physical position of each module in the set in the chip to be tested, selects test pins for each module in the set nearby and tests each module in the set in parallel based on the selected test pins so as to test the module with smaller granularity. Because the test pins are selected for each module nearby, the scanning path is shorter when each module is tested, and the physical wiring difficulty is reduced. Meanwhile, the total number of test pins required by all modules in one set is not more than the total number of pins of the chip to be tested, and all the modules are tested in parallel, so that the test efficiency can be improved, and all the pins of the chip to be tested can be utilized as much as possible. Each set is tested according to the method, time-sharing multiplexing of chip pins can be achieved, and testing cost is reduced.
Correspondingly, the chip testing device, the chip testing equipment and the readable storage medium have the technical effects.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present application, and that other drawings can be obtained according to the provided drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of a chip testing method disclosed by the application;
FIG. 2 is a schematic diagram of a scan path according to the present disclosure;
FIG. 3 is a schematic diagram of a scan chain corresponding to the scan path shown in FIG. 2;
FIG. 4 is a schematic diagram of a scan path across different modules according to the present disclosure;
FIG. 5 is a schematic diagram of a subsystem-based multiplexing chip pin according to the present disclosure;
FIG. 6 is a schematic diagram of another subsystem-based multiplexing chip pin disclosed in the present application;
FIG. 7 is a schematic diagram of a scan chain comprised by a single module of the present disclosure;
FIG. 8 is a schematic diagram of a chip testing apparatus according to the present disclosure;
Fig. 9 is a schematic diagram of an electronic device according to the present disclosure.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
For the convenience of description of the present application, the following description will be given with reference to the background art to which the present application relates.
Along with the rapid increase of the demands of industries such as artificial intelligence, data storage and the like on large-scale chips, the scale of SoC is exponentially increased, the number of transistors integrated on a single chip is millions to tens of millions, but the volume requirement on the chip is smaller and smaller, so that a serious challenge is brought to the test after the chip is manufactured, the stable promotion of a semiconductor process is realized, possible defects in the manufacturing process are more and more diversified and complicated, and more targeted test vectors are required to be developed according to physical manufacturing defects and corresponding fault models so as to ensure the quality of the chip.
The chip test is connected with pins of the chip through ATE (automatic Test Equipment ), test excitation is filled into the chip, after the chip responds, the response result is read, and the result is compared with the expected result, so that the quality of the chip is screened. The increase of the number of the pins of the chip is far smaller than the increase scale of logic in the chip, on the other hand, the number of the pins of the chip is affected by physical realization, and the smaller the number of the pins is, the better the number is on the premise of meeting the function requirement, so that no extra pins are designed for testing the chip, and therefore, the pins used in the chip test are mostly digital pins defined by multiplexing functions.
The compression scan chain technology provided by EDT (Embedded DETERMINISTIC TEST) can compress thousands of scan chains into several to tens of scan chains, so that the problem of insufficient number of chip test pins is effectively solved. However, as the chip scale increases further, the functional pins of the chip are not able to meet the current test requirements.
In addition, in one scan chain, the input test pins and the output test pins span across a plurality of modules, so that the scan path is long, not only is the convergence of the test timing brought with great challenges, the test efficiency is reduced, but also the physical wiring required by the test is difficult. Therefore, the application provides a chip test scheme which can shorten the scanning path and reduce the difficulty of physical wiring.
Referring to fig. 1, the embodiment of the application discloses a chip testing method, which comprises the following steps:
S101, dividing a chip to be tested into a plurality of subsystems.
S102, dividing each subsystem into a plurality of modules, and dividing all the modules into a plurality of sets.
It should be noted that, dividing a chip to be tested needs to consider the independence and interconnectivity of each functional module in the chip. If the function of a certain module is independent, it is indicated that the module can be tested alone. If the functions of two modules are related to each other, it is necessary to test whether the logic of the related part can run or not, in addition to separately testing the two modules.
Accordingly, such rules need to be followed between different subsystems. In one embodiment, therefore, the chip under test and each subsystem are partitioned according to logic independence.
The subsystems and the modules are divided based on the logic functions of the chip and correspond to corresponding physical devices on the chip. Therefore, each module on the chip to be tested is the data processing logic between the corresponding physical devices for realizing the module.
S103, aiming at any set, based on the physical position of each module in the set in the chip to be tested, selecting a test pin for each module in the set nearby, and testing each module in the set in parallel based on the selected test pin.
Since each module on the chip to be tested is essentially a test to implement the data processing logic between the corresponding physical devices of the module, the data processing logic between these physical devices needs to be tested by the corresponding pins of the connection chip. In order to shorten the scan path, the embodiment selects the test pins for each module nearby, so that the physical wiring difficulty required by the test can be reduced. As shown in fig. 2, the test pins (including the input pins and the output pins) of the module a are all near the module a, and the test pins of the module B are all near the module B, so that the difficulty of physical wiring is low.
In this embodiment, after a chip to be tested is divided into each module, the number of pins required for testing each module can be determined based on the testing requirements of each module, and since the pins on a chip to be tested are limited, the test needs to be performed in batches. For this reason, in this embodiment, all the modules are divided into several sets, and a test flow is performed in parallel for each module in one set.
Wherein the total number of test pins required by all modules in any one set is not greater than the total number of pins of the chip to be tested.
In order to make all pins of the chip to be tested as far as possible used in each test flow, all modules can be divided according to the total number of pins of the chip to be tested to obtain a set. I.e. the total number of test pins required for all modules in any one set is made equal to the total number of pins of the chip to be tested. Of course, the total number of test pins required by all modules in any set is smaller than the total number of pins of the chip to be tested, and only the idle chip pins exist when the corresponding set is tested, which is not beneficial to improving the test efficiency.
For example, a chip to be tested is provided with 10 pins, and 5 modules A, B, C, D, E are obtained by dividing the chip to be tested. Wherein, module A needs 2 test pins, module B needs 4 test pins, module C needs 6 test pins, module D needs 8 test pins, and module E needs 10 test pins. Then a and D can be divided into a set X, B and C into a set Y, and E can be independently a set Z. In this way, all pins of the chip are used when the sets X, Y, Z are tested respectively, so that the maximum utilization of the pins of the chip is realized, and meanwhile, the time-sharing multiplexing of the pins of the chip is realized by the test flows respectively corresponding to the sets X, Y, Z.
In general, a chip may not be provided with pins dedicated to testing, and then each functional pin of the chip may be defined as a test pin when testing the chip.
In one embodiment, testing each module in the set in parallel based on the selected test pins includes inputting the same test stimulus in parallel to the same functional module if the same functional module is present in the set. The module for inputting the same test stimulus to the same function in parallel comprises a module for inputting the same test stimulus to the same function in parallel by adopting a broadcast structure. The modules with the same functions are identical. The test stimulus is input data designed for testing the corresponding module. The input data is input through the input pins, and the response of the module to the input data is acquired from the corresponding output pins, so that whether the response meets the expectations can be judged.
It can be seen that the embodiment divides the chip to be tested into a plurality of subsystems, divides each subsystem into a plurality of modules and divides all the modules into a plurality of sets, and for any one set, selects test pins for each module in the set nearby based on the physical position of each module in the set in the chip to be tested, and tests each module in the set in parallel based on the selected test pins, thereby testing for modules with smaller granularity. Because the test pins are selected for each module nearby, the scanning path is shorter when each module is tested, and the physical wiring difficulty is reduced. Meanwhile, the total number of test pins required by all modules in one set is not more than the total number of pins of the chip to be tested, and all the modules are tested in parallel, so that the test efficiency can be improved, and all the pins of the chip to be tested can be utilized as much as possible. Each set is tested according to the method, time-sharing multiplexing of chip pins can be achieved, and testing cost is reduced.
Based on the above embodiment, it should be noted that, in one specific implementation, before testing each module in the set in parallel based on the selected test pins, configuring the interface register of each module based on the internal test mode of WRAPPER CHAIN to isolate the different modules is further included.
Based on the above embodiments, it should be noted that in one embodiment, testing each module in the set in parallel based on the selected test pin includes controlling the selected test pin with a multiplexer selector to test each module in the set in parallel. The multiplexer is used to control the corresponding test pins (including the input pins and the output pins) of each module, so as to determine which module uses which pins to test, see fig. 3.
The scan path corresponding to the module a in fig. 2 is expanded, so that fig. 3 can be obtained. As can be seen from fig. 3, the respective modules need to be tested with a corresponding arrangement of decompressors and compressors. Wherein, a plurality of modules can multiplex the same group of decompressors and compressors, or one module can use one group of decompressors and compressors. The use of a decompressor and a compressor can be referred to in the related art, and will not be described in detail herein.
Meanwhile, there may be multiple scan chains in a module, each scan chain running through N registers. The first register of a scan chain is called the head-of-chain register and the last register is called the tail-of-chain register. The scan path is used to indicate the run of the scan chain.
Based on the above embodiment, it should be noted that, in a specific implementation manner, for any set, after selecting a test pin for each module in the set based on a physical position of each module in the set in the chip to be tested, and testing each module in the set based on the selected test pin in parallel, the method further includes determining at least two modules requiring a connection boundary of the test module in the set, and configuring interface registers of the at least two modules to communicate with the at least two modules by adopting an external test mode of WRAPPER CHAIN, and testing the connection boundary of the module based on any module test pin in the communicated at least two modules.
Referring specifically to fig. 4, it can be seen from fig. 4 that the connection boundary between the module C and the module D, and the connection boundary between the module D and the module E all need to be tested. The prior art generally spans the scan path across module C, D, E with its input pins selected near module C and its output pins selected near module E, and the connection of test lines is not easy because of the physical locations of modules C and E on the chip.
The application adopts WRAPPER CHAIN external test mode to connect the module C and the module D, uses the pins near the module C as input pins and output pins, tests the connection boundary between the module C and the module D, then adopts WRAPPER CHAIN external test mode to connect the module D and the module E, uses the pins near the module E as input pins and output pins, tests the connection boundary between the module D and the module E, and completes the boundary test between the modules. Thus, not only can the scanning path be shortened, but also the wiring difficulty is reduced. Accordingly, testing may also be performed between different subsystems.
It should be noted that, since the compression ratio of the current EDT has reached one hundred or even two hundred, an excessively high compression ratio may result in a decrease in the efficiency of generating the ATPG (automatic TEST PATTERN Generation) vector, and the number of generated test vectors may also increase sharply, which may affect the vector Generation time and the chip test cost.
Therefore, the present embodiment uses a time-division multiplexing technique to time-division multiplex the function pins. Only the chip part subsystem or the implementation logic of the individual modules is tested in a certain period of time. And in another time period, testing logic of other subsystems in the other parts of the chip. The available test pins are doubled, and the problem of insufficient current test pins is effectively solved.
As shown in fig. 5, the system on chip is divided into 2 subsystems, the selection control register is controlled by the multiplexing selector, the input pin and the output pin are multiplexed to the subsystem 1 in a first test period, the scan test of the subsystem 1 is completed first, and the input pin and the output pin are multiplexed to the subsystem 2 in a second test period, and then the scan test of the subsystem 2 is completed. Of course, the pins used in any one test flow should not exceed the total number of chip pins.
If the whole chip is divided into three subsystems, namely subsystem 1, subsystem 2 and subsystem 3, two subsystems can be selected for parallel testing in the first period of testing, and the rest subsystems are tested after the two subsystems are tested in parallel. Of course, the pins used in any one test flow should not exceed the total number of chip pins.
Because of the large number of modules in a subsystem, testing a subsystem may require traversing multiple modules, resulting in longer scan chains and inflexible choice of pins used for testing.
In this regard, in this embodiment, after the whole chip adopts the sub-system division, the sub-module division scheme is used to perform the grouping test, so as to achieve the goal of high coverage rate and few test pins under the condition of meeting the test requirement. In this embodiment, the standard logic unit of the subsystem is further divided into different modules according to the requirements of functions and physical implementation, and the modules are used as test units to perform time-sharing test on the different modules of the subsystem.
Specifically, the scan chain of the modules is taken as a compression object, a compressor and a decompressor are added to each module, and a scan channel formed between the compressor and the decompressor is connected to pins nearby the module. As shown in fig. 2, the scan path is only within a single module, not across different sub-modules. If a test module boundary is desired, this is done with reference to FIG. 4 and the corresponding description above.
If there are pin 1, pin 2, pin 3 and pin 4 on a chip, and the chip is divided into subsystem 1 (including module AB), subsystem 2 (including module CDE), subsystem 3 (including module FG) as shown in fig. 6. Then for the first test scan path 1 and scan path 2 of subsystem 1, scan path 7 and scan path 8 of subsystem 3 use these pins. After the test is finished, the pins are multiplexed by the scanning paths 3, 4, 5 and 6 of the subsystem 2. Thus, the maximum utilization and multiplexing of pins are realized.
It should be noted that, when the subsystems and the modules are divided, the independence and the interactivity of the tests of the subsystems or the sub-modules need to be fully considered, and the test requirements of each subsystem and each sub-module are balanced as much as possible, so that the effective multiplexing rate of the pins can be maximized when the pins are multiplexed in a time-sharing manner. As shown in fig. 6, all pins are used as much as possible in each test flow, while all pins are multiplexed as much as possible in a different test flow to maximize the pin multiplexing rate.
Thus, the interface sequential logic units (i.e., interface registers) of a subsystem or sub-module are configured in a WRAPPER CHAIN manner.
Taking the module D shown in fig. 6 as an example, when designing the scan chain, for the sequential logic of the interface portion of the module D, one or several input/output WRAPPER CHAIN are individually connected, so that WRAPPER CHAIN plays a role of isolating each subsystem or sub-module.
As shown in fig. 7, sequential logic cells associated with the module D interface are individually chained into input and output scan chains. At the time of the module internal test, WRAPPER CHAIN is used only as a shift register or a capture register by controlling the internal test mode of WRAPPER CHAIN. The external test mode by control WRAPPER CHAIN only checks WRAPPER CHAIN when testing different module boundaries or different subsystem boundaries, which facilitates vector generation and testing of larger scale chips.
The embodiment can flexibly configure and reuse the test pins, the test scale and the test unit division are smaller, the scanning path can be shortened, and the timing sequence convergence difficulty is reduced. For a chip with larger logic scale and area, the scanning path can be shortened by almost half, and the time sequence improvement effect is particularly obvious. By adopting WRAPPER CHAIN, the test coverage rate can be effectively improved, and the test time can be reduced.
Therefore, the embodiment not only can realize compression of the scan chain, but also has the main effect of planning the optimal compression scan channel length according to the physical placement position of the chip pins by adopting a time-sharing multiplexing technology for complex large-scale design, so as to relieve the bottleneck of mutual restriction between the number of the chip pins and the test time, reduce the compression ratio and relieve the problems of wire winding blockage in the EDT and difficult wiring of the top layer of the chip. Meanwhile, the test grouping of the subsystem is further refined, multiplexing pins are reasonably configured, a scanning path is optimized, and the timing sequence convergence difficulty is reduced.
In addition, for sub-modules or sub-systems with multiple multiplexing, when the test tube foot multiplexing scheme is determined, the shared data channel can be considered, namely, the same sub-modules or sub-systems are simultaneously tested with the same stimulus by adopting a broadcast structure so as to meet the use requirement of the quantity of the pins.
The following describes a chip testing apparatus according to an embodiment of the present application, and the chip testing apparatus described below and the chip testing method described above may be referred to each other.
Referring to fig. 8, an embodiment of the present application discloses a chip testing apparatus, including:
A first dividing module 801, configured to divide a chip to be tested into a plurality of subsystems;
a second dividing module 802 for dividing each subsystem into a plurality of modules and dividing all the modules into a plurality of sets;
a test module 803, configured to, for any one set, select a test pin for each module in the set nearby based on a physical position of each module in the set in the chip to be tested, and test each module in the set in parallel based on the selected test pin;
Wherein the total number of test pins required by all modules in any one set is not greater than the total number of pins of the chip to be tested.
In one embodiment, the test module is specifically configured to:
If there are modules with the same function in the set, the same test stimulus is input in parallel to the modules with the same function.
In one embodiment, the test module is specifically configured to:
the broadcast structure is adopted to input the same test stimulus to the modules with the same functions in parallel.
In one specific embodiment, the method further comprises:
A first configuration module for configuring the interface registers of each module based on the WRAPPER CHAIN internal test modes to isolate the different modules.
In one embodiment, the test module is specifically configured to:
the selected test pins are controlled by a multiplexer selector to test the modules in the set in parallel.
In one specific embodiment, the method further comprises:
The second configuration module is used for determining at least two modules needing to test the module connection boundary in the set, adopting WRAPPER CHAIN external test mode to configure interface registers of the at least two modules so as to communicate the at least two modules, and testing the module connection boundary based on any module test pin of the communicated at least two modules.
The more specific working process of each module and unit in this embodiment may refer to the corresponding content disclosed in the foregoing embodiment, and will not be described herein.
Therefore, the embodiment provides a chip testing device, which tests a module with smaller granularity, has a shorter scanning path, reduces the difficulty of physical wiring, can realize time-sharing multiplexing of chip pins, and reduces testing cost.
The following describes an electronic device provided by an embodiment of the present application, and the electronic device described below and the method and apparatus for testing a chip described above may be referred to each other.
Referring to fig. 9, an embodiment of the present application discloses an electronic device, including:
A memory 901 for storing a computer program;
A processor 902 for executing the computer program to implement the method disclosed in any of the embodiments above.
The following describes a readable storage medium according to an embodiment of the present application, and the readable storage medium described below and the method, apparatus and device for testing a chip described above may be referred to with each other.
A readable storage medium storing a computer program, wherein the computer program when executed by a processor implements the chip test method disclosed in the foregoing embodiments. For specific steps of the method, reference may be made to the corresponding contents disclosed in the foregoing embodiments, and no further description is given here.
The references to "first," "second," "third," "fourth," etc. (if present) are used to distinguish similar objects from each other and are not necessarily used to describe a particular order or sequence. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments described herein may be implemented in other sequences than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed or inherent to such process, method, or apparatus.
It should be noted that the description of "first", "second", etc. in this disclosure is for descriptive purposes only and is not to be construed as indicating or implying a relative importance or implying an indication of the number of technical features being indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions of the embodiments may be combined with each other, but it is necessary to base that the technical solutions can be realized by those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should be considered to be absent and not within the scope of protection claimed in the present application.
In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, so that the same or similar parts between the embodiments are referred to each other.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. The software modules may be disposed in Random Access Memory (RAM), memory, read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of readable storage medium known in the art.
While the principles and embodiments of the present application have been described in detail in this application, the foregoing embodiments are provided to facilitate understanding of the principles and concepts of the application and are further provided by one of ordinary skill in the art to which the application pertains.
Claims (8)
1. A method of testing a chip, comprising:
dividing a chip to be tested into a plurality of subsystems;
Dividing each subsystem into a plurality of modules, and dividing all the modules into a plurality of sets; the method comprises the steps of dividing a chip to be tested, considering the independence and the interconnectivity of each functional module in the chip, independently testing the module if the function of one module is independent, and independently testing whether the logic of the two modules can run through or not if the functions of the two modules are related to each other except the two modules, wherein the chip to be tested is divided into the chip to be tested and each subsystem according to the logic independence;
Selecting test pins for each module in any set nearby based on the physical position of each module in the set in the chip to be tested, and testing each module in the set in parallel based on the selected test pins; if no special pins for testing are provided, each functional pin is a test pin, and a decompressor and a compressor are correspondingly arranged when each module is tested;
the total number of test pins required by all modules in any one set is not more than the total number of pins of the chip to be tested;
the method further comprises the steps of, for any one set, selecting test pins for each module in the set nearby based on the physical position of each module in the set in the chip to be tested, and after parallel testing each module in the set based on the selected test pins:
Determining at least two modules requiring testing module connection boundaries in the set, and configuring interface registers of the at least two modules by adopting an external test mode of WRAPPER CHAIN so as to communicate the at least two modules;
The module connection boundary is tested based on any one of the at least two modules that are connected.
2. The method of claim 1, wherein the testing each module in the set in parallel based on the selected test pins comprises:
If the modules with the same functions exist in the set, the same test stimulus is input to the modules with the same functions in parallel.
3. The chip testing method according to claim 2, wherein the parallel input of the same test stimulus to the same functional module comprises:
and the same test stimulus is input to the modules with the same functions in parallel by adopting a broadcast structure.
4. The method of claim 1, further comprising, prior to testing each module in the set in parallel based on the selected test pins:
the interface registers of each module are configured based on WRAPPER CHAIN's internal test patterns to isolate the different modules.
5. The method of claim 1, wherein the testing each module in the set in parallel based on the selected test pins comprises:
the selected test pins are controlled by a multiplexer selector to test the modules in the set in parallel.
6. A chip testing apparatus, comprising:
the first dividing module is used for dividing the chip to be detected into a plurality of subsystems;
The system comprises a first dividing module, a second dividing module, a logic running-through testing module and a logic running-through testing module, wherein the first dividing module is used for dividing each subsystem into a plurality of modules and dividing all the modules into a plurality of sets, wherein the independence and the interconnectivity of all functional modules in a chip are considered by dividing one chip to be tested;
the test module is used for aiming at any set, selecting test pins for each module in the set nearby based on the physical position of each module in the set in the chip to be tested, and testing each module in the set in parallel based on the selected test pins;
the total number of test pins required by all modules in any one set is not more than the total number of pins of the chip to be tested;
the method further comprises the steps of, for any one set, selecting test pins for each module in the set nearby based on the physical position of each module in the set in the chip to be tested, and after parallel testing each module in the set based on the selected test pins:
Determining at least two modules requiring testing module connection boundaries in the set, and configuring interface registers of the at least two modules by adopting an external test mode of WRAPPER CHAIN so as to communicate the at least two modules;
The module connection boundary is tested based on any one of the at least two modules that are connected.
7. An electronic device, comprising:
a memory for storing a computer program;
A processor for executing the computer program to implement the chip test method according to any one of claims 1 to 5.
8. A readable storage medium for storing a computer program, wherein the computer program when executed by a processor implements the chip test method according to any one of claims 1 to 5.
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| CN117368698B (en) * | 2023-11-01 | 2024-05-24 | 上海合芯数字科技有限公司 | Chip circuit and testing method thereof |
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