CN118937978B

CN118937978B - A 3DIC Test Architecture

Info

Publication number: CN118937978B
Application number: CN202411428640.2A
Authority: CN
Inventors: 刘劲松
Original assignee: Shanghai Yiruixin Electronic Technology Co ltd
Current assignee: Shanghai Yiruixin Electronic Technology Co ltd
Priority date: 2024-10-14
Filing date: 2024-10-14
Publication date: 2025-02-25
Anticipated expiration: 2044-10-14
Also published as: CN118937978A

Abstract

The present invention provides a 3DIC test architecture, including a carrier chip and an upper chip, wherein the carrier chip and the upper chip are embedded with an ijtag network, and the carrier chip and the upper chip are provided with an IJTAG interface, and the ijtag network controlled by the TAP controller on the carrier chip is connected to the ijtag network of the upper chip via the IJTAG interface of the carrier chip, and the signal connected to the IJTAG interface of the upper chip and the control signal of the TAP controller of the upper chip are selected through multiple multiplexers a, and a single test signal is output to the ijtag network of the upper chip. The beneficial effect of this technical solution is that the present invention connects the ijtag network on the carrier chip to the upper chip of the 3D package chip through the multiplexer, and solves the problem of multiplexing the IEEE 1687 network during the 3DIC test process through the TAP controller on the carrier chip.

Description

3DIC test architecture

Technical Field

The invention belongs to the technical field of chip testing, and particularly relates to a 3DIC testing architecture.

Background

IJTAG (Internal Join Test Action Group) refers to IEEE 1687 protocol, with the development of integrated circuits, IP is increasingly involved in circuit design, a protocol is required to access different modules in a chip in a flexible manner, and to solve the problem of delivery of IP test schemes, meanwhile IEEE 1149.1 and IEEE 1500 protocols are poor in expansibility, access is not flexible enough, a single module has high hardware overhead, and lack of a proper description language, and the two protocols need to be expanded and developed, so that the IEEE 1687 protocol is generated.

The IEEE 1687 protocol defines element connection language (Instrument Connectivity Language, ICL) to describe element connection relation, process description language (Procedural Description Language, PDL) to describe operation of elements, and SIB module is provided, and the IEEE 1687 protocol realizes flexible access to different modules on the basis of being compatible with IEEE 1149.1 and IEEE 1500 protocols.

Modern integrated circuits tend to combine devices from many different sources onto the same chip for packaging. The 3D wafer level packaging technology stacks more than two chips in the vertical direction in the same package body on the premise of not changing the size of the package body, and the packaging technology originates from the stacked packaging of a flash memory and an SDRAM. Its advantages include high performance, high capacity and density, multiple functions and applications per unit volume, and low cost.

In the prior art, a TAP cascading mode based on an IEEE 1149 protocol is generally adopted for 2DIC test. In the 3DIC test, if the TAP cascade mode based on the IEEE 1149 protocol is adopted, the configuration time is too long, and the IEEE 1838 protocol for the 3DIC test can flexibly configure each chip. However, the current business tools differ in the manner in which the IEEE 1838 protocol is supported, so that no generalization is made within the IEEE 1838 protocol, and thus, in actual project execution, it is desirable to solve the 3DIC testing problem with the more mainstream IEEE 1687 protocol.

Disclosure of Invention

The invention provides a 3DIC test architecture, which designs a communication method among 3DIC multiple chips based on an IEEE 1687 protocol and solves the problem of multiplexing an IEEE 1687 network in the 3DIC test.

Other objects and advantages of the present invention will be further appreciated from the technical features disclosed in the present invention.

In order to achieve one or a part of or all of the above objects or other objects, a 3DIC test architecture according to an aspect of the present invention includes a carrier chip and an upper chip, wherein a IJTAG network is embedded in the carrier chip and the upper chip, an ijag interface is provided on the carrier chip and the upper chip, a IJTAG network controlled by a TAP controller on the carrier chip is connected to a IJTAG network of the upper chip through an ijag interface of the carrier chip, signals connected to the ijag interface of the upper chip and control signals of a TAP controller of the upper chip are selected through a plurality of multiplexers a, and a single test signal is output to a IJTAG network of the upper chip. The technical scheme has the beneficial effects that the ijtag network on the carrier chip is accessed into the upper chip of the 3D package body chip through the multiplexer a, and the whole chip is controlled to test the package body chip based on the IEEE 1687 protocol through the TAP controller on the carrier chip, so that the problem of multiplexing the IEEE 1687 network in the 3DIC test process is solved.

The carrier chip and the upper chip except the top chip are provided with an auxiliary SIB module, the auxiliary SIB module is connected into a scanning chain formed by SIB modules in the IJTAG network, the auxiliary SIB module is connected into a selection signal and a scanning input signal in the scanning chain, and the selection signal and the scanning input signal are output to an IJTAG interface.

The carrier chip and the IJTAG interface arranged on the upper chip comprise an interface for transmitting TCK signals input in a carrier chip test interface, an interface for transmitting other control signals except host control signals output by the carrier chip TAP controller to a root SIB module, an interface for transmitting selection signals and scanning input signals output by an auxiliary SIB module, and an interface for returning scanning output signals of the SIB module at the tail end of the upper chip.

The carrier chip and the upper chip except the top chip are also internally provided with a virtual bit SIB module, the virtual bit SIB module receives a selection signal and a scanning input signal which are output by the auxiliary SIB module, and a scanning output signal of the virtual bit SIB module is transmitted back to an interface end of the auxiliary SIB module.

When the upper chip is arranged in a plurality of layers, the carrier chip and the upper chip and the plurality of layers of upper chips are communicated through the IJTAG interface.

And the scanning output signal of the SIB module at the tail end of the upper chip returned by the IJTAG interface and the scanning output signal of the SIB module at the virtual bit of the current chip are selected through a multiplexer b, and the scanning output signal output by the multiplexer b is transmitted to the interface end of the auxiliary SIB module.

The uppermost chip of the packaged chip is not provided with an auxiliary SIB module and a virtual bit SIB module.

The upper chip is also embedded with jtag networks, jtag networks in the upper chip are controlled by a TAP controller of the upper chip, and ijtag network ports and jtag network ports are respectively arranged on the upper chip.

The control signals of the multiplexer a and the multiplexer b come from packaging signals or TDR signals, when the package chip test is carried out after stacking, the packaging signals are pulled up, so that the upper chip is connected into IJTAG networks of the carrier chip through the IJTAG interface, and when the wafer test is carried out before stacking, the multiplexer a controls the upper chip to be connected into jtag networks or IJTAG networks of the upper chip through the TAP controller.

The scanning test result reading mode of the upper chip is that a group of ijtag scanning interfaces for connecting the upper chip are created in ICL files of the carrier chip, the scanning test result of the upper chip is returned to the carrier chip through an ICL network, and the ICL files in the carrier chip are extracted through a TAP controller on the carrier chip to read the scanning test result of the upper chip.

The ICL module is established in the ICL network, ICL files of the upper chip and the carrier chip are read in, ICL files of the simulation top module are generated, and ijtag networks of the simulation top module are configured and used for simulating connection of the upper chip of the packaged chip and the carrier chip.

Compared with the prior art, the method has the advantages that 1, the scheme of the invention mainly comprises the steps of accessing ijtag networks on the carrier chip into an upper chip of the 3D package body chip through the multiplexer a, and controlling the whole chip to test the package body chip based on the IEEE 1687 protocol through the TAP controller on the carrier chip, thereby solving the problem of multiplexing the IEEE 1687 networks in the 3DIC test process.

2. The multiplexer a inserted in the upper chip can be controlled based on the packaging signal or the TDR output signal, and when the chip packaging level test or the chip wafer level test is performed, the upper chip selects the IEEE 1687 protocol accessed into the carrier chip to perform the packaging chip test, or the chip wafer level test is performed based on the ijtag network or the jtag network embedded in the upper chip, so that the testing function is enriched.

The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of preferred embodiments, as illustrated in the accompanying drawings.

Drawings

In order to more clearly illustrate the technical solutions of specific embodiments of the present invention, the drawings that are needed in the description of the embodiments will be briefly described below, and it is obvious that the drawings described below are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort to a person of ordinary skill in the art.

Fig. 1 is a circuit diagram of a 3DIC testing architecture according to the present invention.

Fig. 2 is a circuit diagram of a test structure for sealing two wafers in accordance with the first embodiment.

FIG. 3 is a circuit diagram of a test structure for sealing a three-layer wafer in accordance with the first embodiment.

Detailed Description

In order that the application may be readily understood, a more complete description of the application will be rendered by reference to the appended drawings. Embodiments of the application are illustrated in the accompanying drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

The foregoing and other features, aspects, and advantages of the present invention will become more apparent from the following detailed description of a preferred embodiment, which proceeds with reference to the accompanying drawings. The directional terms mentioned in the following embodiments, such as up, down, left, right, front or rear, etc., are only referring to the directions of the attached drawings. Thus, the directional terminology is used for purposes of illustration and is not intended to be limiting of the invention.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

Example 1

Referring to the 3DIC test architecture circuit diagram of the present invention of fig. 1, comprising ijtag networks formed in a carrier chip and an upper chip, ijtag networks are formed by connecting a plurality of SIB modules (only one SIB module is given as an example for the carrier chip in fig. 1, a plurality of SIB modules may be formed in an actual ijtag network, and corresponding devices may be mounted under the SIB modules) to form an access network.

The TAP controller of the carrier chip and the TAP controller of the upper chip control ijtag the network, wherein the TAP controller of the carrier chip controls one or more upper chips to test based on the ijtag network, and the TAP controller of the carrier chip sends out corresponding control signals (test signals are input to the TAP controller of the carrier chip through the pad of the carrier chip) to the ijtag network of the upper chip. Meanwhile, the TAP controller of the carrier chip controls the SIB module to send out a corresponding test signal to the SIB module of the upper chip, and the SIB module of the upper chip transmits the scanning result back to the SIB module in the carrier chip to form a loop (see the signal loop formed by the SIB module of the carrier chip and the SIB module of the upper chip in fig. 1).

The test signals comprise scanning input signals and selection signals, wherein the scanning input signals are used for loading test data into a scanning chain, and the internal states of the circuit are controlled and observed in the test process. The selection signal is used to control the operation mode of the circuit to switch between a normal operation mode and a test mode.

The signal transmission between the carrier chip and the upper chip is performed by Micro Bump (Micro Bump for establishing electrical connection between chips of the package wafer or between the chips and the substrate) between the carrier chip and the upper chip. And a plurality of Micro-modules of the carrier chip and the upper chip form a signal transmission interface, and a control signal of the TAP controller and a test signal of the SIB module are transmitted to the upper chip through the signal transmission interface between the carrier chip and the upper chip.

The test of the package chip will be described below taking two-layer package chips and three-layer package chips as examples.

Referring to fig. 2, the two-layer package chip includes a carrier chip and a layer 2 chip, wherein the carrier chip refers to a chip located at the bottommost layer of the stacked layer structure, and the carrier chip may be selected according to application requirements and technical requirements, and may be a logic chip, an application specific integrated circuit, an interconnection chip, or the like. The carrier chip and the upper chip are embedded with ijtag networks based on IEEE 1687 protocol, wherein ijtag networks based on IEEE 1687 protocol build an Access Network (Access Network) through a plurality of SIB (Segment Insertion Bit) modules, TDR (Test Data Register), a controller interface, an embedded module interface and the like, the SIB modules function as switches, when the SIB modules are opened, signals and data pass through a test device (Instrument) mounted on the SIB modules, and when the SIB modules are closed, the signals and the data only pass through the SIB modules and do not pass through the test device mounted on the SIB modules. TDR (Test Data Register) modules control and observe the modules, typically in ijtag networks, through embedded module interfaces. The control, configuration and operation signals of the TDR are generated by a TAP (TEST ACCESS Port) controller, and the TDR is divided into three types of write-only, read-only and writable and readable. SIB module, mounting equipment and TDR module in ijtag network can be designed according to the requirement.

After the test data is received by the TAP controller, a selection signal, a clock signal, TDI data and the like are sent to an access network of which the data conduction direction is controlled by the SIB module for testing. The ijtag access network under the IEEE 1687 protocol is a prior art, and the present application is not described in detail herein.

The ijtag network on the carrier chip is controlled by a TAP controller which is part of the IEEE 1149.1 protocol test network, and a jtag network may be embedded separately in the upper chip, where the testing of individual wafers is performed primarily based on the IEEE 1149.1 protocol.

To facilitate testing of the packaged chip, and to facilitate use of mainstream business tools, the ijtag network on the carrier chip is accessed into the ijtag network of the layer 2 chip, and the TAP controller of the carrier chip is used to control testing of the entire packaged chip. The main way of accessing the carrier chip to the layer 2 chip is to insert the multiplexer a (the ECO way includes determining the requirement, preparing the design file, creating the ECO working area, designing and inserting the multiplexer, verifying, updating the test vector and the document, evaluating and archiving, the multiplexer insertion is the conventional technical scheme by the ECO way, the application is not described in detail), meanwhile, a plurality of IJTAG interfaces are arranged on the carrier chip and the layer 2 chip, the IJTAG interfaces mainly include an interface IJTAG _tck for transmitting the clock signal TCK in the test signal input on the carrier chip to the layer 2 chip, and the rest control signals except the host control signal host_1_to_sel in the control signals sent by the TAP controller are accessed to the interface in the IJTAG network of the layer 2 chip.

Taking fig. 2 as an example, among the control signals issued by the carrier chip TAP controller of fig. 2, signals other than the host control signal include a control signal capture_dr_en for controlling the capture operation of the data register, a test_logic_reset signal for resetting the TAP controller to its initial state, a shift_dr_en signal for enabling and controlling the data shift process during the shift operation of the data register, and an update_dr_en signal for enabling and controlling the data update process during the update operation of the data register. The interfaces corresponding to the four signals are interface ijtag _ce, interface ijtag _reset, interface ijtag _se and interface ijtag _ue respectively.

The ijjtag interface includes interfaces IJTAG _sel and IJTAG _si that pass the select signal and the scan-in signal of the root SIB module on the carrier chip to the SIB module mounted on the root SIB module into the layer 2 chip IJTAG network.

Illustratively, the HIP interface-connected SIB module of the SIB module mounted on the root SIB module, that is, the auxiliary SIB module sibauxdie in FIG. 2, the root SIB module in FIG. 2 is turned on under the control of the selection signal, the scan in signal ijtag _to_si and the scan select signal ijtag _to_sel output by the root SIB module enter the auxiliary SIB module, and the auxiliary SIB module similarly outputs the scan in signal ijtag _to_si and the scan select signal ijtag _to_sel after being turned on.

The ijjtag interface also includes an interface IJTAG _so that transmits the scan out signals of the terminal SIB modules in the IJTAG network of the upper chip to the carrier chip. Taking the two-layer packaged chip of fig. 2 as an example, the end SIB module is the last SIB module of the scan chain.

In order to facilitate control of ijtag networks of the layer 2 chip, an auxiliary SIB module sib_aux_die and a virtual bit SIB module sib_aux_die_dummy are arranged in the carrier chip, wherein the auxiliary SIB module and the virtual bit SIB module are not mounted with test equipment (HIP interfaces of the auxiliary SIB module and the virtual bit SIB module are not mounted with equipment), but the auxiliary SIB module is mounted under a root SIB module, the virtual bit SIB module is mounted under the auxiliary SIB module, and the auxiliary SIB module, the virtual bit SIB module and the virtual bit SIB module form a multi-layer parallel network. The scan out data ijtag _so of the auxiliary SIB module and the virtual bit SIB module in the co-layer chip are input to the root SIB module and the receiving end ijtag _from_so in the auxiliary SIB module, respectively, to form a loop. The auxiliary SIB module is used for controlling the IJTAG network of the upper chip by the auxiliary TAP controller, transmitting the scan input signal IJTAG _to_si and the scan selection signal IJTAG _to_sel output to the next SIB module to the IJTAG network of the layer 2 chip through the ijjtag interface (more specifically, taking the output scan input signal IJTAG _to_si and the scan selection signal IJTAG _to_sel as the scan input signal IJTAG _si and the selection signal input IJTAG _sel of the root SIB module in the network of the upper chip IJTAG) and transmitting the scan input signal IJTAG _to the virtual bit SIB module, wherein the virtual bit SIB module is loaded with the TDR module.

The multiplexer a inserted into the layer 2 chip selects the control signal of the TAP controller of the layer 2 chip, the test input signal of the layer 2 chip and the signal input by the IJTAG interface (wherein, the TAP controller in the layer 2 chip can be connected with IJTAG network and jtag network to realize simultaneous control and can be connected with IJTAG network only), and under the control of the control signal, the unique test signal is selected according to the chip test type to be accessed into the upper chip test network. Wherein the layer 2 chip has a ijtag network based on the IEEE 1686 protocol and a jtag network based on the IEEE 1149.1 protocol controlled by the TAP controller. Two kinds of network ports (two kinds of device interfaces and module interfaces) exist in the hardware architecture of the upper chip correspondingly. Among the control signal line access pads of the plurality of multiplexers a, the control signal of the multiplexer a is derived from the package signal and the TDR signal.

The control signals of the multiplexer a and the multiplexer b come from the packaging signals during the packaging chip test, and come from the TDR output signals during the wafer level test. After the chip is packaged, a packaging signal is pulled up and is input into a bonding pad, a multiplexer a is controlled to input a clock signal, a TAP controller control signal and a scanning input signal and a selection signal which are output by an auxiliary SIB module on a carrier chip into a ijtag network in a layer 2 chip, so that when the layer 2 chip is tested based on an IEEE 1687 protocol, the TAP controller on the carrier chip can be directly used for controlling, the time waste for loading test signals is reduced when the TAP controller is cascaded, and the test efficiency is improved.

And in the wafer level test, the control signal of the multiplexer a comes from the TDR signal, and the multiplexer a selects the TAP controller of the layer 2 chip to be connected to the ijtag network or the jtag network in the upper layer chip for the wafer level test.

Through the control of the multiplexer a, different protocol types can be selected to test the chip according to different test types, so that the test selectivity is expanded, and the test functions are enriched.

In order to make the SIB module in IJTAG network form complete loop, the scan output data of the terminal SIB module in IJTAG network of layer 2 chip is transmitted to the multiplexer b on the carrier chip through the ijjtag interface, the other input data of the multiplexer b is the scan output data of the SIB module with virtual bit, the control signal of the multiplexer b is the same as the control signal of the multiplexer a above, when the package chip test is performed, the package signal is pulled up, and the multiplexer b outputs the scan output data of the terminal SIB module input by the layer 2 chip to the receiving end of the auxiliary SIB module. When the wafer level test is performed, the control signal is derived from the TDR signal, and the multiplexer b outputs the scan-out data of the SIB module with the virtual bit to the receiving end of the SIB module with the auxiliary bit.

For testing of multi-layer packaged chips (at least greater than 2 layers), a 3-layer packaged chip test in fig. 3 is illustrated, the 3-layer packaged chip in fig. 3 including a carrier chip, a 2 nd layer chip, and a 3 rd layer chip.

The three-layer package chip test in fig. 3 is different from the 2-layer package chip test in fig. 2 in that communication is performed between the carrier chip and the upper chip and between the upper chip through the ijag interface. A plurality of IJTAG interfaces are arranged between the carrier chip and the layer 2 chip, and a plurality of IJTAG interfaces are arranged between the layer 2 chip and the layer 3 chip. The layer 2 chip in fig. 3 is provided with an auxiliary SIB module and a virtual bit SIB module. Meanwhile, the auxiliary SIB module of the layer 2 chip is arranged at the extreme end of the scanning chain and is used for returning scanning output signals to the carrier chip through the IJTAG interface. Therefore, in the test design of the multi-layer chip, the position of the auxiliary SIB module is not particularly limited, and may be in the scan chain formed by the SIB modules, but in general, in order to facilitate the design of the circuit and reduce the interference of the auxiliary SIB module to the circuit, the auxiliary SIB is often disposed at the end of the scan chain or connected to the root SIB module. The connection of the auxiliary SIB module and the virtual bit SIB module in the layer 2 chip is the same as the two-layer chip package test in fig. 2.

Other schemes are the same as the two-layer chip package test of fig. 2 and are not described here in detail.

Therefore, when there are multiple upper-layer chips to package, the multiple upper-layer chips (except the topmost upper-layer chip) are provided with the auxiliary SIB module and the virtual bit SIB module. The loop formed by the auxiliary SIB module and the virtual SIB module arranged on the upper chip is the same as the loop formed by the auxiliary SIB module and the virtual SIB module on the carrier chip. Meanwhile, an IJTAG interface and a multiplexer a are arranged between the upper chips, and the IJTAG interface arranged between the upper chips is used for receiving control signals from a TAP controller on the carrier chip, clock signals on the carrier chip, scan output data of an auxiliary SIB module from a lower chip (the lower chip in the two upper chips for signal transmission) and selection signals. The manner of accessing signals among the upper chips to the multiplexer a and the manner of returning the scan output data of the SIB module at the tail end of the upper chip to the auxiliary SIB module of the lower chip are the same as the two-layer package chip test scheme, and are not repeated here.

In addition to improving the existing hardware architecture, the 3DIC testing architecture in the first embodiment also requires corresponding modification to the ICL (Instrument Connection Language, ijjtag network connection language) network, including inserting the multiplexer a and the multiplexer b into the ICL network, and modifying the corresponding ICL file, so that the business tool can extract and identify the ILC networks of different levels normally. When multiplexer a selects the ICL network to access the upper chip, the virtual bit SIB module will no longer be accessed.

Meanwhile, in order to facilitate reading of test contents of the upper chip, a group of ijtag scan interfaces for connecting the upper chip is additionally created in the TCL file of the carrier chip, the ICL file of the upper chip can be transmitted to the carrier chip through the ijtag interface, and the TAP controller controls corresponding commercial software to extract the ICL file on the carrier chip by using a standard flow so as to obtain a test result of the upper chip.

Meanwhile, in order to simulate the connection between the upper chip and the carrier chip of the package wafer, a Pseudo Top layer (simulated Top layer module) is created in the ICL network, the ICL files of the upper chip and the carrier chip are read in the Pseudo Top layer, the ICL files of the package chip are extracted by adopting a standard flow of commercial software (commercial EDA tool), and a ijtag network is configured in the Pseudo Top layer so as to be capable of accessing and controlling various test points and registers in the upper chip and the carrier chip. ICL files of the pseudoTop layer are generated using a commercial EDA tool and applied. And setting a unified interface on the Pseudo Top layer, testing the chip according to the generated TCL file, and verifying the result, including verifying the feasibility of the ICL file. By this method, the test process of the entire packaging system can be managed and controlled at a higher level of abstraction.

The technical features of the above embodiments may be arbitrarily combined, and for brevity, all of the possible combinations of the technical features of the above embodiments are not described, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.

The above description of a 3DIC testing architecture provided by the present invention applies specific examples to illustrate the architecture and principles of operation of the present invention, and the above description of the embodiments is only for aiding in understanding the method and core concept of the present invention. It should be noted that it will be apparent to those skilled in the art that various improvements and modifications can be made to the present invention without departing from the principles of the invention, and such improvements and modifications fall within the scope of the appended claims.

Claims

1. A3 DIC test architecture includes a carrier chip and an upper chip;

The carrier chip is embedded with ijtag networks in the upper chip, and is characterized by comprising the following components:

The carrier chip and the upper chip are provided with IJTAG interfaces, a IJTAG network controlled by the TAP controller on the carrier chip is accessed into a IJTAG network of the upper chip through the IJTAG interfaces of the carrier chip, signals accessed on the IJTAG interfaces of the upper chip and control signals of the TAP controller of the upper chip are selected through a plurality of multiplexers a, and a single test signal is output to a IJTAG network of the upper chip;

The ijtag network is formed by a plurality of SIB modules to form an access network;

The TAP controller of the carrier chip sends out corresponding control signals to the ijtag network of the upper chip, the TAP controller of the carrier chip controls the SIB module to send out corresponding test signals to the SIB module of the upper chip, and the SIB module of the upper chip returns the scanning result to the SIB module in the carrier chip to form a loop.

2. The 3DIC testing architecture of claim 1, wherein the carrier chip and the upper chip except for a top chip are provided with an auxiliary SIB module, the auxiliary SIB module being connected to a scan chain formed by SIB modules in the IJTAG network, the auxiliary SIB module being connected to a selection signal and a scan-in signal in the scan chain and outputting the selection signal and the scan-in signal to an ijag interface.

3. The 3DIC testing architecture of claim 2, wherein the carrier chip and the ijag interface provided on the upper chip comprise an interface for transferring TCK signals inputted in the carrier chip testing interface, an interface for transferring control signals outputted from the carrier chip TAP controller to the root SIB module except for host control signals, an interface for transferring selection signals outputted from the auxiliary SIB module and scan-in signals, and an interface for returning scan-out signals from the SIB module at the end of the upper chip.

4. The 3DIC testing architecture of claim 3, wherein the carrier chip and the upper chip except for a top chip are further provided with a virtual bit SIB module, the virtual bit SIB module receiving a selection signal and a scan in signal outputted by the auxiliary SIB module, and a scan out signal of the virtual bit SIB module being returned to an interface end of the auxiliary SIB module.

5. The 3DIC testing architecture according to any one of claims 1-4, wherein when the upper chip is layer 1, communication is performed between the upper chip and the carrier chip via the ijag interface, and when the upper chip is provided with a plurality of layers, communication is performed between the carrier chip and the upper chip and between the plurality of layers of upper chips via the ijag interface.

6. The 3DIC testing architecture of claim 4, wherein the upper chip end SIB module scan out signal returned by the ijjtag interface is selected with the scan out signal of the virtual bit SIB module of the current chip through a multiplexer b, and the scan out signal outputted by the multiplexer b is transmitted to the interface end of the auxiliary SIB module.

7. The 3DIC testing architecture of claim 4, wherein the uppermost chip of the packaged chip is not provided with an auxiliary SIB module and a dummy bit SIB module.

8. The 3DIC testing architecture of claim 1, wherein the upper chip is further embedded with jtag networks, jtag networks within the upper chip are controlled by a TAP controller of the upper chip, and the upper chip is provided with ijtag network ports and jtag network ports, respectively.

9. The 3DIC testing architecture of claim 8, wherein the control signals for multiplexer a and multiplexer b are from package signals or from TDR signals, wherein the package signals are pulled high during post-stack package chip testing to enable the upper die to access the IJTAG network of the carrier die via the ijjtag interface, and wherein the multiplexer a controls the upper die to access the jtag network or IJTAG network of the upper die via its own TAP controller during pre-stack wafer testing.

10. The 3DIC testing architecture of claim 1, wherein the scan test results of the upper chip are read by creating a set of ijtag scan interfaces for connection to the upper chip in ICL files of the carrier chip, returning the scan test results of the upper chip to the carrier chip via the ICL network, and extracting the ICL files in the carrier chip via a TAP controller on the carrier chip to read the scan test results of the upper chip.

11. The 3DIC testing architecture of claim 1, further comprising creating a simulated top module in the ICL network, reading ICL files of the top chip and the carrier chip, generating ICL files of the simulated top module, and configuring ijtag network of the simulated top module for simulating connection of the top chip of the packaged chip and the carrier chip.