CN114002577A - A chip testing method, apparatus, device and readable storage medium - Google Patents
A chip testing method, apparatus, device and readable storage medium Download PDFInfo
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Abstract
本申请公开了一种芯片测试方法、装置、设备及可读存储介质。本申请将待测芯片划分为多个子系统；将每个子系统划分为多个模块，并将所有模块划分至多个集合；针对任一个集合，基于该集合中的各模块在待测芯片中的物理位置，为该集合中的各模块就近选择测试管脚，并基于所选择的测试管脚并行测试该集合中的各模块，从而针对更小粒度的模块进行测试，扫描路径更短，降低了物理布线难度，还能实现芯片管脚的分时复用，降低了测试开销。相应地，本申请提供的一种芯片测试装置、设备及可读存储介质，也同样具有上述技术效果。
The present application discloses a chip testing method, apparatus, device and readable storage medium. The application divides the chip under test into multiple subsystems; divides each subsystem into multiple modules, and divides all modules into multiple sets; for any set, based on the physical properties of the modules in the set in the chip under test location, select test pins nearby for each module in the set, and test each module in the set in parallel based on the selected test pins, so as to test modules with smaller granularity, the scan path is shorter, and the physical The wiring is difficult, and the time-sharing multiplexing of the chip pins can also be realized, which reduces the test overhead. Correspondingly, the chip testing apparatus, device and readable storage medium provided by the present application also have the above technical effects.
Description
Technical Field
The present disclosure relates to the field of computer chip testing technologies, and in particular, to a chip testing method, apparatus, device, and readable storage medium.
Background
At present, the number of transistors integrated on a single chip is from millions to tens of millions, and even billions, the chip functions are more and more powerful, and the number of modules to be tested is increased.
Thousands of scan chains in a chip can be currently compressed into several or tens of scan chains based on EDT compression scan chain technology to alleviate the shortage of chip test pins. However, in one scan chain, the input test pin and the output test pin span multiple modules, so that the scan path is long, which not only brings great challenge to test timing sequence convergence and reduces test efficiency, but also causes difficulty in physical wiring required by the test.
Therefore, how to shorten the scanning path and reduce the physical wiring difficulty is a problem to be solved by those skilled in the art.
Disclosure of Invention
In view of the above, an object of the present invention is to provide a chip testing method, device, apparatus and readable storage medium, so as to shorten a scan path and reduce physical wiring difficulty. The specific scheme is as follows:
in a first aspect, the present application provides a chip testing method, including:
dividing a chip to be tested into a plurality of subsystems;
dividing each subsystem into a plurality of modules, and dividing all the modules into a plurality of sets;
for any set, based on the physical positions of the modules in the set in the chip to be tested, selecting test pins nearby for the modules in the set, and testing the modules in the set in parallel based on the selected test pins;
and the total number of the test pins required by all the modules in any set is not more than the total number of the pins of the chip to be tested.
Preferably, the chip to be tested and each subsystem are divided according to logic independence.
Preferably, the parallel testing of the modules in the set based on the selected test pins includes:
and if the modules with the same functions exist in the set, inputting the same test stimulus to the modules with the same functions in parallel.
Preferably, the parallel input of the same test stimulus to the modules of the same function includes:
and inputting the same test stimulus to the modules with the same function in parallel by adopting a broadcasting structure.
Preferably, before the parallel testing of the modules in the set based on the selected test pins, the method further includes:
the interface registers of each module are configured based on the Wrapper chain's internal test mode to isolate different modules.
Preferably, the parallel testing of the modules in the set based on the selected test pins includes:
the selected test pins are controlled by a multiplexer selector to test the modules in the set in parallel.
Preferably, for any one set, after selecting a test pin for each module in the set in the vicinity based on the physical position of each module in the set in the chip to be tested, and testing each module in the set in parallel based on the selected test pin, the method further includes:
determining at least two modules needing to test the module connection boundary in the set, and configuring interface registers of the at least two modules by adopting an external test mode of a Wrapper chain so as to communicate the at least two modules;
testing the module connection boundary based on any one of the connected at least two modules.
In a second aspect, the present application provides a chip testing apparatus, comprising:
the first dividing module is used for dividing the chip to be tested into a plurality of subsystems;
the second dividing module is used for dividing each subsystem into a plurality of modules and dividing all the modules into a plurality of sets;
the test module is used for selecting test pins for the modules in the set nearby based on the physical positions of the modules in the set in the chip to be tested aiming at any set, and testing the modules in the set in parallel based on the selected test pins;
and the total number of the test pins required by all the modules in any set is not more than the total number of the pins of the chip to be tested.
In a third aspect, the present application provides an electronic device, comprising:
a memory for storing a computer program;
a processor for executing the computer program to implement the chip testing method disclosed in the foregoing.
In a fourth aspect, the present application provides a readable storage medium for storing a computer program, wherein the computer program, when executed by a processor, implements the chip testing method disclosed in the foregoing.
According to the scheme, the chip testing method comprises the following steps: dividing a chip to be tested into a plurality of subsystems; dividing each subsystem into a plurality of modules, and dividing all the modules into a plurality of sets; for any set, based on the physical positions of the modules in the set in the chip to be tested, selecting test pins nearby for the modules in the set, and testing the modules in the set in parallel based on the selected test pins; and the total number of the test pins required by all the modules in any set is not more than the total number of the pins of the chip to be tested.
Therefore, the chip to be tested is divided into a plurality of subsystems; dividing each subsystem into a plurality of modules, and dividing all the modules into a plurality of sets; and aiming at any set, selecting test pins nearby for each module in the set based on the physical position of each module in the set in the chip to be tested, and testing each module in the set in parallel based on the selected test pins, thereby testing the modules with smaller granularity. Because the test pins are selected for each module nearby, the scanning path is shorter when each module is tested, and the physical wiring difficulty is reduced. Meanwhile, the total number of the test pins required by all the modules in one set is not more than that of the chips to be tested, and all the modules are tested in parallel, so that the test efficiency can be improved, and all the pins of the chips to be tested can be utilized as far as possible. Each set is tested according to the method, time-sharing multiplexing of chip pins can be realized, and test overhead is reduced.
Accordingly, the chip testing device, the chip testing equipment and the readable storage medium provided by the application also have the technical effects.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a flow chart of a chip testing method disclosed in the present application;
FIG. 2 is a schematic view of a scan path disclosed herein;
FIG. 3 is a schematic diagram of a scan chain corresponding to the scan path shown in FIG. 2;
FIG. 4 is a schematic view of a scan path across different modules according to the present disclosure;
FIG. 5 is a schematic diagram of a subsystem-based multiplexing chip pin according to the present disclosure;
FIG. 6 is a schematic diagram of another subsystem-based multiplexing chip pin disclosed in the present application;
FIG. 7 is a schematic diagram of a scan chain included in a single module disclosed herein;
FIG. 8 is a schematic diagram of a chip testing apparatus according to the present disclosure;
fig. 9 is a schematic diagram of an electronic device disclosed in the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
For the purpose of describing the present application, the following description will be made in view of the background art to which the present application relates.
With the rapid increase of the demand of industries such as artificial intelligence and data storage on large-scale chips, the SoC scale shows exponential growth, the number of transistors integrated on a single chip ranges from millions to tens of millions to billions, but the requirement on the size of the chip is smaller and smaller, and a severe challenge is brought to the test after the chip is manufactured; the semiconductor process is steadily promoted, possible defects in the manufacturing process are more and more diversified and complicated, and more targeted test vectors are developed according to physical manufacturing defects and corresponding fault models to ensure the quality of chips.
The chip Test is performed by connecting an Automatic Test Equipment (ATE) with a pin of the chip, injecting a Test stimulus to the chip, reading a response result after the chip responds, and comparing the response result with an expected result to screen the quality of the chip. The increase of the number of the chip pins is far smaller than the increase scale of the internal logic of the chip, and on the other hand, the number of the chip pins is influenced by physical implementation, and on the premise of meeting the functional requirements, the smaller the number of the chip pins is, the better the chip pins are, so that extra pins are not designed and specially used for testing the chip, and therefore the pins used in the chip testing are mostly digital pins defined by multiplexing functions.
The scan chain compression technology provided by the EDT (Embedded Deterministic Test) can compress thousands of scan chains into several to dozens of scan chains, and effectively relieves the problem of insufficient Test pins of the chip. However, as the chip scale increases further, the functional pins of the chip cannot meet the current test requirements.
In addition, in one scan chain, the input test pin and the output test pin span a plurality of modules, so that the scan path is long, great challenge is brought to test timing sequence convergence, test efficiency is reduced, and physical wiring required by test is difficult. Therefore, the chip testing scheme is provided, the scanning path can be shortened, and the physical wiring difficulty is reduced.
Referring to fig. 1, an embodiment of the present application discloses a chip testing method, including:
and S101, dividing the chip to be tested into a plurality of subsystems.
S102, dividing each subsystem into a plurality of modules, and dividing all the modules into a plurality of sets.
It should be noted that, the independence and the interconnectivity of each functional module in the chip need to be considered when dividing one chip to be tested. If the function of a certain module is independent, the module can be tested independently. If the functions of two modules are related to each other, it is necessary to test whether the related part of logic can run through, in addition to separately testing the two modules.
Accordingly, such rules need to be followed between different subsystems. Thus, in one embodiment, the chip under test and each subsystem are partitioned according to logical independence.
Each subsystem and each module are divided based on the logic function of the chip and correspond to corresponding physical devices on the chip. Therefore, each module on the chip to be tested tests the data processing logic between the corresponding physical devices for realizing the module.
S103, for any set, selecting test pins nearby for each module in the set based on the physical position of each module in the set in the chip to be tested, and testing each module in the set in parallel based on the selected test pins.
Since each module on the chip to be tested is essentially testing the data processing logic between the corresponding physical devices implementing the module, it is necessary to connect the corresponding pins of the chip to test the data processing logic between these physical devices. In order to shorten the scanning path, the embodiment selects the test pins for each module nearby, so that the physical wiring difficulty required by the test can be reduced. As shown in fig. 2, the test pins (including the input pin and the output pin) of module a are all near module a, and the test pins of module B are all near module B, so that the physical wiring difficulty is low.
In this embodiment, after a chip to be tested is divided into modules, the number of pins required for testing each module can be determined based on the test requirements of each module, and because the number of pins on a chip to be tested is limited, the chip to be tested needs to be tested in batches. For this reason, in the present embodiment, all modules are divided into several sets, and a test flow is performed in parallel for each module in one set.
And the total number of the test pins required by all the modules in any set is not more than the total number of the pins of the chip to be tested.
In order to make all pins of the chip to be tested used as much as possible in each testing process, all modules can be divided into sets according to the total number of the pins of the chip to be tested. Namely: the total number of test pins required by all the modules in any one set is equal to the total number of pins of the chip to be tested. Of course, the total number of test pins required by all modules in any set may be smaller than the total number of pins of the chip to be tested, and only idle chip pins exist during testing of the corresponding set, which is not beneficial to improving the testing efficiency.
For example: a certain chip to be tested supplies 10 pins, and the chip to be tested is divided to obtain 5 modules: A. b, C, D, E are provided. Module a needs 2 test pins, module B needs 4 test pins, module C needs 6 test pins, module D needs 8 test pins, and module E needs 10 test pins. Then a and D may be divided into a set X, B and C into a set Y, and E is independent of a set Z. Thus, when the sets X, Y, Z are respectively tested, all pins of the chip are used, and the maximum utilization of the chip pins is realized; meanwhile, the time-sharing multiplexing of the chip pins is realized by the test flows respectively corresponding to the sets X, Y, Z.
Generally, a chip may not provide pins dedicated for testing, and then each functional pin of the chip may be defined as a test pin when testing the chip.
In one embodiment, testing the modules in the set in parallel based on the selected test pins includes: if the modules with the same function exist in the set, the same test stimulus is input to the modules with the same function in parallel. Wherein, the module of the same test excitation to the same function of parallel input includes: and a broadcast structure is adopted to input the same test stimulus to the modules with the same function in parallel. The modules with the same functions are as follows: the modules are identical. The test stimulus is: for testing the input data designed by the corresponding module. The input data is input through the input pins, and the response of the module to the input data is obtained from the corresponding output pins, so that whether the response is in accordance with the expectation or not can be judged.
Therefore, the chip to be tested is divided into a plurality of subsystems in the embodiment; dividing each subsystem into a plurality of modules, and dividing all the modules into a plurality of sets; and aiming at any set, selecting test pins nearby for each module in the set based on the physical position of each module in the set in the chip to be tested, and testing each module in the set in parallel based on the selected test pins, thereby testing the modules with smaller granularity. Because the test pins are selected for each module nearby, the scanning path is shorter when each module is tested, and the physical wiring difficulty is reduced. Meanwhile, the total number of the test pins required by all the modules in one set is not more than that of the chips to be tested, and all the modules are tested in parallel, so that the test efficiency can be improved, and all the pins of the chips to be tested can be utilized as far as possible. Each set is tested according to the method, time-sharing multiplexing of chip pins can be realized, and test overhead is reduced.
Based on the foregoing embodiments, it should be noted that, in a specific implementation, before testing the modules in the set in parallel based on the selected test pins, the method further includes: the interface registers of each module are configured based on the Wrapper chain's internal test mode to isolate different modules.
Based on the foregoing embodiments, it should be noted that, in a specific implementation manner, the parallel testing of the modules in the set based on the selected test pins includes: the selected test pins are controlled by a multiplexer selector to test the modules in the set in parallel. The multiplexer is used to control the corresponding test pins (including the input pin and the output pin) of each module, so as to determine which module uses which pins to perform the test, as shown in fig. 3.
The scan path corresponding to module a in fig. 2 is expanded to obtain fig. 3. As can be seen from fig. 3, the decompressor and the compressor need to be set up accordingly when testing each module. Multiple modules may multiplex the same set of decompressor and compressor, or one module may use a set of decompressor and compressor. The usage of the decompressor and the compressor can refer to the prior related art, and will not be described herein.
Meanwhile, a module can have a plurality of scan chains, and each scan chain runs through N registers. The first register of a scan chain is called the head-of-chain register, and the last register is called the tail-of-chain register. The scan path is used to indicate the run of the scan chain.
Based on the foregoing embodiments, it should be noted that, in a specific implementation manner, for any set, after selecting a test pin for each module in the set in the vicinity based on a physical position of each module in the set in a chip to be tested, and testing each module in the set in parallel based on the selected test pin, the method further includes: determining at least two modules needing to test the module connection boundary in the set, and configuring interface registers of the at least two modules by adopting an external test mode of a Wrapper chain so as to communicate the at least two modules; the module connection boundary is tested based on any one of the connected at least two modules test pins.
Referring to fig. 4 in particular, it can be seen from fig. 4 that the connection boundary between module C and module D and the connection boundary between module D and module E all need to be tested. The prior art typically has the scan path across module C, D, E with the input pin selected near module C and the output pin selected near module E, which are not easily connected to the test lines because of the remote physical location of modules C and E on the chip.
Therefore, the module C is communicated with the module D by adopting an external test mode of the Wrapper chain, pins near the module C are used as input pins and output pins, and the connection boundary between the module C and the module D is tested firstly; and then, communicating the module D with the module E by adopting an external test mode of the Wrapper chain, using pins near the module E as input pins and output pins, and testing the connection boundary between the module D and the module E, thereby completing the boundary test between the modules. Therefore, the scanning path can be shortened, and the wiring difficulty is reduced. Accordingly, testing between different subsystems may be performed as well.
It should be noted that, because the compression ratio of the current EDT has already reached one hundred or even two hundred, an excessively high compression ratio may cause a reduction in the efficiency of generating vectors by ATPG (automatic Test Pattern Generation), and the number of generated Test vectors may also increase sharply, which adversely affects the vector Generation time and chip Test cost.
Therefore, the present embodiment time-division multiplexes the functional pins by using the time-division multiplexing technique. Only part of the chip subsystem or the implementation logic of the individual modules is tested during a certain period of time. And in another time period, testing the logic of other parts of the subsystem of the chip. Therefore, the number of available test pins is doubled, and the problem of insufficient test pins at present is effectively solved.
As shown in fig. 5, the system on chip is divided into 2 subsystems, the selection control register is controlled by the multiplexer, the input pin and the output pin are multiplexed to the subsystem 1 in the first testing period, and the scan test of the subsystem 1 is completed first; and in a second testing time period, multiplexing the input pin and the output pin to the subsystem 2, and then completing the scanning test of the subsystem 2. Of course, the total number of pins used in any test procedure should not exceed the total number of pins of the chip.
If the whole chip is divided into three subsystems, namely subsystem 1, subsystem 2 and subsystem 3, two subsystems can be selected to be tested in parallel in the first testing period, and the rest subsystems are tested after the two subsystems are tested in parallel. Of course, the total number of pins used in any test procedure should not exceed the total number of pins of the chip.
Because there are many modules in a subsystem, testing a subsystem may need to span multiple modules, resulting in a long scan chain and a flexible selection of pins for testing.
In contrast, in the present embodiment, after the whole chip adopts the partitioning subsystem, the sub-modules are partitioned to perform the grouping test, so that the targets of high coverage and few test pins are achieved under the condition that the test requirements are met. In this embodiment, the standard logic unit of the subsystem is further divided into different modules according to the requirements of functional and physical implementation, and the modules are used as test units to perform time-sharing tests on the different modules of the subsystem.
Specifically, the scan chain of the module is taken as a compression object, a compressor and a decompressor are added to each module, and a scan channel formed between the compressor and the decompressor is connected to a pin near the module nearby. As shown in fig. 2, the scan path is only within a single module and does not span different sub-modules. If testing of module boundaries is required, this is done with reference to FIG. 4 and the corresponding description above.
If a chip has pin 1, pin 2, pin 3, and pin 4, and the chip is divided into subsystem 1 (including module AB), subsystem 2 (including module CDE), and subsystem 3 (including module FG) as shown in fig. 6. Then these pins are used for scan path 1 and scan path 2 for subsystem 1, and scan path 7 and scan path 8 for subsystem 3, for the first test. After the test is finished, the scanning path 3, the scanning path 4, the scanning path 5 and the scanning path 6 of the subsystem 2 multiplex the pins. Thus, the maximum utilization and multiplexing of pins are realized.
It should be noted that, when the subsystems and the modules are divided, the independence and the interactivity of the test of each subsystem or sub-module need to be fully considered, and the test requirements of each subsystem and sub-module need to be balanced as much as possible, so that the effective reuse rate of the pins can be maximized when the functional pins are time-division multiplexed. As shown in fig. 6, in each test flow, all pins are used as much as possible; in different test flows, all pins can be multiplexed as much as possible, so that the pin multiplexing rate is maximized.
Therefore, the interface sequential logic unit (i.e. the interface register) of the sub-system or the sub-module is configured in the way of Wrapper chain.
Taking the module D shown in fig. 6 as an example, when designing a scan chain, sequential logic of an interface portion of the module D is separately connected into one or several input/output wrapper chains, so that the wrapper chains play a role in isolating each subsystem or sub-module.
As shown in fig. 7, sequential logic cells associated with module D interfaces are individually chained into input and output scan chains. In the internal test of the module, the wrapper chain is only used as a shift register or a capture register by controlling the internal test mode of the wrapper chain. When testing different module boundaries or different subsystem boundaries, only the wrapper chain is checked by controlling an external test mode of the wrapper chain, which is beneficial to vector generation and testing of a chip with a larger scale.
The embodiment can flexibly configure and multiplex the test pins, has smaller test scale and test unit division, can shorten the scanning path, and reduces the time sequence convergence difficulty. For a chip with large logic scale and area, the scanning path can be almost shortened by half, and the time sequence improvement effect is particularly obvious. By adopting the wrapper chain, the test coverage rate can be effectively improved, and the test time is reduced.
It can be seen that this embodiment not only can realize the compression of scan chain, and the most important effect is to complicated large-scale design, according to the physics position of putting of chip pin, adopts the timesharing multiplexing technique, plans best compression scanning channel length, alleviates the bottleneck of the mutual restriction between chip pin figure and the test time, reduces the compression ratio, alleviates inside wire winding jam of EDT and the difficult problem of chip top layer wiring. Meanwhile, the test grouping of the subsystems is further refined, multiplexing pins are reasonably configured, a scanning path is optimized, and the time sequence convergence difficulty is reduced.
Furthermore, for sub-modules or sub-systems with multiple multiplexing, when determining the test pin multiplexing scheme, a shared data channel may be considered, namely: these same sub-modules or subsystems are tested simultaneously with the same stimulus using a broadcast architecture to meet the use requirements for pin count.
In the following, a chip testing apparatus provided by an embodiment of the present application is introduced, and a chip testing apparatus described below and a chip testing method described above may be referred to each other.
Referring to fig. 8, an embodiment of the present application discloses a chip testing apparatus, including:
the first dividing module 801 is used for dividing a chip to be tested into a plurality of subsystems;
a second dividing module 802, configured to divide each subsystem into a plurality of modules and divide all the modules into a plurality of sets;
a test module 803, configured to select, for any one set, a test pin for each module in the set based on a physical position of each module in the set in the chip to be tested, and test each module in the set in parallel based on the selected test pin;
and the total number of the test pins required by all the modules in any set is not more than the total number of the pins of the chip to be tested.
In one embodiment, the test module is specifically configured to:
if the modules with the same function exist in the set, the same test stimulus is input to the modules with the same function in parallel.
In one embodiment, the test module is specifically configured to:
and a broadcast structure is adopted to input the same test stimulus to the modules with the same function in parallel.
In a specific embodiment, the method further comprises the following steps:
the first configuration module is used for configuring the interface register of each module based on the internal test mode of the Wrapper chain so as to isolate different modules.
In one embodiment, the test module is specifically configured to:
the selected test pins are controlled by a multiplexer selector to test the modules in the set in parallel.
In a specific embodiment, the method further comprises the following steps:
the second configuration module is used for determining at least two modules needing to test the module connection boundary in the set and configuring interface registers of the at least two modules by adopting an external test mode of the Wrapper chain so as to communicate the at least two modules; the module connection boundary is tested based on any one of the connected at least two modules test pins.
For more specific working processes of each module and unit in this embodiment, reference may be made to corresponding contents disclosed in the foregoing embodiments, and details are not described here again.
Therefore, the embodiment provides a chip testing device, which tests a module with smaller granularity, has a shorter scanning path, reduces the difficulty of physical wiring, can realize time-sharing multiplexing of chip pins, and reduces the testing overhead.
In the following, an electronic device provided by an embodiment of the present application is introduced, and an electronic device described below and a chip testing method and apparatus described above may be referred to each other.
Referring to fig. 9, an embodiment of the present application discloses an electronic device, including:
a memory 901 for storing a computer program;
a processor 902 for executing the computer program to implement the method disclosed in any of the embodiments above.
A readable storage medium provided in the embodiments of the present application is introduced below, and a readable storage medium described below and a chip testing method, apparatus, and device described above may be referred to each other.
A readable storage medium for storing a computer program, wherein the computer program, when executed by a processor, implements the chip testing method disclosed in the foregoing embodiments. For the specific steps of the method, reference may be made to the corresponding contents disclosed in the foregoing embodiments, which are not described herein again.
References in this application to "first," "second," "third," "fourth," etc., if any, are intended to distinguish between similar elements and not necessarily to describe a particular order or sequence. It will be appreciated that the data so used may be interchanged under appropriate circumstances such that the embodiments described herein may be practiced otherwise than as specifically illustrated or described herein. Furthermore, the terms "comprises" and "comprising," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, or apparatus.
It should be noted that the descriptions in this application referring to "first", "second", etc. are for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, technical solutions between various embodiments may be combined with each other, but must be realized by a person skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination should not be considered to exist, and is not within the protection scope of the present application.
The embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same or similar parts among the embodiments are referred to each other.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in Random Access Memory (RAM), memory, Read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of readable storage medium known in the art.
The principle and the implementation of the present application are explained herein by applying specific examples, and the above description of the embodiments is only used to help understand the method and the core idea of the present application; meanwhile, for a person skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.
Claims (10)
1. A method for testing a chip, comprising:
dividing a chip to be tested into a plurality of subsystems;
dividing each subsystem into a plurality of modules, and dividing all the modules into a plurality of sets;
for any set, based on the physical positions of the modules in the set in the chip to be tested, selecting test pins nearby for the modules in the set, and testing the modules in the set in parallel based on the selected test pins;
and the total number of the test pins required by all the modules in any set is not more than the total number of the pins of the chip to be tested.
2. The chip testing method according to claim 1, wherein the chip under test and each subsystem are divided in logical independence.
3. The method of claim 1, wherein testing the modules in the set in parallel based on the selected test pins comprises:
and if the modules with the same functions exist in the set, inputting the same test stimulus to the modules with the same functions in parallel.
4. The chip testing method according to claim 3, wherein the inputting the same test stimulus to the modules with the same function in parallel comprises:
and inputting the same test stimulus to the modules with the same function in parallel by adopting a broadcasting structure.
5. The method of chip testing of claim 1, wherein prior to testing the modules in the set in parallel based on the selected test pins, further comprising:
the interface registers of each module are configured based on the Wrapper chain's internal test mode to isolate different modules.
6. The method of claim 1, wherein testing the modules in the set in parallel based on the selected test pins comprises:
the selected test pins are controlled by a multiplexer selector to test the modules in the set in parallel.
7. The chip testing method according to any one of claims 1 to 6, wherein, for any one set, after selecting test pins for each module in the set nearby based on the physical location of each module in the set in the chip to be tested, and testing each module in the set in parallel based on the selected test pins, further comprising:
determining at least two modules needing to test the module connection boundary in the set, and configuring interface registers of the at least two modules by adopting an external test mode of a Wrapper chain so as to communicate the at least two modules;
testing the module connection boundary based on any one of the connected at least two modules.
8. A chip testing apparatus, comprising:
the first dividing module is used for dividing the chip to be tested into a plurality of subsystems;
the second dividing module is used for dividing each subsystem into a plurality of modules and dividing all the modules into a plurality of sets;
the test module is used for selecting test pins for the modules in the set nearby based on the physical positions of the modules in the set in the chip to be tested aiming at any set, and testing the modules in the set in parallel based on the selected test pins;
and the total number of the test pins required by all the modules in any set is not more than the total number of the pins of the chip to be tested.
9. An electronic device, comprising:
a memory for storing a computer program;
a processor for executing the computer program to implement the chip testing method of any one of claims 1 to 7.
10. A readable storage medium for storing a computer program, wherein the computer program, when executed by a processor, implements the chip testing method according to any one of claims 1 to 7.
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