CN113972258A - Semiconductor device and metal oxide semiconductor capacitor structure - Google Patents
Semiconductor device and metal oxide semiconductor capacitor structure Download PDFInfo
- Publication number
- CN113972258A CN113972258A CN202010722652.1A CN202010722652A CN113972258A CN 113972258 A CN113972258 A CN 113972258A CN 202010722652 A CN202010722652 A CN 202010722652A CN 113972258 A CN113972258 A CN 113972258A
- Authority
- CN
- China
- Prior art keywords
- semiconductor device
- layer
- metal layer
- conductive
- metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 80
- 239000003990 capacitor Substances 0.000 title claims abstract description 30
- 229910044991 metal oxide Inorganic materials 0.000 title claims abstract description 13
- 150000004706 metal oxides Chemical class 0.000 title claims abstract description 13
- 239000002184 metal Substances 0.000 claims abstract description 52
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 22
- 229920005591 polysilicon Polymers 0.000 claims abstract description 20
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000008707 rearrangement Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/642—Capacitive arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/645—Inductive arrangements
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
本申请提供了半导体装置以及金属氧化物半导体电容器结构。半导体装置设置于一电感器之下。半导体装置包含一金属氧化物半导体电容器结构以及一图案化屏蔽结构。金属氧化物半导体电容器结构包含一多晶硅层、一氧化定义层以及一第一金属层。第一金属层连接多晶硅层以及氧化定义层。图案化屏蔽结构设置于金属氧化物半导体电容器结构之上且包含一第二金属层。
The present application provides semiconductor devices and metal oxide semiconductor capacitor structures. The semiconductor device is disposed under an inductor. The semiconductor device includes a metal oxide semiconductor capacitor structure and a patterned shielding structure. The metal oxide semiconductor capacitor structure includes a polysilicon layer, an oxide definition layer and a first metal layer. The first metal layer is connected to the polysilicon layer and the oxide definition layer. The patterned shielding structure is disposed on the MOS capacitor structure and includes a second metal layer.
Description
Technical Field
Embodiments described in the present disclosure relate to semiconductor technology, and more particularly, to a metal oxide semiconductor capacitor structure and a semiconductor device including the same.
Background
With the development of semiconductor technology, mos capacitor structures have been applied to many circuit systems. However, some related art mos capacitor structures have many disadvantages, which result in poor quality factor (Q value) of the semiconductor device.
Disclosure of Invention
Some embodiments of the present disclosure relate to a semiconductor device. The semiconductor device is disposed below an inductor. The semiconductor device comprises a metal oxide semiconductor capacitor structure and a patterned shielding structure. The MOS capacitor structure comprises a polysilicon layer, an oxide definition layer and a first metal layer. The first metal layer is connected with the polycrystalline silicon layer and the oxidation definition layer. The patterned shielding structure is disposed on the MOS capacitor structure and includes a second metal layer.
Some embodiments of the present disclosure relate to a metal oxide semiconductor capacitor structure. The MOS capacitor structure is disposed under a patterned shielding structure. The MOS capacitor structure comprises a polysilicon layer, an oxide definition layer and a first metal layer. The first metal layer is connected with the polysilicon layer through a first connecting through hole and is connected with the oxidation definition layer through a second connecting through hole. The patterned shielding structure comprises a second metal layer, and the first metal layer is connected with the second metal layer through a third connecting through hole.
In summary, the semiconductor device of the present disclosure can utilize two metal layers to realize the mos capacitor structure and the patterned shielding structure, and can improve the quality factor value.
Drawings
In order to make the above and other objects, features, advantages and embodiments of the present disclosure more comprehensible, the following description is given:
fig. 1 is a schematic diagram of an inductor and a semiconductor device according to some embodiments of the present disclosure;
FIG. 2 is a schematic diagram of a semiconductor device according to some embodiments of the present disclosure;
FIG. 3 is a cross-sectional view of a section line of FIG. 2 shown in accordance with some embodiments of the present disclosure;
FIG. 4 is a cross-sectional view of a section line of FIG. 2 shown in accordance with some embodiments of the present disclosure;
FIG. 5 is a schematic diagram of a semiconductor device according to some embodiments of the present disclosure; and
fig. 6 is a schematic diagram illustrating a semiconductor device in accordance with some embodiments of the present disclosure.
Description of the symbols
110: inductor
120: semiconductor device with a plurality of semiconductor chips
120A: semiconductor device with a plurality of semiconductor chips
120B: semiconductor device with a plurality of semiconductor chips
120C: semiconductor device with a plurality of semiconductor chips
122: metal oxide semiconductor capacitor structure
1221: polycrystalline silicon layer
1222: oxide definition layer
1223. M1: a first metal layer
124: patterned shielding structure
AA': section line
BB': section line
M11: first conductive member
M12: second conductive member
M2: second metal layer
V1: first connecting through hole
V2: second connecting through hole
V3: third connecting through hole
X: direction of rotation
Y: direction of rotation
Z: direction of rotation
C1: first conductive segment
C2: second conductive segment
C3: third conductive segment
Detailed Description
The following embodiments are described in detail with reference to the accompanying drawings, but the embodiments are not provided to limit the scope of the disclosure, and the description of the structure operation is not intended to limit the execution sequence thereof, and any structure resulting from the rearrangement of elements to produce an apparatus with equivalent technical effect is included in the scope of the disclosure. In addition, the drawings are for illustrative purposes only and are not drawn to scale. For ease of understanding, the same or similar elements will be described with the same reference numerals in the following description.
It will be understood that the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections. These elements, components, regions, layers and/or regions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure.
Refer to fig. 1. Fig. 1 is a schematic diagram illustrating an inductor 110 and a semiconductor device 120, in accordance with some embodiments of the present disclosure. In the example of fig. 1, the semiconductor device 120 is disposed below the inductor 110.
Refer to fig. 2, 3 and 4. Fig. 2 is a schematic diagram illustrating a semiconductor device 120A in accordance with some embodiments of the present disclosure. Fig. 3 is a cross-sectional view of the cross-sectional line AA' of fig. 2, shown in accordance with some embodiments of the present disclosure. Fig. 4 is a cross-sectional view of the cross-sectional line BB' of fig. 2, shown in accordance with some embodiments of the present disclosure. In some embodiments, the semiconductor device 120A of fig. 2 is used to implement the semiconductor device 120 of fig. 1.
The semiconductor device 120A includes a metal-oxide-semiconductor capacitor (MOSCAP) structure 122 and a patterned shielding structure 124. The patterned shielding structure 124 is disposed above the mos capacitor structure 122.
In detail, the mos capacitor structure 122 includes a polysilicon layer 1221, an Oxide Definition (OD) layer 1222, a first metal layer 1223 (e.g., M1 layer, referred to as a first metal layer M1, hereinafter), a plurality of via (via) V1, and a plurality of via V2. The polysilicon layer 1221 is disposed over the oxide definition layer 1222. The first metal layer 1223 is disposed over the polysilicon layer 1221.
The patterned shielding structure 124 is disposed over the first metal layer 1223. The patterned shielding structure 124 may be implemented by a second metal layer (e.g., a layer M2, which will be referred to as a second metal layer M2).
In some related art, the magnetic field generated when the inductor located above operates may cause the semiconductor device located below to generate eddy current. The eddy current affects the quality factor (Q value) of the upper inductor.
In contrast to the related art, the semiconductor device 120A of the present disclosure includes the patterned shielding structure 124. In some embodiments, the patterned shielding structure 124 may be grounded. The patterned shielding structure 124 may reduce the mutual inductance in the inductor 110 to prevent the semiconductor device 120A from generating the above-mentioned eddy current, thereby effectively maintaining the quality factor of the inductor 110.
In addition, in some other related technologies, the mos capacitor structure needs to be implemented with at least three metal layers.
In contrast to the other related technologies, the mos capacitor structure 122 in the present disclosure is implemented by only two metal layers (the first metal layer M1 and the second metal layer M2). Accordingly, the metal oxide semiconductor capacitor structure 122 of the present disclosure has the advantages of low cost and simple structure.
Reference is again made to fig. 3. The first metal layer M1 includes a first conductive element M11 and at least a second conductive element M12. In the example of FIG. 3, the first metal layer M1 includes two second conductive features M12. The first conductive member M11 is configured to receive a first voltage. The second metal layer M2 is for receiving a second voltage. The second voltage is different from the first voltage. For example, the first voltage may be greater than the second voltage. In some embodiments, the first voltage is a positive voltage and the second voltage is a ground voltage.
Reference is again made to fig. 4. The first conductive member M11 is connected to the polysilicon layer 1221 through the first connection via V1. Reference is again made to fig. 3. The oxide defining layer 1222 is connected to the second conductive member M12 of the first metal layer M1 through the second connection via V2. The conductive member M12 of the first metal layer M1 is connected to the second metal layer M2 through the third connecting via V3. Since the oxide definition layer 1222 connects the second conductive element M12 of the first metal layer M1 and the second metal layer M2, the voltage levels of the oxide definition layer 1222, the second conductive element M12 of the first metal layer M1 and the second metal layer M2 are the same.
Reference is again made to fig. 2. The first projection range of the first conductive element M11 of the first metal layer M1 on the plane formed by the direction X and the direction Y is located within the second projection range of the second metal layer M2 on the plane formed by the direction X and the direction Y. In other words, the area of the projection range of the first conductive element M11 of the first metal layer M1 on the plane formed by the direction X and the direction Y is smaller than the area of the projection range of the second metal layer M2 on the plane formed by the direction X and the direction Y. The direction X and the direction Y are parallel to the direction Z.
The second conductive member M12 has an approximately H shape. In particular, second conductive member M12 includes a first conductive segment C1, a second conductive segment C2, and a third conductive segment C3. The first conductive segment C1 is connected to the oxide definition layer 1222 through a second connection via V2. The second conductive segment C2 is connected to the second metal layer M2 through the third connecting via V3. A third conductive segment C3 connects first conductive segment C1 and second conductive segment C2. Third conductive segment C3 is disposed perpendicular to first conductive segment C1 and second conductive segment C2. First conductive segment C1 is disposed parallel to second conductive segment C2. First conductive segment C1 and second conductive segment C2 extend in direction X. Third conductive segment C3 extends in direction Y.
In some related arts, the mos capacitor structure has a drawback of large capacitance and a large number of loops (loops), which are disadvantageous for the quality factor of the mos capacitor structure.
Compared to the related art, in the embodiment of fig. 2, since the second conductive element M12 is formed by a plurality of conductive segments, and the projection range of the second conductive element M12 on the plane formed by the direction X and the direction Y and the projection range of the polysilicon layer 1221 on the plane formed by the direction X and the direction Y are less overlapped (only the second conductive segment C2 and the third conductive segment C3 are overlapped with the polysilicon layer 1221), the capacitance (e.g., parasitic capacitance) can be reduced and the loop formation can be reduced, so as to improve the quality factor.
In the example of FIG. 2, the length of first conductive segment C1 is greater than the length of second conductive segment C2. In some other embodiments, the length of first conductive segment C1 may be equal to or less than the length of second conductive segment C2.
For example, in fig. 2, a first connection direction of the first through holes V1 on the left side of the drawing is a direction Y, and a second connection direction of the second through holes V2 on the top side of the drawing is a direction X. The direction Y is perpendicular to the direction X. That is, the first connecting direction of the first connecting vias V1 on the left side of the drawing is perpendicular to the second connecting direction of the second connecting vias V2 on the top side of the drawing. The second connecting vias V2 above the drawing and the second connecting vias V2 below the drawing are disposed on two sides of the polysilicon layer 1221, respectively.
For example, in fig. 2, the connection direction of the first through holes V1 on the left side of the drawing is the direction Y, and the connection direction of the third through holes V3 on the top side of the drawing is the direction X. The direction Y is perpendicular to the direction X. That is, the connection line of the first connecting vias V1 on the left side of the drawing is perpendicular to the connection line of the third connecting vias V3 on the top side of the drawing.
It is to be noted that the number of the first connecting vias V1, the number of the second connecting vias V2, and the number of the third connecting vias V3 in fig. 2 are only examples, and various suitable numbers are within the scope of the disclosure.
In some embodiments, the semiconductor devices 120A of fig. 2 may be repeatedly arranged and connected along a direction. For example, the semiconductor devices 120A of fig. 2 may be repeatedly arranged and connected along the direction X to form larger semiconductor devices and may be used in applications requiring larger dimensions.
Refer to fig. 5. Fig. 5 is a schematic diagram illustrating a semiconductor device 120B in accordance with some embodiments of the present disclosure. The main difference between the semiconductor device 120B of fig. 5 and the semiconductor device 120A of fig. 2 is that the second conductive members M12 of the first metal layer M1 of the semiconductor device 120B of fig. 5 are rectangular. In the example of fig. 5, the semiconductor device 120B has a rectangular parallelepiped shape, and the projection range of the second conductive member M12 on the plane formed by the direction X and the direction Y overlaps with the projection range of the polysilicon layer 1221 on the plane formed by the direction X and the direction Y more, so that the capacitance value thereof is large. In addition, the capacitance between the first conductive element M11 and the second conductive element M12 is also larger. Accordingly, the semiconductor device 120B of fig. 5 can be used in applications requiring larger capacitance values.
In some embodiments, the semiconductor devices 120B of fig. 5 may be repeatedly arranged and connected along a direction. For example, the semiconductor devices 120B of fig. 5 may be repeatedly arranged and connected along the direction X to form larger semiconductor devices and may be used in applications requiring larger dimensions.
Refer to fig. 6. Fig. 6 is a schematic diagram illustrating a semiconductor device 120C in accordance with some embodiments of the present disclosure. One of the main differences between the semiconductor device 120C of fig. 6 and the semiconductor device 120A of fig. 2 is that the semiconductor device 120C only includes the first through vias V1 on the left of the drawing and does not include the first through vias V1 on the right of the drawing of fig. 2. In addition, another major difference between the semiconductor device 120C of FIG. 6 and the semiconductor device 120A of FIG. 2 is that the second conductive component M12 below the plane of the drawing includes only the first conductive segment C1 and does not include the second conductive segment C2, the third conductive segment C3, and the third connecting via V3 below the plane of the drawing of FIG. 2.
In the embodiment of fig. 6, since the projection range of the second conductive component M12 on the plane formed by the directions X and Y and the projection range of the polysilicon layer 1221 on the plane formed by the directions X and Y are less overlapped (the overlapping portions of the second conductive segment C2 and the third conductive segment C3 below the plane of the drawing of fig. 2 and the polysilicon layer 1221 are less overlapped), the capacitance (e.g., parasitic capacitance) can be more effectively reduced and the loop formation can be reduced, so as to improve the quality factor value.
In some embodiments, the semiconductor devices 120C of fig. 6 may be repeatedly arranged and connected along a direction. For example, the semiconductor device 120C of fig. 6 may be repeatedly arranged and connected along the direction X to form a larger semiconductor device and may be used in applications requiring larger dimensions.
In summary, the semiconductor device of the present disclosure can utilize two metal layers to realize the mos capacitor structure and the patterned shielding structure, and can improve the quality factor value.
Although the present disclosure has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made by one skilled in the art without departing from the spirit and scope of the disclosure, and therefore, the scope of the disclosure should be limited only by the appended claims.
Claims (10)
1. A semiconductor device disposed below an inductor, wherein the semiconductor device comprises:
a metal oxide semiconductor capacitor structure, comprising:
a polysilicon layer;
an oxidation definition layer; and
a first metal layer connecting the polysilicon layer and the oxide definition layer; and
a patterned shielding structure disposed on the MOS capacitor structure and including a second metal layer.
2. The semiconductor device of claim 1, wherein said first metal layer comprises a first conductive component and at least a second conductive component, wherein said first conductive component is connected to said polysilicon layer through a first connecting via, and said at least a second conductive component is connected to said oxide definition layer through a second connecting via.
3. The semiconductor device of claim 2, wherein said at least one second conductive portion is H-shaped.
4. The semiconductor device of claim 2, wherein a first projected area of said first conductive element on a plane is within a second projected area of said second metal layer on said plane.
5. The semiconductor device of claim 2, wherein said at least one second conductive feature is connected to said second metal layer by a third connecting via.
6. The semiconductor device of claim 5, wherein said at least one second conductive feature comprises:
a first conductive segment connected to the oxide definition layer through the second connection via;
a second conductive segment connected to the second metal layer through the third connecting via; and
and a third conductive segment connecting the first conductive segment and the second conductive segment, wherein the first conductive segment is parallel to the second conductive segment.
7. The semiconductor device according to claim 5, wherein a first wiring direction of the first plurality of connection vias is perpendicular to a second wiring direction of the second plurality of connection vias.
8. The semiconductor device of claim 2, wherein said first conductive component is configured to receive a first voltage and said second metal layer is configured to receive a second voltage.
9. The semiconductor device of claim 2, wherein said at least one second conductive portion is rectangular.
10. A metal oxide semiconductor capacitor structure disposed under a patterned shielding structure, wherein the metal oxide semiconductor capacitor structure comprises:
a polysilicon layer;
an oxidation definition layer; and
a first metal layer connected to the polysilicon layer through a first via and connected to the oxide definition layer through a second via, wherein the patterned shielding structure comprises a second metal layer, and the first metal layer is connected to the second metal layer through a third via.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010722652.1A CN113972258B (en) | 2020-07-24 | 2020-07-24 | Semiconductor device and metal oxide semiconductor capacitor structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010722652.1A CN113972258B (en) | 2020-07-24 | 2020-07-24 | Semiconductor device and metal oxide semiconductor capacitor structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113972258A true CN113972258A (en) | 2022-01-25 |
| CN113972258B CN113972258B (en) | 2024-04-12 |
Family
ID=79585538
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010722652.1A Active CN113972258B (en) | 2020-07-24 | 2020-07-24 | Semiconductor device and metal oxide semiconductor capacitor structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113972258B (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6294834B1 (en) * | 2000-01-21 | 2001-09-25 | United Microelectronics Corp. | Structure of combined passive elements and logic circuit on a silicon on insulator wafer |
| US20050101116A1 (en) * | 2003-11-10 | 2005-05-12 | Shih-Hsien Tseng | Integrated circuit device and the manufacturing method thereof |
| TW200614490A (en) * | 2004-10-29 | 2006-05-01 | Phoenix Prec Technology Corp | Multi-layer capacitance semiconductor structure and fabrication method thereof |
| US20100283926A1 (en) * | 2008-07-03 | 2010-11-11 | Seiconductor Manufacturing International (Shanghai) Corporation | Method and resulting capacitor structure for liquid crystal on silicon display devices |
| US20140361401A1 (en) * | 2013-06-05 | 2014-12-11 | Semiconductor Manufacturing International (Shanghai) Corporation | Patterned ground shield structures and semiconductor devices |
-
2020
- 2020-07-24 CN CN202010722652.1A patent/CN113972258B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6294834B1 (en) * | 2000-01-21 | 2001-09-25 | United Microelectronics Corp. | Structure of combined passive elements and logic circuit on a silicon on insulator wafer |
| US20050101116A1 (en) * | 2003-11-10 | 2005-05-12 | Shih-Hsien Tseng | Integrated circuit device and the manufacturing method thereof |
| TW200614490A (en) * | 2004-10-29 | 2006-05-01 | Phoenix Prec Technology Corp | Multi-layer capacitance semiconductor structure and fabrication method thereof |
| US20100283926A1 (en) * | 2008-07-03 | 2010-11-11 | Seiconductor Manufacturing International (Shanghai) Corporation | Method and resulting capacitor structure for liquid crystal on silicon display devices |
| US20140361401A1 (en) * | 2013-06-05 | 2014-12-11 | Semiconductor Manufacturing International (Shanghai) Corporation | Patterned ground shield structures and semiconductor devices |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113972258B (en) | 2024-04-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11024622B2 (en) | Integrated circuit having angled conductive feature | |
| US9478533B2 (en) | Method and apparatus for forming an integrated circuit with a metalized resistor in a standard cell configuration | |
| KR101166032B1 (en) | Integrated semiconductor inductor and method therefor | |
| US9524964B2 (en) | Capacitor structure in an integrated circuit | |
| US9673145B2 (en) | Semiconductor integrated circuit layout structure | |
| JP2010045133A (en) | Semiconductor integrated circuit | |
| US9941270B2 (en) | Semiconductor device and design method of same | |
| CN112490360B (en) | Semiconductor device with a semiconductor device having a plurality of semiconductor chips | |
| US8841774B2 (en) | Semiconductor device including a first wiring having a bending portion a via | |
| US20080158772A1 (en) | Common centroid symmetric structure capacitor | |
| JP2008112974A (en) | Semiconductor capacitive element | |
| US11557535B2 (en) | Semiconductor device and metal-oxide-semiconductor capacitor structure | |
| US11616012B2 (en) | Patterned shielding structure | |
| CN113972258A (en) | Semiconductor device and metal oxide semiconductor capacitor structure | |
| US20210225998A1 (en) | Patterned shielding structure and integrated inductor | |
| US20210091173A1 (en) | Capacitor structure | |
| US10692967B1 (en) | High density self-routing metal-oxide-metal capacitor | |
| KR101487591B1 (en) | Mom capacitor | |
| CN112582379B (en) | Patterned shielding structure | |
| US20230097424A1 (en) | Inductor device | |
| US11830659B2 (en) | Shielding structure and inductor device | |
| US20210368614A1 (en) | Power line structure | |
| WO2019196354A1 (en) | Inductor stack structure | |
| JP7371151B2 (en) | switch module | |
| JP2006269604A (en) | Power terminal structure for hard macro cell |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |