JP2008112974A - Semiconductor capacitor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor capacitive element in which a capacitance per unit area is large, and the manufacture variations in the capacitance is small, and a Q value is high, and a self-resonant frequency is high. <P>SOLUTION: Each of a first wiring layer and a second wiring layer includes a wire group on an input side and a wire group on an output side. A lead-out wire included in the wire group on the input side in the first wiring layer and a lead-out wire included in the wire group on the input side in the second wiring layer are disposed so as to overlap with each other when viewed from a direction of lamination of the wiring layers. A lead-out wire included in the wire group on the output side in the first wiring layer and a lead-out wire included in the wire group on the output side in the second wiring layer are disposed so as to overlap with each other when viewed from the direction of lamination of the wiring layers. The wires which generate capacitances three-dimensionally intersect with each other when viewed from the direction of lamination of the wiring layers. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor capacitor using a metal wiring built in a semiconductor integrated circuit, and more particularly to a semiconductor capacitor having a large capacity and a small number of masks required for a semiconductor process.

  In a semiconductor integrated circuit, a capacitor is indispensable. The first characteristic required for the capacitive element is that the capacitance per unit area is large. This is because if the capacitance per unit area is large, the chip size can be reduced and the cost can be reduced. Second, the Q value is high. This is because if the Q value is high, the loss is reduced and the noise characteristics of the circuit are improved. Third, there is little variation in characteristics. This is because if the variation in characteristics is small, the variation margin of the circuit can be reduced and power consumption can be reduced.

  Semiconductor capacitor elements include MOS capacitors, MIM capacitors, fringe capacitors, and the like. These capacitive elements have merits and demerits with respect to the above-described three characteristics, and are selectively used depending on the application. Among these, the fringe capacitance has a small Q value per unit area as compared with others, but has a high Q value characteristic and a low variation characteristic in RF (Radio Frequency). Furthermore, there is an advantage that the number of masks to be used can be reduced as compared with an MIM capacitor that requires an additional mask for using a thin dielectric layer.

  FIG. 21 is a configuration diagram of a semiconductor capacitor element 110 which is an example of a conventional one-layer fringe capacitor described in Patent Document 1. In FIG. Further, (1) in FIG. 21 is a plan view, and (2) is a sectional view. In the semiconductor capacitor 110, capacitance is generated between the input side metal wiring 4-1 and the output side metal wiring 4-2 by electric field coupling in the left-right direction toward FIG. 21. The semiconductor capacitance element 110 has a structure in which comb shapes are combined to increase the capacitance per unit area.

  FIG. 22 is a configuration diagram of a semiconductor capacitor element 115 which is an example of a conventional multilayer fringe capacitor described in Patent Document 2. In FIG. The semiconductor capacitor 115 has a configuration in which the semiconductor capacitors 110 of FIG. 21 are stacked in the vertical direction and the upper and lower metal wirings are connected by vias. With this configuration, in the semiconductor capacitor 115, in addition to the horizontal electric field coupling between the metal wirings, the horizontal electric field coupling between the vias is added, so that the capacitance per unit area increases.

  FIG. 23 is a configuration diagram of a semiconductor capacitor element 120 which is an example of a conventional multilayer fringe capacitor described in Patent Document 3. In the semiconductor capacitor 120, the metal wiring 4-4 is disposed above the lower metal wiring 4-1, and the metal wiring 4-3 is disposed above the lower metal wiring 4-2. With this configuration, in the semiconductor capacitor 120, in addition to the horizontal electric field coupling between adjacent metal wirings, the electric field coupling between the upper metal wiring and the lower metal wiring is added. As a result, in the semiconductor capacitor 120, the capacitance per unit area increases.

FIG. 24 is a configuration diagram of a semiconductor capacitor element 125 which is an example of a conventional multilayer fringe capacitor described in Patent Document 4. In FIG. As shown in FIG. 24, in the semiconductor capacitor 125, the lower-layer metal wirings A1, B1, A2, and B2 are arranged in parallel to each other, and the metal wiring in the direction perpendicular to the metal wirings A1, B1, A2, and B2 is disposed on the upper layer. A3, B3, A4, B4 are arranged in parallel to each other, and further, metal wirings A5, B5, A6, B6 are arranged in parallel to each other in a direction perpendicular to the metal wirings A3, B3, A4, B4. It is. Here, FIG. 25 is a diagram for explaining the reason why the capacitance per unit area increases due to the configuration of the semiconductor capacitive element 125. As shown in FIG. 25, electric lines of force run obliquely from the side surface of the metal wiring B3 to the lower metal wiring A1 and the upper metal wiring A5. That is, capacitance is generated between the side surface of the metal wiring B3, the upper surface of the metal wiring A1, and the lower surface of the metal wiring A5. As a result, in the semiconductor capacitor 125, the capacitance per unit area is increased.
Japanese Patent No. 3209253 Special table 2003-530699 gazette JP-A-7-283076 Japanese Patent Laid-Open No. 11-168182

  The semiconductor capacitance element 110 in FIG. 21 has a small capacitance per unit area. The semiconductor capacitance element 115 in FIG. 22 has a large capacitance per unit area. However, since the capacitance between adjacent vias is used, the mass production variation of capacitance increases. The semiconductor capacitance element 120 of FIG. 23 uses the capacitance generated between the upper and lower layers of the metal wiring to increase the capacitance per unit area. However, like the semiconductor capacitance element 125 of FIG. No electrostatic capacitance is generated by electric lines of force that run from the side of the wiring to the lower and upper metal wirings (see FIG. 25). Accordingly, the capacitance per unit area of the semiconductor capacitor 120 in FIG. 23 is smaller than that of the semiconductor capacitor 115 in FIG. 22 and the semiconductor capacitor 125 in FIG.

  The semiconductor capacitance element 125 in FIG. 24 has a large capacitance per unit area and a small variation in production of capacitance. FIG. 26 is a diagram of the semiconductor capacitor 125 viewed from the stacking direction of the metal wiring. F, G, H, and I in FIG. 26 show four side surfaces of the semiconductor capacitor 125, where the side surface F and the side surface H face each other, and the side surface G and the side surface I face each other. As shown in FIG. 26, the extraction wiring 145 included in the comb metal wiring 140 on the input side is provided along the side surface F, and the extraction wiring 146 included in the comb metal wiring 141 on the output side faces the side surface F. It is provided along the side surface H. In the comb-shaped metal wirings 142 and 143 provided below the metal wirings 140 and 141, the extraction wiring 147 included in the input-side metal wiring 143 is provided along the side surface G, and is connected to the output-side metal wiring 142. The included extraction wiring 148 is provided along the side surface I facing the side surface G. On the input side, the upper extraction wiring 145 and the lower extraction wiring 147 are connected to each other by the extraction wiring 149 and led out of the semiconductor capacitor element 125. Similarly, on the output side, the upper extraction wiring 146 and the lower extraction wiring 148 are connected by the extraction wiring 150 and drawn out of the semiconductor capacitor element 125.

  As described above, the semiconductor capacitance element 125 has a configuration in which the side surface provided with the extraction wiring included in the comb-shaped metal wiring is replaced for each layer of the metal wiring. As a result, as shown in FIG. 26, extraction wirings 149 and 150 having a long wiring length are required. As a result, the chip occupation area of the extraction wiring increases, and in addition, the parasitic resistance and parasitic inductance of the extraction wiring increase. For example, in the case of a rectangular semiconductor capacitance element 125 having a side length of 100 μm, the lengths of the extraction wirings 149 and 150 on the input side and the output side need to be about 100 μm, respectively. And 0. A parasitic inductance of several nH is generated. As a result, the semiconductor capacitor 125 has a problem that the Q value is lowered due to the increase in parasitic resistance and parasitic inductance, and the self-resonance frequency is lowered.

  In order to shorten the wiring length of the extraction wirings 149 and 150, as shown in FIG. 27, the extraction wirings 149 and 150 are connected to the corner portions where the extraction wirings included in the comb-shaped metal wirings of each layer are adjacent to each other. A method is conceivable. However, in this method, it is necessary to connect the extraction wiring 149 or 150 to the ends of the extraction wirings 145 to 148. Therefore, when the extraction wiring 149 or 150 is connected to the center of the extraction wirings 145 to 148 (see FIG. 26). The parasitic resistance and the parasitic inductance generated in the extraction wirings 145 to 148 are increased compared to the reference). As a result, even if the wiring lengths of the extraction wirings 149 and 150 are shortened as shown in FIG. 27, the semiconductor capacitor 125 has a low Q value due to an increase in parasitic resistance and parasitic inductance, and the self-resonance frequency is reduced The problem of being lowered arises.

  Therefore, an object of the present invention is to provide a semiconductor capacitor element having a large capacitance per unit area, a small manufacturing variation of the capacitance, a high Q value, and a high self-resonant frequency.

  The present invention is directed to a semiconductor capacitor element having a structure in which N (N is an integer of 2 or more) wiring layers are stacked. In order to achieve the above object, the semiconductor capacitance element of the present invention includes a K layer metal wiring provided in a Kth (K is any one of 1 to N−1) wiring layer, and a K + 1th wiring layer. The K + 1 layer metal wiring and the K + 1 layer metal wiring are respectively provided with a plurality of first predetermined shape wirings formed by regularly coupling first unit straight lines and the plurality of the plurality of first predetermined shape wirings. A plurality of second predetermined shape wirings formed by regularly connecting first unit wirings, a first wiring group including an extraction wiring for connecting the first predetermined shape wiring to the first terminal, and the plurality of second predetermined shape wirings; A plurality of first predetermined shape wirings and the plurality of second predetermined shape wirings are identical to each other. In the wiring layer, the first and second layers of the K layer are alternately arranged at equal intervals. The extraction wiring of the line group and the extraction wiring of the first wiring group of the (K + 1) layer are arranged at positions overlapping in the stacking direction of the wiring layers and connected to each other, and the extraction wiring of the second wiring group of the K layer and the first wiring group of the (K + 1) layer are connected. The lead-out wirings of the two wiring groups are arranged at positions overlapping in the wiring layer stacking direction and connected to each other, and in the wiring layer stacking direction, the first unit straight wiring of the K layer and the second unit straight line of the K + 1 layer The wiring intersects three-dimensionally, and the first unit straight wiring in the K + 1 layer and the second unit straight wiring in the K layer intersect three-dimensionally in the stacking direction of the wiring layers.

  Further, the first predetermined shape wiring is a zigzag wiring formed by coupling the first unit straight wiring in a zigzag shape, and the second predetermined shape wiring is a second unit straight wiring coupled in a zigzag shape. The zigzag wiring formed may be used.

  Further, the K layer metal wiring further includes zigzag floating wirings adjacent to the outer periphery of the region where the zigzag wirings are arranged at equal intervals with the zigzag wirings at both ends of the arranged zigzag wirings. The K + 1 layer metal wiring further includes zigzag floating wirings adjacent to the outer periphery of the region where the zigzag wirings are arranged at equal intervals with the zigzag wirings at both ends of the arranged zigzag wirings. Also good.

  Further, in the stacking direction of the wiring layer, vias that respectively connect portions where the zigzag wiring connected to the first terminal of the K layer and the zigzag wiring connected to the first terminal of the K + 1 layer overlap, In the stacking direction of the wiring layers, there are further provided vias that connect portions where the zigzag wiring connected to the second terminal of the K layer and the zigzag wiring connected to the second terminal of the K + 1 layer overlap each other. May be.

  Further, among the bent portions of the K layer zigzag wiring, the floating wiring provided at the position of the K + 1 layer corresponding to the outer peripheral bent portion located in the outer periphery of the region where the zigzag wiring is arranged A floating wiring provided at the position of the K layer corresponding to the outer peripheral bent portion located in the outer periphery of the region where the zigzag wiring is arranged in the bent portion of the K + 1 layer zigzag wiring; A via connecting each of the K-layer outer periphery bent portion and the K + 1 layer floating wiring and a via connecting each of the K + 1 layer outer bent portion and the K layer floating wiring may be further provided.

  The shapes of the K + 1 layer floating wiring and the K layer floating wiring may be square, triangular, or pentagonal.

  Further, the first predetermined shape wiring is a quadrangular wiring formed by connecting four first unit straight wirings into a quadrangular shape, and the second predetermined shape wiring is a cross between two second unit straight wirings. The K-shaped quadrangular wiring and the (K + 1) -thick quadrangular wiring are respectively connected by vias and connected to the first terminal, and the K-layer cross-shaped wiring and the K + 1 wiring are connected to the first terminal. The cross-shaped wirings of the layers may be connected to the second terminals by vias, respectively.

  Moreover, it is preferable that the angle of intersection is 90 degrees.

  As described above, according to the present invention, it is possible to arrange the input-side wirings provided in the plurality of wiring layers and the extraction wirings included in the output-side wirings to be aligned at the same position by using the zigzag-shaped wirings. . Thus, according to the present invention, it is possible to realize a semiconductor capacitor element having a large capacitance per unit area, a small manufacturing variation of the capacitance, a high Q, and a high self-resonance frequency.

(First embodiment)
FIG. 1 is a diagram illustrating a configuration example of the semiconductor capacitor 10 according to the first embodiment. As shown in FIG. 1, the semiconductor capacitor 10 includes a first wiring layer indicated by a solid line and a second wiring layer indicated by a dotted line. The first wiring layer includes a metal wiring 11 on the signal input side (hereinafter simply referred to as input side), a metal wiring 12 on the signal output side (hereinafter simply referred to as output side), and an extraction wiring 17 on the input side. And an output-side extraction wiring 18. Note that the input side and the output side may be reversed. The input side metal wiring 11 includes an input side extraction wiring 13, and the output side metal wiring 12 includes an output side extraction wiring 14. An extraction wiring 17 connected to an input side terminal (not shown) of the semiconductor capacitor 10 is connected to the center of the extraction wiring 13, and an output side terminal of the semiconductor capacitance element 10 ( A take-out wiring 18 connected to (not shown) is connected. The second wiring layer includes an input side metal wiring 15 and an output side metal wiring 16. The input side metal wiring 15 includes an input side extraction wiring 23 (not shown), and the output side metal wiring 16 includes an output side extraction wiring 24 (not shown). The first wiring layer and the second wiring layer overlap, and the input-side metal wiring 11 and the metal wiring 15 are connected by vias 19 and 20 that are conductors. Similarly, the output side metal wiring 12 and the metal wiring 16 are connected by vias 21 and 22 which are conductors.

  FIG. 2 is a diagram for explaining the metal wiring provided in the first wiring layer provided in the semiconductor capacitor 10. As shown in FIG. 2, the metal wiring 11 has a configuration in which two wirings (hereinafter referred to as a zigzag shape) in which straight lines are bent alternately left and right (hereinafter referred to as a zigzag shape) are connected by an extraction wiring 13. is there. Note that the zigzag wiring can be considered as a wiring formed by regularly combining one unit of linear wiring (unit linear wiring) indicated by an arrow in FIG. Similarly, the metal wiring 12 has a configuration in which two zigzag wirings are connected by an extraction wiring 14. The angle of the zigzag-shaped bending of the zigzag-shaped wiring is 90 °. Further, the zigzag wiring of the metal wiring 11 and the zigzag wiring of the metal wiring 12 are alternately arranged at equal intervals in the first wiring layer with the same zigzag period as shown in FIG. .

  FIG. 3 is a diagram for explaining wirings included in the second wiring layer included in the semiconductor capacitor 10. As shown in FIG. 3, the metal wiring 15 has a configuration in which two zigzag wirings are connected by an extraction wiring 23, and the metal wiring 16 has two zigzag wirings connected by an extraction wiring 24. It is a configuration. The angle of the zigzag-shaped bending of the zigzag-shaped wiring is 90 °. Further, the zigzag wiring of the metal wiring 15 and the zigzag wiring of the metal wiring 16 are alternately arranged in the second wiring layer at equal intervals with the same zigzag period as shown in FIG. .

  Here, referring again to FIG. 1, the zigzag wiring of the first wiring layer (see FIG. 2) and the zigzag wiring of the second wiring layer (see FIG. 3) in the semiconductor capacitor 10. The positional relationship will be described. As shown in FIG. 1, the zigzag wiring of the metal wirings 11 and 12 arranged in the first wiring layer shown by the solid line and the metal wirings 15 and 16 arranged in the second wiring layer shown by the dotted line. The zigzag wiring is arranged with the period of the zigzag shape shifted by a half period in the stacking direction of the first and second wiring layers.

  With the configuration described above, as shown in FIG. 1, the zigzag wiring included in the input-side metal wiring 11 arranged in the first wiring layer and the output-side metal wiring 16 arranged in the second wiring layer are provided. The zigzag wiring included in the circuit has a plurality of orthogonal portions in the stacking direction of the first and second wiring layers. Similarly, the zigzag wiring provided in the output-side metal wiring 12 arranged in the first wiring layer and the zigzag wiring provided in the input-side metal wiring 15 arranged in the second wiring layer are: And a plurality of orthogonal portions in the stacking direction of the second wiring layer. As a result, the semiconductor capacitor 10 can obtain the same effects as those described with reference to FIG. 25 in the conventional semiconductor capacitor 125 (see FIG. 24 and FIG. 26). Specifically, the side surfaces of the zigzag wiring provided in the input side metal wiring 11 arranged in the first wiring layer and the zigzag wiring provided in the output side metal wiring 16 arranged in the second wiring layer are provided. Capacitance is generated between the upper surface. Further, the side surface of the zigzag wiring provided in the output side metal wiring 16 arranged in the second wiring layer and the lower surface of the zigzag wiring provided in the input side metal wiring 11 arranged in the first wiring layer. Capacitance is generated between them. Similarly, the side surface of the zigzag wiring included in the output-side metal wiring 12 disposed in the first wiring layer, and the upper surface of the zigzag wiring included in the input-side metal wiring 15 disposed in the second wiring layer, Capacitance is generated between the two. Further, the side surface of the zigzag wiring provided in the input side metal wiring 15 arranged in the second wiring layer and the lower surface of the zigzag wiring provided in the output side metal wiring 12 arranged in the first wiring layer. Capacitance is generated between them. As a result, in the semiconductor capacitor 10, the capacitance per unit area can be increased as in the conventional semiconductor capacitor 125.

  Here, as shown in FIGS. 1 to 3, in the semiconductor capacitor 10, unlike the conventional semiconductor capacitor 125, the input-side extraction wires 13 and 23 are the same in the stacking direction of the first and second wiring layers. Further, the output side extraction wires 14 and 24 are provided on the same side surface (position). Further, the input side extraction wirings 13 and 23 are connected by vias 19 and 20, and the output side extraction wirings 14 and 24 are connected by vias 21 and 22. Thus, the semiconductor capacitor 10 may be connected to the extraction wiring 17 on the input-side extraction wiring 13 and connected to the extraction wiring 14 on the output side. As a result, the semiconductor capacitance element 10 can reduce the wiring length of the extraction wiring as compared with the conventional semiconductor capacitance element 125 shown in FIG. 26, so that parasitic resistance and parasitic inductance generated in the extraction wiring are suppressed. Can do.

  Further, in the semiconductor capacitor 10, the extraction wiring 17 is connected to the central portion of the extraction wiring 13, and the extraction wiring 18 is connected to the central portion of the extraction wiring 14. As a result, the semiconductor capacitor 10 is connected to the ends of the extraction wires 145 and 147 and the extraction wiring 150 is connected to the ends of the extraction wires 146 and 148, and the semiconductor capacitance element 125 shown in FIG. In comparison, parasitic resistance and parasitic inductance generated in the extraction wirings 13, 14, 23, and 24 can be reduced.

  In addition, the semiconductor capacitor element 10 does not have vias in portions that generate capacitance (portions of zigzag wiring). When a via is formed, since the zigzag wiring needs to be thickened, the capacity per unit area is reduced. From this, according to the semiconductor capacitive element 10, it is possible to realize a capacitive element with high area efficiency of the generated capacitance.

  As described above, the semiconductor capacitor 10 has a large capacitance per unit area and a small manufacturing variation of the capacitance, similarly to the conventional semiconductor capacitor 125. In addition, the semiconductor capacitor 10 can reduce parasitic resistance and parasitic inductance compared to the conventional semiconductor capacitor 125. As a result, according to the semiconductor capacitive element 10, it is possible to provide a semiconductor capacitive element that has a large capacitance per unit area, a small manufacturing variation of the capacitance, a high Q value, and a high self-resonance frequency. Can do.

  In FIG. 1, the tip of the zigzag wiring of the semiconductor capacitor 10 has an acute angle shape. Depending on the semiconductor process, an acute-angle wiring may violate the rule. In this case, for example, as shown in FIG. 4, the semiconductor capacitor 10 may have a shape obtained by cutting an acute-angled portion at the tip of the zigzag wiring. In the above description, the zigzag wiring of the first wiring layer and the zigzag wiring of the second wiring layer are three-dimensionally intersected at 90 ° (see FIG. 1). As shown in FIG. 6, the zigzag wiring of the first wiring layer and the zigzag wiring of the second wiring layer may be three-dimensionally intersected at 90 ° or more and 90 ° or less. In the above description, the two-layer semiconductor capacitor element including the first wiring layer and the second wiring layer has been described. However, the wiring layer may have three or more layers. In this case, the capacitance per unit area can be further increased. In the above description, the number of zigzag wirings provided in each wiring layer has been described as four. However, the number of zigzag wirings provided in each wiring layer is not limited to four. Further, in the above, in the stacking direction of the first and second wiring layers, the zigzag wiring included in the input-side metal wiring 11 disposed in the first wiring layer and the output disposed in the second wiring layer. The zigzag wiring provided in the side metal wiring 16 intersects three-dimensionally at a plurality of locations, and the zigzag wiring provided in the output side metal wiring 12 arranged in the first wiring layer and the second wiring The zigzag wiring provided in the input side metal wiring 15 arranged in the layer intersects three-dimensionally at a plurality of locations. However, it is sufficient that there are one or more intersections, and furthermore, the intersections may be overlapped without intersecting. In this case, the total amount of capacitance generated on the side surface of the zigzag wiring is smaller than in the case of having a plurality of intersections.

  Further, as shown in FIG. 7, floating wirings 25 and 26 that are the same shape as the zigzag wiring of the metal wirings 11 and 12 and are not connected to either of the metal wirings 11 and 12 are replaced with zigzags of the metal wirings 11 and 12. The positions of the outer periphery of the area where the shape wirings are arranged, adjacent to the zigzag wirings at both ends with an equal interval, and arranged in the first wiring layer, respectively. Similarly, the zigzag of the metal wirings 15 and 16 is arranged. Floating wirings 27 and 28 having the same shape as the shape wiring may be arranged in the second wiring layer. As a result, the metal wiring portion that generates the electrostatic capacitance can be flattened, so that the variation in the electrostatic capacitance of the semiconductor capacitive element 10 can be reduced.

  Below, the electrostatic capacitance which generate | occur | produces in the semiconductor capacitive element 10 of FIG. 1 is demonstrated. FIG. 8 is a diagram for explaining the capacitance generated in the semiconductor capacitor 10 of FIG. The capacitance generated in the semiconductor capacitance element 10 is roughly classified into four types of capacitances shown in FIGS. 8A to 8D show a plan view, a cross-sectional view, and a generated capacitance of the zigzag wiring, respectively. The capacitance shown in FIG. 8A is a line capacitance in the same layer direction generated between the wirings of the first wiring layer and between the wirings of the second wiring layer. The electrostatic capacitance shown in FIG. 8B is a line-to-line capacitance generated between the wiring of the first wiring layer and the wiring of the second wiring layer. The capacitance shown in FIG. 8C is between the cross wirings generated between one side surface and the other upper surface (or lower surface) of the wirings of the first wiring layer and the second wiring layer that intersect each other. Fringe capacity. The electrostatic capacitance shown in FIG. 8D is generated between one side surface and the other upper surface (or lower surface) of the wiring of the first wiring layer and the wiring of the second wiring layer which are in a parallel positional relationship. This is the fringe capacity between parallel wires.

  Here, in the conventional semiconductor capacitance element 125 (see FIG. 24), the capacitances shown in FIGS. 8A to 8C are generated, but the capacitance shown in FIG. 8D is not generated. . That is, the capacitance shown in FIG. 8D is further generated in the semiconductor capacitive element 10 of the present invention as compared with the conventional semiconductor capacitive element 125.

Hereinafter, the optimum value of the intersection angle (hereinafter simply referred to as the intersection angle) between the wiring of the first wiring layer and the wiring of the second wiring layer will be considered. A case is calculated in which the wiring of the first wiring layer (upper layer) and the wiring of the second wiring layer (lower layer) intersect at an angle θ when viewed from the stacking direction of both wiring layers. FIG. 9 is a diagram showing a unit cell of the semiconductor capacitor 10. FIG. 9A shows a front view of the unit cell, and FIG. 9B shows a cross-sectional view of the unit cell. A portion surrounded by a thick quadrilateral in FIG. 9A is a unit cell. Further, the wiring of the first wiring layer (upper layer) is indicated by a solid line, and the wiring of the second wiring layer (lower layer) is indicated by a dotted line. Here, the width of the wiring of the first and second wiring layers is W ₁ and the thickness is T. Let S ₁ be the spacing between the wirings in the first wiring layer and the spacing between the wirings in the second wiring layer. Let H be the distance between the wiring in the first wiring layer and the wiring in the second wiring layer. In this case, the area of the unit cell is calculated by Equation 1.

Using equation 1, the line capacitance C _side in the same layer direction shown in FIG. 8A per unit cell is calculated by equation 2. Note that ε _γ is a relative dielectric constant, and ε ₀ is a dielectric constant in a vacuum.

The line capacity C _{plate in the} stacking direction shown in FIG. 8B per unit cell is calculated by Equation 3.

The fringe capacity between the cross wirings shown in FIG. 8C and the fringe capacity between the parallel wirings shown in FIG. 8D are calculated together as the fringe capacity C _fringe per unit cell. The dependence of the fringe capacity C _{fringe on} the crossing angle differs depending on whether the crossing angle θ is an acute angle or an obtuse angle. Therefore, in the following, description will be made with classification.

First, the case where the intersection angle θ is an acute angle will be described. FIG. 10 is a diagram for calculating the fringe capacity C _fringe per unit cell when the intersection angle θ is an acute angle. FIG. 10A shows the wiring of the unit cell shown in FIG. 9A as one wiring of the first wiring layer (hereinafter referred to as wiring 1) and one second wiring for convenience of explanation. It is the front view represented as wiring (henceforth wiring 2) only of this wiring layer. As shown in FIG. 10A, an l axis and an h axis that are orthogonal to each other with the point O as the origin are defined. The l-axis and the h-axis are located in the first wiring layer, and the l-axis is along the side surface of the wiring 1. In addition, FIG.10 (b) is a figure of the FF cross section of Fig.10 (a).

配線１のｈ軸方向の側面の微小区間ｄｌと配線２の上面との間のフリンジ容量ｄＣ／ｄｌを、領域１〜５において求めて８倍することで、単位セル当たりのフリンジ容量Ｃ_fringeを式５に示すように計算する。

In the following, as shown in FIG. 10A, the fringe capacity per unit length is calculated for each of five regions (regions 1 to 5) along the l axis. Regions 1 to 5 can be represented by Equation 4.

By determining the fringe capacitance dC / dl between the minute section dl on the side surface in the h-axis direction of the wiring 1 and the upper surface of the wiring 2 in the regions 1 to 5 and multiplying it by eight, the fringe capacitance C _fringe per unit cell is obtained. Calculate as shown in Equation 5.

但し、配線１のｈ軸方向の側面と、配線２を除く第２の配線層の配線の上面と間のフリンジ容量は、十分小さく無視できるものとする。 First, the fringe capacitance dC / dl between the minute section dl on the side surface in the h-axis direction of the wiring 1 and the upper surface of the wiring 2 in the regions 1 and 5 is calculated. In the region 1, it can be considered that the wiring 1 itself is connected to a side surface (cross section) along the l-axis of the wiring 1. In the region 5, there is no wiring 2 on the h axis direction side of the wiring 1 (see FIG. 10A). For this reason, the fringe capacitance dC / dl between the minute section dl on the side surface in the h-axis direction of the wiring 1 and the upper surface of the wiring 2 in the regions 1 and 5 is calculated by Expression 6.

However, the fringe capacity between the side surface in the h-axis direction of the wiring 1 and the upper surface of the wiring in the second wiring layer excluding the wiring 2 is sufficiently small and can be ignored.

そして、領域２における、配線１のｈ軸方向の側面の微小区間ｄｌと配線２の上面との間のフリンジ容量ｄＣ／ｄｌは、式８で計算される。

Next, the fringe capacitance dC / dl between the minute section dl on the side surface in the h-axis direction of the wiring 1 and the upper surface of the wiring 2 in the region 2 is calculated. Here, as shown in FIGS. 10A and 10B, the width of the cross section of the wiring 2 in the FF cross section at an arbitrary distance from the point O is W _2, and the wiring 1 generated in the h-axis direction And the space between the wiring 2 and S ₂ . In this case, in the region 2, as is understood from FIG.

Then, the fringe capacitance dC / dl between the minute section dl on the side surface in the h-axis direction of the wiring 1 and the upper surface of the wiring 2 in the region 2 is calculated by Expression 8.

また、領域３では、Ｗ₂ は式１０で表される。

そして、領域３における、配線１のｈ軸方向の側面の微小区間ｄｌと配線２の上面との間のフリンジ容量ｄＣ／ｄｌは、式８で計算される。 Next, the fringe capacitance dC / dl between the minute section dl on the side surface in the h-axis direction of the wiring 1 and the upper surface of the wiring 2 in the region 3 is calculated. In region 3, S ₂ is expressed by Equation 9.

In region 3, W ₂ is expressed by Equation 10.

Then, the fringe capacitance dC / dl between the minute section dl on the side surface in the h-axis direction of the wiring 1 and the upper surface of the wiring 2 in the region 3 is calculated by Expression 8.

そして、領域４における、配線１のｈ軸方向の側面の微小区間ｄｌと配線２の上面との間のフリンジ容量は、式８にＳ₂ ＝０を代入した式１２で計算される。

Next, the fringe capacitance dC / dl between the minute section dl on the side surface in the h-axis direction of the wiring 1 and the upper surface of the wiring 2 in the region 4 is calculated. In the region 4, as can be seen from FIG. 10A, S ₂ = 0. In region 4, W ₂ is expressed by Equation 11.

Then, the fringe capacity between the minute section dl on the side surface in the h-axis direction of the wiring 1 and the upper surface of the wiring 2 in the region 4 is calculated by Expression 12 in which S ₂ = 0 is substituted into Expression 8.

By calculating the expression 5 using the fringe capacity dC / dl in the regions 1 to 5 calculated above, the fringe capacity C _fringe per unit cell when the intersection angle θ is an acute angle can be calculated.

Next, the case where the intersection angle θ is an obtuse angle will be described. FIG. 11 is a diagram for calculating the fringe capacity C _fringe per unit cell when the intersection angle θ is an obtuse angle. FIG. 11A shows the wiring of the unit cell shown in FIG. 9A as one wiring of the first wiring layer (hereinafter referred to as wiring 1) and one second wiring for convenience of explanation. It is the front view represented as wiring (henceforth wiring 2) only of this wiring layer. As shown in FIG. 11A, an l-axis and an h-axis that are orthogonal to each other with the point O as the origin are defined. The l-axis and the h-axis are located in the first wiring layer, and the l-axis is along the side surface of the wiring 1. In addition, FIG.11 (b) is a figure of the GG cross section of Fig.11 (a). FIG.11 (c) is a figure of the G'-G 'cross section of Fig.11 (a).

配線１のｌ軸に沿った側面の微小区間ｄｌと配線２の上面との間のフリンジ容量ｄＣ／ｄｌを、領域１及び２において求めて８倍することで、単位セル当たりのフリンジ容量Ｃ_fringeを式１４に示すように計算する。

In the following, as shown in FIG. 11A, the fringe capacity per unit length is calculated for each of two regions (regions 1 and 2) along the l-axis. Here, θ ′ = 180 ° −θ. Regions 1 and 2 can be represented by Equation 13.

The fringe capacitance dC / dl between the minute interval dl on the side surface along the l-axis of the wiring 1 and the upper surface of the wiring 2 is obtained in the regions 1 and 2 and multiplied by 8 to obtain the fringe capacitance C _fringe per unit cell. Is calculated as shown in Equation 14.

First, in the region 2, the fringe capacitance between the minute interval dl on the side surface along the l-axis of the wiring 1 and the upper surface of the wiring 2 is calculated. In the region 2, the wiring 1 itself exists in the h-axis direction from the side surface along the l-axis of the wiring 1. As a result, the electric lines of force that emerge from the side surface along the l-axis of the wiring 1 are blocked. As a result, the fringe capacity between the minute interval dl on the side surface along the l-axis of the wiring 1 and the upper surface of the wiring 2 in the region 2 is calculated by Expression 15.

但し、領域１−２及び領域１−３は、θ’の大きさによっては、領域１には存在しない。図１１（ａ）に示した位置関係（θ’の大きさ）では、領域１−２の一部及び領域１−３は、領域１に存在しないが、説明の便宜のために、存在するものとして図１１（ａ）に示している。 Next, the fringe capacitance between the minute interval dl on the side surface along the l axis of the wiring 1 and the upper surface of the wiring 2 in the region 1 is calculated. Here, the region 1 is divided into three regions (regions 1-1 to 1-3) as shown in FIG. Region 1-1 to region 1-3 can be expressed by Equation 16.

However, the region 1-2 and the region 1-3 do not exist in the region 1 depending on the magnitude of θ ′. In the positional relationship (the magnitude of θ ′) shown in FIG. 11A, a part of the region 1-2 and the region 1-3 are not present in the region 1, but are present for convenience of explanation. This is shown in FIG.

そして、領域１−１における、配線１のｌ軸に沿った側面の微小区間ｄｌと配線２の上面との間のフリンジ容量は、図１０（ａ）の領域２の説明で用いた式８で計算される。 The fringe capacitance between the minute section dl on the side surface along the l-axis of the wiring 1 and the upper surface of the wiring 2 in the region 1-1 is calculated. Here, as shown in FIGS. 11A and 11B, the width of the cross-section of the wiring 2 in the GG cross-sectional view of the region 1-1 is W _2, and the wiring 1 and the wiring 2 generated in the h-axis direction. Let S ₂ be the space. In this case, Expression 17 holds in the area 1-1.

The fringe capacity between the minute section dl on the side surface along the l-axis of the wiring 1 and the upper surface of the wiring 2 in the area 1-1 is expressed by the equation 8 used in the description of the area 2 in FIG. Calculated.

そして、領域１−２における、配線１のｌ軸に沿った側面の微小区間ｄｌと配線２の上面との間のフリンジ容量は、図１０（ａ）の領域４の説明で用いた式１２で計算される。 The fringe capacitance between the minute section dl on the side surface along the l axis of the wiring 1 and the upper surface of the wiring 2 in the region 1-2 is calculated. In the area 1-2, as is understood from FIG. 11A, Expression 18 is established.

Then, the fringe capacitance between the minute section dl on the side surface along the l-axis of the wiring 1 and the upper surface of the wiring 2 in the region 1-2 is expressed by the equation 12 used in the description of the region 4 in FIG. Calculated.

  The fringe capacitance between the minute interval dl on the side surface along the l-axis of the wiring 1 and the upper surface of the wiring 2 in the region 1-3 is calculated. Here, as shown in FIGS. 11A and 11C, the wiring 2 is divided into two in the region 1-3. In the area 1-3, the wiring 2 closer to the wiring 1 is defined as a wiring 2a, and the wiring 2 far from the wiring 1 is defined as a wiring 2b. In the following, calculation is performed separately for the wiring 2a and the wiring 2b.

そして、領域１−３における、配線１のｌ軸に沿った側面の微小区間ｄｌと配線２ａの上面との間のフリンジ容量は、図１０（ａ）の領域４の説明で用いた式１２で計算される。 First, the fringe capacitance between the minute section dl on the side surface along the l-axis of the wiring 1 and the upper surface of the wiring 2a is calculated. As shown in FIG. 11C, Equation 19 holds for S ₂ and W ₂ .

Then, the fringe capacitance between the minute section dl on the side surface along the l-axis of the wiring 1 and the upper surface of the wiring 2a in the region 1-3 is expressed by the equation 12 used in the description of the region 4 in FIG. Calculated.

そして、領域１−３における、配線１のｌ軸に沿った側面の微小区間ｄｌと配線２ｂの上面との間のフリンジ容量は、図１０（ａ）の領域２の説明で用いた式８で計算される。 Next, the fringe capacitance between the minute interval dl on the side surface along the l-axis of the wiring 1 and the upper surface of the wiring 2b is calculated. As shown in FIG. 11C, Expression 20 holds for S ₂ and W ₂ .

The fringe capacity between the minute section dl on the side surface along the l-axis of the wiring 1 and the upper surface of the wiring 2b in the area 1-3 is expressed by the equation 8 used in the description of the area 2 in FIG. Calculated.

  In the region 1-3, the fringe capacitance between the minute section dl on the side surface along the l-axis of the wiring 1 and the upper surface of the wiring 2 is calculated by the fringe capacity for the wiring 2a and the fringe capacity for the wiring 2b calculated above. It becomes the sum of.

  And the fringe capacity | capacitance about the area | region 1 becomes the sum total of the fringe capacity | capacitance about the area | region 1-1-the area | region 1-3.

The fringe capacity C _fringe per unit cell when the intersection angle θ is an obtuse angle can be calculated by calculating the expression 14 using the fringe capacity dC / dl in the regions 1 and 2 calculated above.

As a calculation result described above, the capacitance C ₀ (θ) per unit area generated in the semiconductor capacitor 10 is calculated by Equation 21.

FIG. 12 is a diagram illustrating a calculation result of the capacitance C ₀ (θ) per unit area generated in the semiconductor capacitor 10 when the intersection angle θ is changed from 0 ° to 180 °. For comparison, FIG. 12 shows a calculation result of the capacitance per unit area generated in the conventional semiconductor capacitance element 125 (see FIG. 24). As shown in FIG. 12, the maximum value of the capacitance per unit area is substantially equal between the semiconductor capacitor 10 of the present invention and the conventional semiconductor capacitor 125. However, at the intersection angle θ = 90 ° and in the vicinity thereof, the capacitance per unit area of the semiconductor capacitive element 10 of the present invention is larger.

FIG. 13 is a diagram illustrating a calculation result of the capacitance C ₀ (θ) per unit area of the semiconductor capacitor 10 when W ₁ and S ₁ are changed. FIG. 14 is a diagram illustrating a calculation result of the capacitance C ₀ (θ) per unit area of the semiconductor capacitor 10 when T and H are changed. 13 (a) shows, the W ₁ 0.5 times, shows the 1-fold and 2-fold and the capacitance C ₀ per unit area when the (theta), FIG. 13 (b), the S ₁ 0. The electrostatic capacity C ₀ (θ) per unit area when 5 times, 1 time and 2 times are shown. 14A shows the capacitance C ₀ (θ) per unit area when T is multiplied by 0.5, 1 and 2, and FIG. 14B shows H by 0.5. The electrostatic capacity C ₀ (θ) per unit area when it is multiplied by 1 and 2 is shown. As shown in FIGS. 13 and 14, even if W ₁ , S ₁ , T, and H change, the capacitance C ₀ (θ) per unit area of the semiconductor capacitive element 10 is the crossing angle θ = 90 °. It becomes the maximum or a value very close to the maximum. Therefore, even when W ₁ , S ₁ , T, and H change, at the crossing angle θ = 90 ° and in the vicinity thereof, the capacitance per unit area of the semiconductor capacitive element 10 of the present invention is It is larger than the capacitance per unit area of the conventional semiconductor capacitance element 125.

  Here, in general, the capacity device is designed and manufactured easily when the crossing angle θ is 90 °. In the conventional semiconductor capacitance element 125, the capacitance per unit area is greatly reduced at the intersection angle θ = 90 °, which is easy to manufacture. On the other hand, as described above, in the semiconductor capacitive element 10 of the present invention, the capacitance per unit area becomes a maximum value or a value very close to the maximum at an intersection angle θ = 90 °, which is easy to manufacture. As a result, it can be said that the semiconductor capacitor 10 of the present invention is more practical than the conventional semiconductor capacitor 125.

(Second Embodiment)
FIG. 15 is a diagram illustrating a configuration example of the semiconductor capacitor 50 according to the second embodiment. As shown in FIG. 15, the semiconductor capacitor 50 includes a zigzag bent portion of the input-side metal wiring 11 provided in the first wiring layer, compared to the configuration of the semiconductor capacitor 10 according to the first embodiment. And vias 51 to 59 for connecting the zigzag bent portions of the input-side metal wiring 15 provided in the second wiring layer, respectively, and the output-side metal wiring 12 provided in the first wiring layer. This zigzag bent portion is further provided with vias 60 to 68 that connect the zigzag bent portion of the output-side metal wiring 16 provided in the second wiring layer, respectively. In the semiconductor capacitance element 50, the same components as those of the semiconductor capacitance element 10 are denoted by the same reference numerals, and the description thereof is omitted.

  With the above configuration, the semiconductor capacitor 50 has vias 51 to 51 that connect the metal wiring of the first wiring layer and the metal wiring of the second wiring layer as compared with the semiconductor capacitor 10 according to the first embodiment. Since 68 electric field couplings are added, the capacitance per unit area can be further increased.

  In the above description, vias are provided in the zigzag bent portion of the metal wiring. However, the zigzag shape of the input-side metal wiring 11 provided in the first wiring layer in the stacking direction of the first and second wiring layers. The portions where the wiring and the zigzag wiring of the input side metal wiring 15 provided in the second wiring layer overlap are connected by vias, and similarly, the zigzag of the output side metal wiring 12 provided in the first wiring layer is connected. A portion where the shape wiring overlaps with the zigzag wiring of the output side metal wiring 16 provided in the second wiring layer may be connected by a via.

  FIG. 16 is a diagram illustrating a configuration of a first modification of the semiconductor capacitor 50. The configuration of the first modification will be described below with reference to FIG. The first modification includes the following configuration in addition to the configuration of the semiconductor capacitor 50 (see FIG. 15).

  In the first modified example, the outer peripheral bent portions 69 to 74 located on the outer periphery of the region where the zigzag wiring is arranged, out of the square bent portions provided in the zigzag wiring arranged in the first wiring layer. Vias 81 to 86 connected to the. Further, in the first modification, the floating wirings 75 to 80 having the same square shape as that of the outer peripheral bent portions 69 to 74 are arranged on the second wiring layer and the outer peripheral bent portion 69 of the first wiring layer. To 74 are respectively provided at positions projected onto the second wiring layer by the parallel light irradiated in the stacking direction of the first and second wiring layers. The floating wirings 75 to 80 are connected to the vias 81 to 86, respectively. In other words, in the first modification, the respective outer peripheral bent portions 69 to 74 of the first wiring layer are connected to the respective floating wirings 75 to 80 by the respective vias 81 to 86. Similarly, in the first modified example, the outer periphery bent portion located in the outer periphery of the area where the zigzag wiring is arranged, among the bent portions of the square shape provided in the zigzag wiring arranged in the second wiring layer. Vias 93 to 98 connected to 87 to 92 are provided. Further, in the first modification, the floating wirings 99 to 104 having the same square shape as that of the outer peripheral bent portions 87 to 92 are arranged on the first wiring layer and the outer peripheral bent portion 87 of the second wiring layer. To 92 are respectively provided at positions projected onto the first wiring layer by the parallel light irradiated in the stacking direction of the first and second wiring layers. The floating wirings 99 to 104 are connected to the vias 93 to 98, respectively. In other words, in the first modification, the outer peripheral bent portions 87 to 92 of the second wiring layer are connected to the floating wirings 99 to 104 by the vias 93 to 98, respectively.

  With such a configuration, electrolytic coupling generated by the floating wirings 75 to 80 and the zigzag wiring of the metal wiring 15 or 16 adjacent to the floating wirings 75 to 80, and the floating wirings 99 to 104 and the floating wirings 99 to 104 are adjacent. The electrolytic coupling generated by the zigzag wiring of the metal wiring 11 or 12 is added. As a result, the first modification of the semiconductor capacitor 50 can further increase the capacitance per unit area as compared with the semiconductor capacitor 50 (see FIG. 15).

  FIG. 17 is a diagram illustrating a configuration of a second modification of the semiconductor capacitor 50. As shown in FIG. 17, in the second modification, the shapes of the floating wirings 75 to 80 and 99 to 104 in the first modification shown in FIG. 16 are changed from a square shape to a triangular shape. The floating wirings 75 to 80 have a triangular shape having the largest area while keeping a predetermined distance from the adjacent zigzag wirings provided in the same wiring layer (second wiring layer) as the floating wirings 75 to 80. The Similarly, the floating wirings 99 to 104 have a triangular shape having the largest area while keeping a predetermined distance from an adjacent zigzag wiring provided in the same wiring layer (first wiring layer) as the floating wirings 99 to 104. Is done.

  With such a configuration, the areas of the floating wirings 75 to 80 and 99 to 104 of the second modification are larger than the areas of the floating wirings 75 to 80 and 99 to 104 of the first modification (FIG. 16 and FIG. 16). See FIG. As a result, in the second modified example, the electrolytic coupling caused by the floating wirings 75 to 80 and the zigzag wiring of the metal wiring 15 or 16 adjacent to the floating wirings 75 to 80, the floating wirings 99 to 104, and the floating wiring 99. The electrolytic coupling caused by the zigzag wiring of the metal wiring 11 or 12 adjacent to .about.104 is larger than that of the first modification. As a result, the second modification example of the semiconductor capacitor element 50 can further increase the capacitance per unit area as compared with the first modification example of the semiconductor capacitor element (see FIG. 16).

  In the second modification described above, as shown in FIG. 17, the two inner angles of the triangular shapes of the floating wirings 75 to 80 and 99 to 104 are smaller than 90 °. Here, depending on the semiconductor process, such a shape may violate the rule. FIG. 18 is a diagram illustrating a configuration of a third modification of the semiconductor capacitor 50. Therefore, for example, as shown in FIG. 18, the floating wirings 75 to 80 and 99 to 104 have a pentagonal shape obtained by cutting two corners having an inner angle smaller than 90 ° of the triangular shape. In this modification, it is possible to avoid a violation of the rules of the semiconductor process while obtaining substantially the same effect as in the second modification.

(Third embodiment)
FIG. 19 is a diagram illustrating a configuration example of a semiconductor capacitor element 200 according to the third embodiment of the present invention. As shown in FIG. 19A, the semiconductor capacitor element 200 includes a first wiring layer indicated by a solid line and a second wiring layer indicated by a dotted line. FIG. 19B shows the wiring of the first wiring layer. FIG. 19C shows the wiring of the second wiring layer. The semiconductor capacitor element 200 is different from the semiconductor capacitor element 10 of the first embodiment (see FIG. 1) in that the metal wiring 11 is replaced with a metal wiring 11-1, the metal wiring 12 is replaced with a metal wiring 12-1, In this configuration, the metal wiring 15 is replaced with the metal wiring 15-1, and the metal wiring 16 is replaced with the metal wiring 16-1. FIG. 20 is a diagram illustrating the metal wirings 11-1, 12-1, 15-1, and 16-1. 20A shows the metal wirings 11-1 and 12-1, and FIG. 20B shows the metal wirings 15-1 and 16-1. As shown in FIGS. 20A and 20B, the metal wirings 11-1, 12-1, 15-1 and 16-1 have the zigzag wiring shape of the metal wirings 11, 12, 15 and 16, respectively. The wiring is changed. In FIGS. 20A and 20B, the wiring located in the first wiring layer is indicated by a solid line, and the wiring located in the second wiring layer is indicated by a dotted line. In the semiconductor capacitive element 200, the same components as those of the semiconductor capacitive element 10 are denoted by the same reference numerals, and redundant description is omitted.

  Below, the shape of metal wiring 11-1, 12-1, 15-1, and 16-1 is demonstrated. As shown in FIG. 20A, the metal wiring 11-1 includes rectangular wirings (hereinafter referred to as square wirings) 301, 302, 303, and 304. Note that the square wiring can be considered as a wiring in which four linear wirings (unit linear wiring) of one unit indicated by a black arrow in FIG. The square wiring 301 is located in the first wiring layer and is connected to the extraction wiring 13. The square wiring 302 is located in the second wiring layer and is connected to the square wiring 301 by the via 204. The square wiring 303 is located in the first wiring layer and is connected to the square wiring 302 by the via 205. The square wiring 304 is located in the second wiring layer and is connected to the square wiring 303 by the via 206. Here, the square wirings 301 and 304 have a shape in which a quadrangle is cut due to space restrictions.

  The metal wiring 12-1 is a wiring (hereinafter referred to as a cross wiring) 401, 402, 403 having a shape in which one unit of linear wiring (unit linear wiring) indicated by a white arrow in FIG. And 404. The cross wiring 401 is located in the first wiring layer and is connected to the extraction wiring 14. The cross wiring 402 is located in the second wiring layer and is connected to the cross wiring 401 by the via 203. The cross wiring 403 is located in the first wiring layer and is connected to the cross wiring 402 by the via 202. The cross wiring 404 is located in the second wiring layer and is connected to the cross wiring 403 by the via 201. Here, the cross wirings 401 and 404 have a shape in which the cross shape is cut due to space restrictions.

  Next, as shown in FIG. 20B, the metal wiring 15-1 includes square wirings 305, 306, 307 and 308. The square wiring 305 is located in the second wiring layer and is connected to the extraction wiring 23. The square wiring 306 is located in the first wiring layer and is connected to the square wiring 305 by the via 207. The square wiring 307 is located in the second wiring layer and is connected to the square wiring 306 by the via 208. The square wiring 308 is located in the first wiring layer and is connected to the square wiring 307 by the via 209. Here, the square wirings 305 and 308 have a shape in which a square is cut due to space restrictions.

  The metal wiring 16-1 includes cross wirings 405, 406, 407 and 408. The cross wiring 405 is located in the second wiring layer and is connected to the extraction wiring 24. The cross wiring 406 is located in the first wiring layer and is connected to the cross wiring 405 by the via 212. The cross wiring 407 is located in the second wiring layer and is connected to the cross wiring 406 by the via 211. The cross wiring 408 is located in the first wiring layer and is connected to the cross wiring 407 by the via 210. Here, the cross wirings 405 and 408 have a shape in which the cross shape is cut due to space limitations.

  Next, the positional relationship between the square wiring of the metal wirings 11-1 and 15-1 and the cross wiring of the metal wirings 12-1 and 16-1 will be described. The wiring of the first wiring layer shown in FIG. 19B will be described. As shown in FIG. 19B, in the first wiring layer, the square wiring and the cross wiring are alternately arranged with a predetermined interval S therebetween. More specifically, the unit straight line constituting the square line and the unit straight line constituting the cross line are arranged in parallel with a predetermined interval S therebetween. Similarly to the wiring of the first wiring layer shown in FIG. 19B, the wiring of the second wiring layer shown in FIG. 19C also has a predetermined interval S between the square wiring and the cross wiring. Alternatingly arranged. Also, as shown in FIGS. 19A, 20A, and 20B, the unit linear wiring that forms the square wiring of the first wiring layer and the unit that forms the cross wiring of the second wiring layer. The straight wiring intersects three-dimensionally when viewed from the stacking direction of the wiring layers. Similarly, the unit straight line constituting the square wiring of the second wiring layer and the unit straight line constituting the cross wiring of the first wiring layer intersect three-dimensionally as viewed from the stacking direction of the wiring layers.

  Here, when the semiconductor process is miniaturized, the gate of the field effect transistor is easily broken electrostatically. This is because when the metal wiring length in the IC is long, the metal wiring serves as an antenna and receives static electricity from the outside. For this reason, there may be a limitation on the metal wiring length in the same wiring layer.

  The semiconductor capacitor 200 does not use a zigzag wiring having a long wiring length (see FIG. 1) but uses a square wiring and a cross wiring (see FIGS. 19 and 20) having a short wiring length. Therefore, the semiconductor capacitor element 200 according to the third embodiment can shorten the metal wiring length in the same wiring layer as compared with the semiconductor capacitor element 10 according to the first embodiment using the zigzag wiring. As a result, the semiconductor capacitor element 200 according to the third embodiment obtains the same effect as the semiconductor capacitor element 10 according to the first embodiment, and further, static electricity generated by the metal wiring serving as an antenna. It is possible to avoid the electric breakdown and satisfy the limit of the metal wiring length.

  The unit straight wiring of the first wiring layer and the unit straight wiring of the second wiring layer preferably cross three-dimensionally at 90 ° when viewed from the stacking direction of the wiring layers, but are not limited thereto. It is not a thing. In the above description, the two-layer semiconductor capacitor element including the first wiring layer and the second wiring layer has been described. However, the wiring layer may have three or more layers. In this case, the capacitance per unit area can be further increased. Further, the number of square wirings and cross wirings provided in each wiring layer is not limited to the number described above.

  INDUSTRIAL APPLICABILITY The present invention can be used for a semiconductor capacitor element between metal wirings built in a semiconductor integrated circuit, and in particular, increases the capacitance per unit area of the semiconductor capacitor element and reduces the manufacturing variation of the capacitance. In addition, it is useful for increasing the Q value and increasing the self-resonance frequency.

1 is a diagram illustrating a configuration example of a semiconductor capacitor 10 according to a first embodiment. The figure for demonstrating the wiring provided in the 1st wiring layer with which the semiconductor capacitive element 10 which concerns on 1st Embodiment is provided. The figure for demonstrating the wiring with which the 2nd wiring layer with which the semiconductor capacitive element 10 which concerns on 1st Embodiment is provided is equipped. The figure which shows another structural example of the semiconductor capacitive element 10 which concerns on 1st Embodiment. The figure which shows another structural example of the semiconductor capacitive element 10 which concerns on 1st Embodiment. The figure which shows another structural example of the semiconductor capacitive element 10 which concerns on 1st Embodiment. The figure which shows another structural example of the semiconductor capacitive element 10 which concerns on 1st Embodiment. The figure for demonstrating the electrostatic capacitance which generate | occur | produces in the semiconductor capacitive element 10 which concerns on 1st Embodiment. The figure which shows the unit cell of the semiconductor capacitive element 10 which concerns on 1st Embodiment. FIG. 7 is a diagram for calculating the fringe capacitance C _fringe per unit cell when the crossing angle θ of the semiconductor capacitor 10 according to the first embodiment is an acute angle. FIG. 6 is a diagram for calculating the fringe capacitance C _fringe per unit cell when the crossing angle θ of the semiconductor capacitor 10 according to the first embodiment is an obtuse angle. The figure which shows the calculation result of electrostatic capacitance _C0 ((theta)) per unit area which generate | occur | produces in the semiconductor capacitive element 10 when crossing angle (theta) is changed from 0 degree to 180 degrees. Graph showing the calculation results of the W ₁ and the capacitance C ₀ per unit area of the semiconductor capacitive element 10 when each changing the S ₁ (θ) The figure which shows the calculation result of electrostatic capacitance _C0 ((theta)) per unit area of the semiconductor capacitive element 10 when T and H are each changed. The figure which shows the structural example of the semiconductor capacitance element 50 which concerns on 2nd Embodiment. The figure which shows the structure of the 1st modification of the semiconductor capacitance element 50 which concerns on 2nd Embodiment. The figure which shows the structure of the 2nd modification of the semiconductor capacitance element 50 which concerns on 2nd Embodiment. The figure which shows the structure of the 3rd modification of the semiconductor capacitance element 50 which concerns on 2nd Embodiment. The figure which shows the structural example of the semiconductor capacitive element 200 which concerns on 3rd Embodiment. The figure which shows the metal wiring 11-1, 12-1, 15-1, and 16-1 of the semiconductor capacitive element 200 which concerns on 3rd Embodiment. Configuration diagram of a semiconductor capacitor element 110 which is an example of a conventional one-layer fringe capacitor described in Patent Document 1 Structure diagram of a semiconductor capacitor element 115 as an example of a conventional multi-layer fringe capacitor described in Patent Document 2 Configuration diagram of a semiconductor capacitor element 120 as an example of a conventional multilayer fringe capacitor described in Patent Document 3 Configuration diagram of a semiconductor capacitor element 125 as an example of a conventional multi-layer fringe capacitor described in Patent Document 4 The figure for demonstrating the reason for the electrostatic capacitance per unit area increasing with the structure of the conventional semiconductor capacitive element 125. A view of a conventional semiconductor capacitor element 125 as viewed from the direction of metal wiring lamination A view of a conventional semiconductor capacitor element 125 as viewed from the direction of metal wiring lamination

Explanation of symbols

10, 50, 110, 115, 120, 125, 200 Semiconductor capacitor element 11, 12, 15, 16, 75-80, 99-104, 140-143, 4-1, 4-2, 4-3, 4- 4, A1-A6, B1-B6 Metal wiring 13, 14, 17, 18, 23, 24, 145-150 Extraction wiring 19-21, 51-68, 81-86, 93-98, 201-212 Via 25- 28 Floating wiring 69-74, 87-92 Bent part 301-308 Square wiring 401-408 Cross wiring

Claims (11)

A semiconductor capacitor element having a structure in which N (N is an integer of 2 or more) wiring layers are stacked,
K layer metal wiring provided in the Kth (K is any one of 1 to N-1) wiring layer;
K + 1 layer metal wiring provided in the (K + 1) th wiring layer,
The K layer metal wiring and the K + 1 layer metal wiring are respectively
A first wiring group comprising a plurality of first predetermined shape wirings formed by regularly combining first unit straight wirings and an extraction wiring for connecting the plurality of first predetermined shape wirings to a first terminal; ,
A second wiring group comprising a plurality of second predetermined shape wirings formed by regularly joining the second unit straight wirings and an extraction wiring for connecting the plurality of second predetermined shape wirings to the second terminal; Including
The plurality of first predetermined shape wires and the plurality of second predetermined shape wires are alternately arranged at equal intervals in the same wiring layer,
The extraction wiring of the first wiring group of the K layer and the extraction wiring of the first wiring group of the K + 1 layer are arranged at positions overlapping in the stacking direction of the wiring layers and connected to each other,
The extraction wiring of the second wiring group of the K layer and the extraction wiring of the second wiring group of the K + 1 layer are arranged at positions overlapping in the stacking direction of the wiring layer, and are connected to each other.
In the stacking direction of the wiring layer, the first unit straight wiring of the K layer and the second unit straight wiring of the K + 1 layer each intersect three-dimensionally.
In the stacking direction of the wiring layer, the first unit straight line in the K + 1 layer and the second unit straight line in the K layer each intersect three-dimensionally. The first predetermined shape wiring is a zigzag wiring formed by joining the first unit straight lines in a zigzag shape,
2. The semiconductor capacitor according to claim 1, wherein the second predetermined shape wiring is a zigzag wiring formed by joining the second unit straight lines in a zigzag shape.   The semiconductor capacitance element according to claim 2, wherein each of the intersection angles is 90 °. The K layer metal wiring further includes zigzag floating wirings adjacent to the outer periphery of the region where the zigzag wirings are arranged at equal intervals with the zigzag wirings at both ends of the arranged zigzag wirings. Prepared,
The K + 1 layer metal wiring further includes zigzag floating wirings adjacent to the outer periphery of the region where the zigzag wirings are arranged at equal intervals with the zigzag wirings at both ends of the arranged zigzag wirings. The semiconductor capacitance element according to claim 2, further comprising: In the stacking direction of the wiring layer, the portions where the zigzag wiring connected to the first terminal of the K layer and the zigzag wiring connected to the first terminal of the (K + 1) layer overlap are respectively connected. With vias,
In the stacking direction of the wiring layers, the portions where the zigzag wiring connected to the second terminal of the K layer and the zigzag wiring connected to the second terminal of the (K + 1) layer overlap are respectively connected. The semiconductor capacitor according to claim 2, further comprising a via. Among the bent portions of the K layer zigzag wiring, the floating wiring provided at the position of the K + 1 layer corresponding to the outer peripheral bent portion located in the outer periphery of the region where the zigzag wiring is arranged in the stacking direction of the wiring layers. When,
Floating wiring provided at the position of the K layer corresponding to the outer peripheral bent portion located in the outer periphery of the region where the zigzag wiring is arranged in the bent portion of the K + 1 layer zigzag wiring. When,
Vias connecting the outer peripheral bent portion of the K layer and the floating wiring of the K + 1 layer, respectively;
The semiconductor capacitance element according to claim 2, further comprising vias that respectively connect the outer peripheral bent portion of the K + 1 layer and the floating wiring of the K layer.   The semiconductor capacitor according to claim 6, wherein the K + 1 layer floating wiring and the K layer floating wiring are square in shape.   7. The semiconductor capacitor according to claim 6, wherein the shape of the K + 1 layer floating wiring and the K layer floating wiring is triangular.   The semiconductor capacitor according to claim 6, wherein the K + 1 layer floating wiring and the K layer floating wiring are pentagonal in shape. The first predetermined shape wiring is a quadrangular wiring formed by combining the four first unit straight wirings into a quadrangular shape,
The second predetermined shape wiring is a cross-shaped wiring formed by combining two second unit straight wirings in a cross shape,
The quadrangular wiring of the K layer and the quadrangular wiring of the K + 1 layer are each connected by a via and connected to the first terminal,
2. The semiconductor capacitor according to claim 1, wherein the cross-shaped wiring of the K layer and the cross-shaped wiring of the K + 1 layer are connected to each other by a via and connected to the second terminal. .   The semiconductor capacitor according to claim 10, wherein the crossing angles are 90 °.

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