CN113823637B - Electronic Devices - Google Patents

Abstract

The invention discloses an electronic device which comprises a flexible substrate, anisotropic conductive adhesive and an electronic element. The flexible substrate comprises an active region, a bonding pad and a plurality of protrusions positioned on the bonding pad. The anisotropic conductive paste includes a plurality of conductive particles, wherein the conductive particles contact the protrusions. The anisotropic conductive adhesive is located between the bonding pad of the flexible substrate and the electronic element. By arranging the protrusions on the bonding pads of the flexible substrate, the contact area between the conductive particles of the anisotropic conductive adhesive and the flexible substrate can be increased. By making the conductive particles contact the protrusions, the deformation amount of the conductive particles can be increased, and the bonding stability between the electronic device and the flexible substrate can be improved. Furthermore, in embodiments in which the conductive particles have an insulating layer, the provision of protrusions is also advantageous for breaking through the insulating layer. In this way, in the bonding process, the external force required to achieve effective contact between the electronic component and the flexible substrate can be reduced, and thus the collapse of the bonding pad of the flexible substrate can be avoided.

Description

Electronic Devices

Technical Field

The invention relates to an electronic device, in particular to an electronic device with a protrusion located on a bonding pad.

Background technique

The surface of the bonding pad in the existing electronic device is flat. In order to allow the conductive particles in the anisotropic conductive adhesive to effectively deform and contact the conductive layer of the bonding pad, there must be enough contact area between the conductive particles and the bonding pad to achieve effective contact. In order to ensure effective contact between the conductive particles and the bonding pad, a larger bonding pressure is required. In electronic devices using flexible substrates, a larger bonding pressure will cause the bonding pad area of the flexible substrate to sink.

In view of this, how to provide a flexible substrate that can prevent the flexible substrate from collapsing due to bonding pressure is still one of the goals that the industry urgently needs to develop.

Summary of the invention

The object of the present invention is to provide an electronic device which can prevent the bonding pad of a flexible substrate from collapsing.

In one embodiment, an electronic device comprises a flexible substrate, an anisotropic conductive adhesive and an electronic component. The flexible substrate comprises an active region, a bonding pad and a plurality of protrusions on the bonding pad. The anisotropic conductive adhesive comprises a plurality of conductive particles, wherein the conductive particles contact the protrusions. The anisotropic conductive adhesive is located between the bonding pad of the flexible substrate and the electronic component.

In one embodiment, each protrusion has a width ranging from 1 micron to 2 microns.

In one embodiment, each protrusion has a height ranging from 0.1 micrometer to 1 micrometer.

In one embodiment, there is a distance between two adjacent protrusions, and the distance is in a range of 1.2 microns to 2 microns.

In one embodiment, each protrusion has a width, each conductive particle has a diameter, the width is greater than 20% of the diameter and less than 3 times of the diameter.

In one embodiment, each protrusion has a height, each conductive particle has a diameter, the height is greater than 5% of the diameter, and the height is less than 30% of the diameter.

In one embodiment, there is a spacing between two adjacent protrusions, each conductive particle has a diameter, the spacing is greater than 50% of the diameter of the conductive particle, and the spacing is less than 3 times of the diameter of the conductive particle.

In one embodiment, the conductive particles have a deformation amount greater than 15%.

In one embodiment, the protrusion includes a passivation layer having a thickness in a range of 0.3 microns to 0.4 microns.

In one embodiment, the passivation layer has a plurality of segments.

In one embodiment, the protrusion includes a gate insulating layer having a thickness in a range of 0.3 microns to 0.4 microns.

In one embodiment, the gate insulating layer has a plurality of segments.

In one embodiment, vertical projections of the segments of the gate insulating layer on the flexible substrate overlap with the segments of the gate insulating layer respectively.

In one embodiment, a portion of the passivation layer is located between two adjacent segments of the gate insulation layer and extends onto the bonding pad.

In one embodiment, the protrusion further includes an amorphous silicon layer located between the passivation layer and the gate insulating layer, the amorphous silicon layer having a thickness ranging from 0.05 microns to 0.15 microns.

In one embodiment, the passivation layer has a plurality of segments, and the amorphous silicon layer has a plurality of segments.

In one embodiment, a vertical projection of a section of the passivation layer on the flexible substrate at least partially overlaps with a vertical projection of a section of the amorphous silicon layer on the flexible substrate.

In one embodiment, the gate insulating layer has a plurality of segments, a vertical projection of a segment of the gate insulating layer on the flexible substrate overlaps with a segment of the gate insulating layer, and a vertical projection of a segment of the gate insulating layer overlaps with a segment of the amorphous silicon layer on the flexible substrate.

In one embodiment, the protrusion further includes a gate insulating layer and an amorphous silicon layer, wherein the amorphous silicon layer is located between the passivation layer and the gate insulating layer, wherein the gate insulating layer has a plurality of segments, and the amorphous silicon layer has a plurality of segments.

In one embodiment, a portion of the passivation layer is located between two adjacent segments of the gate insulation layer and extends onto the bonding pad.

In the above embodiment, by providing a protrusion on the bonding pad of the flexible substrate, the contact area between the conductive particles of the anisotropic conductive adhesive and the flexible substrate can be increased. In other words, by making the conductive particles contact the protrusion, the deformation of the conductive particles can be increased, thereby improving the bonding stability between the electronic device and the flexible substrate. In addition, in the embodiment where the conductive particles have an insulating layer, providing the protrusion is also conducive to breaking through the insulating layer. In this way, in the bonding process, the external force required to achieve effective contact between the electronic component and the flexible substrate can be reduced, thereby avoiding the collapse of the bonding pad of the flexible substrate.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view of an electronic device according to an embodiment of the present invention.

FIG. 2A is an enlarged view of area A in FIG. 1 .

FIG. 2B is an enlarged view of area B in FIG. 1 .

FIG. 3 is a cross-sectional view of a flexible substrate according to an embodiment of the present invention.

FIG. 4A is a top view of a flexible substrate according to an embodiment of the present invention, wherein a portion of the active region is omitted.

FIG. 4B is a top view of a flexible substrate according to an embodiment of the present invention, wherein a portion of the active region is omitted.

FIG. 5 is a partial enlarged view of the protrusion and the bonding pad in FIG. 3 .

6A to 6F are cross-sectional views of protrusions and bonding pads according to different embodiments of the present invention, respectively.

Description of main reference numerals:

10-electronic device; 100, 100a-flexible substrate; 102-first metal layer; 104, 104S, 104D-second metal layer; 106-third metal layer; 108-protective layer; 110, 110a, 110b, 110c, 110d, 110e, 110f, 110g-protrusion; 112, 122-gate insulating layer; 112S-upper surface; 112W-side wall; 1122A, 1122B, 1122C-segment; 114, 124-amorphous silicon layer; 114S-upper surface; 114W-side wall; 11 42A, 1142B, 1142C-segments; 116, 126-passivation layers; 116S-upper surface; 116W-sidewalls; 200-anisotropic conductive adhesive; 210-conductive particles; 212-insulating layer; 214-metal layer; 216-resin; 300-electronic components; 310-electrical connectors; A, B-areas; BP-bonding pads; AA-active areas; DA-diameter; H-height; W-width; D-spacing; I1-interval; I2-interval; D1-first direction; D2-second direction; T1-thickness; T2-thickness; T3-thickness.

Detailed ways

The following will disclose multiple embodiments of the present invention with the accompanying drawings. For the sake of clarity, many practical details will be described together in the following description. However, it should be understood that these practical details should not be used to limit the present invention. That is, in some embodiments of the present invention, these practical details are not necessary. In addition, in order to simplify the drawings, some well-known and commonly used structures and elements will be illustrated in a simple schematic manner in the drawings. And for the sake of clarity, the thickness of the layers and regions in the drawings may be exaggerated, and the same element symbols represent the same elements in the description of the drawings.

FIG. 1 is a cross-sectional view of an electronic device 10 according to an embodiment of the present invention. The electronic device 10 includes a flexible substrate 100, an anisotropic conductive adhesive 200, and an electronic component 300. FIG. 2A is an enlarged view of region A in FIG. 1. Referring to FIG. 1 and FIG. 2A simultaneously. The flexible substrate 100 includes a bonding pad BP and a protrusion 110 located on the bonding pad BP. The anisotropic conductive adhesive 200 includes a plurality of conductive particles 210, wherein the conductive particles 210 contact the protrusion 110. The anisotropic conductive adhesive 200 is located between the bonding pad BP of the flexible substrate 100 and the electronic component 300. The flexible substrate 100 and the electronic component 300 are electrically connected and bonded to each other through the anisotropic conductive adhesive 200. The electronic component 300 includes an electrical connector 310. As shown in FIG. 2A , after the electronic component 300 is bonded to the flexible substrate 100 through a bonding process, the electrical connector 310 and the bonding pad BP squeeze the conductive particles 210 , so that the electrical connector 310 and the conductive layer on the bonding pad BP (as shown in the metal layer 106 of FIG. 3 ) are electrically connected to the circuit between the electronic component 300 and the flexible substrate 100 through the conductive particles 210 .

The flexible substrate 100 is, for example, polyimide (PI), polyester (PET), a composite flexible material of PI and glass, a composite flexible material of PET and glass, or a composite flexible material of PI, optical adhesive (OCA) and PET. The electronic component 300 may be, for example, an integrated circuit (IC) or a flexible printed circuit (FPC).

The electrical connection member 310 may be, for example, a gold bump, a solder bump, a conductive pillar, or other elements used for electrical connection.

The conductive particle 210 includes an insulating layer 212, a metal layer 214, and a resin 216. The core of the conductive particle 210 includes the resin 216, and the metal layer 214 covers the resin 216. The metal layer 214 may be composed of at least one of gold (Au), silver (Ag), copper (Cu), nickel (Ni), and nickel alloy (Ni Alloy). The insulating layer 212 surrounds the metal layer 214 and the resin 216, but the present invention is not limited thereto. In some embodiments, the conductive particle 210 may not include the insulating layer 212.

As shown in FIG. 2A , by providing a protrusion 110 on the bonding pad BP of the flexible substrate 100, the contact area between the conductive particle 210 and the flexible substrate 100 can be increased. In other words, by making the conductive particle 210 contact the protrusion 110, the deformation of the conductive particle 210 can be increased, thereby improving the bonding stability between the electronic component 300 and the flexible substrate 100. In one embodiment, the deformation of the conductive particle 210 is greater than 15%, thereby improving the bonding stability between the electronic component 300 and the flexible substrate 100. In addition, in the embodiment where the conductive particle 210 has an insulating layer 212, providing the protrusion 110 is also conducive to breaking through the insulating layer 212. In this way, in the bonding process, the external force required to achieve effective contact between the electronic component 300 and the flexible substrate 100 can be reduced, thereby avoiding the collapse of the bonding pad BP of the flexible substrate 100.

As shown in FIG. 2A , the protrusion 110 has a width W, which is in the range of about 1 micron to 2 microns. The protrusion 110 has a height H, which is in the range of about 0.1 micron to 1 micron. When the electronic component 300 and the flexible substrate 100 are bonded by the bonding process, there is a gap I1 between the electrical connector 310 of the electronic component 300 and the bonding pad BP of the flexible substrate 100. There is a gap I2 between the electrical connector 310 of the electronic component 300 and the top of the protrusion 110, and the gap I2 is smaller than the gap I1. Such a structure can overcome the problem of the conductive particles 210 rebounding during environmental testing or after the electronic device 10 has been used for a long time. In other words, since the interval I2 between the electrical connector 310 and the top of the protrusion 110 is small, even if the interval I1 between the electrical connector 310 and the bonding pad BP increases with time or environmental changes, it can still be ensured that the contact area between the conductive particles 210 and the flexible substrate 100 is sufficient to maintain effective contact and effective electrical connection between the electronic component 300 and the flexible substrate 100.

FIG. 2B is an enlarged view of the area B in FIG. 1 . The conductive particles 210 may also partially contact the protrusions 110, while the other part is located on the bonding pad BP without the protrusions 110. However, the height difference generated by the protrusions 110 may also have the effect of squeezing the protrusions 110. In other words, the protrusions 110 do not need to be completely covered by the conductive particles 210, and may also have the technical effect of increasing the contact area between the conductive particles 210 and the flexible substrate 100. It can be seen from this that the size of the protrusions 110 does not need to be smaller than the size of the conductive particles 210, as long as the protrusions 110 on the bonding pads BP can increase the deformation amount of the conductive particles 210. The relationship between the size of the protrusions 110 and the size of the conductive particles 210 will be described in the subsequent paragraphs.

FIG3 is a cross-sectional view of a flexible substrate 100 according to an embodiment of the present invention. The flexible substrate 100 further includes an active area AA. In this embodiment, the flexible substrate 100 includes a plurality of protrusions 110 located on the bonding pad BP. There is a spacing D between two adjacent protrusions 110, and the spacing D is in the range of about 1.2 microns to 2 microns.

1 and 3 , the conductive particles 210 have a diameter DA. In some embodiments, the diameter DA of the conductive particles 210 is approximately in the range of about 3 microns to 10 microns, but the present invention is not limited thereto, and the user can select the appropriate size of the conductive particles 210 according to the needs. The width W of the conductive particles 210 is greater than 20% of the diameter DA, and the width W is less than 3 times the diameter DA. The height H of the conductive particles 210 is greater than 5% of the diameter DA, and the height H is less than 30% of the diameter DA. Such a structural design can ensure that the contact area between the conductive particles 210 and the flexible substrate 100 is sufficient to maintain effective contact and effective electrical connection between the electronic component 300 and the flexible substrate 100. The spacing D of the conductive particles 210 is greater than 50% of the diameter DA of the conductive particles 210, and the spacing D is less than 3 times the diameter DA of the conductive particles 210. Such a structural design can ensure that the conductive particles 210 can contact the protrusions 110 and produce a larger deformation (see FIGS. 2A and 2B ).

3 , the protrusion 110 includes a gate insulating layer 112, an amorphous silicon layer 114, and a passivation layer 116. The amorphous silicon layer 114 is located between the gate insulating layer 112 and the passivation layer 116. The amorphous silicon layer 114 contacts the gate insulating layer 112 and the passivation layer 116. The active area AA has an active array 120. The active array 120 has a gate insulating layer 122, an amorphous silicon layer 124, and a passivation layer 126. The gate insulating layer 122 of the active area AA extends to the gate insulating layer 112 above the bonding pad BP. The gate insulating layer 122 of the active area AA and the gate insulating layer 112 above the bonding pad BP can be formed in the same process step. The amorphous silicon layer 124 of the active area AA and the amorphous silicon layer 114 above the bonding pad BP can also be formed in the same process step. The passivation layer 126 of the active area AA and the passivation layer 116 above the bonding pad BP can also be formed in the same process step. A second metal layer 104S and a second metal layer 104D are disposed between the amorphous silicon layer 124 and the passivation layer 126 of the active area AA, and are respectively the source and the drain of the thin film transistor (TFT) of the active area AA.

A first metal layer 102 is provided between the flexible substrate 100 and the gate insulating layer 112, which is located on the active area AA and the bonding pad BP. A third metal layer 106, such as a transparent conductive film, is provided above the passivation layer 116 of the protrusion 110 and the passivation layer 126 of the active area AA. For example, the third metal layer 106 can be indium zinc oxide (IZO), indium tin oxide (ITO) or other transparent metal oxide films. A protective layer 108 is also provided between the passivation layer 126 of the active area AA and the third metal layer 106. The active area AA also includes a contact through hole 130, and the first metal layer 102, the second metal layer 104 and the third metal layer 106 in the contact through hole 130 are in contact with each other.

According to the above, in the process of forming the active array 120, the gate insulating layer 112, the amorphous silicon layer 114 and the passivation layer 116 having different patterns from those of the active area AA can be formed on the bonding pad BP through a patterning process. In other words, the protrusion 110 can be produced without adding process steps and can be achieved by simply adjusting the original mask design.

FIG. 4A is a top view of a flexible substrate 100 according to an embodiment of the present invention, wherein a portion of the active area AA (see FIG. 3 ) is omitted. In this embodiment, the protrusion 110 is in the shape of a long strip extending along the first direction D1. There is a spacing D between two adjacent protrusions 110 in the second direction D2. The second direction D2 is different from the first direction D1. In this embodiment, the second direction D2 is substantially perpendicular to the first direction D1.

FIG. 4B is a top view of a flexible substrate 100a according to an embodiment of the present invention, wherein a portion of the active area AA (see FIG. 3 ) is omitted. In this embodiment, the protrusion 110a is island-shaped. The width W of the protrusion 110a is substantially the diameter of the protrusion 110a. There is a distance D between two adjacent protrusions 110a.

FIG. 5 is a partial enlarged view of the protrusion 110 and the bonding pad BP in FIG. 3 . In the present embodiment, the gate insulating layer 112 of the protrusion 110 includes sections 1122A, 1122B, and 1122C. The amorphous silicon layer 114 of the protrusion 110 includes sections 1142A, 1142B, and 1142C. The sections 1122A, 1122B, and 1122C correspond to the sections 1142A, 1142B, and 1142C, respectively. In addition, the vertical projection of the amorphous silicon layer 114 on the bonding pad BP overlaps with the gate insulating layer 112. A portion of the passivation layer 116 is located between two adjacent sections 1122A, 1122B, and 1122C of the gate insulating layer 112, and this portion of the passivation layer 116 extends onto the bonding pad BP. As shown in FIG. 5 , the passivation layer 116 extending onto the bonding pad BP contacts the first metal layer 102. In the present embodiment, the passivation layer 116 covers and contacts the amorphous silicon layer 114, the gate insulating layer 112, and the first metal layer 102. The gate insulating layer 112 has a thickness T1 in the range of about 0.3 microns to 0.4 microns. The amorphous silicon layer 114 has a thickness T2 in the range of about 0.05 microns to 0.15 microns. The passivation layer 116 has a thickness T3 in the range of about 0.3 microns to 0.4 microns. The thickness of the above structure can be determined according to the requirements in the active area AA, so there is no need to change the steps of depositing the materials of the above structure.

6A to 6F are cross-sectional views of protrusions and bonding pads BP according to different embodiments of the present invention. As shown in FIG6A , the passivation layer 116 of the protrusion 110 b has multiple sections, but does not have the amorphous silicon layer 114 as shown in FIG5 . The gate insulating layer 112 is continuous and covers the first metal layer 102 and the bonding pad BP.

Referring to FIG. 6B , the passivation layer 116 and the gate insulating layer 112 of the protrusion 110 c each have a plurality of segments, and do not have the amorphous silicon layer 114 as shown in FIG. 5 . The vertical projection of the segment of the passivation layer 116 on the bonding pad BP overlaps with the segment of the gate insulating layer 112 . In addition, the width of the passivation layer 116 is smaller than the width of the gate insulating layer 112 , so a stepped protrusion 110 c can be formed. In the present embodiment, the upper surface 116S of the passivation layer 116 , the sidewall 116W of the passivation layer 116 , a portion of the upper surface 112S of the gate insulating layer 112 , and the sidewall 112W of the gate insulating layer 112 constitute the stepped profile of the protrusion 110 c. The stepped protrusion 110 c is conducive to breaking through the insulating layer 212 of the conductive particle 210 , and increasing the bonding stability between the conductive particle 210 (see FIG. 2A , which may or may not include the insulating layer 212 ) and the bonding pad BP.

Referring to FIG. 6C , the gate insulating layer 112 and the passivation layer 116 of the protrusion 110 d each have a plurality of segments. A portion of the segment of the passivation layer 116 is located between two adjacent segments of the gate insulating layer 112 and extends onto the bonding pad BP. In the present embodiment, the segment of the passivation layer 116 extending onto the bonding pad BP contacts the first metal layer 102. In other words, in the present embodiment, two segments of the gate insulating layer 112 and one segment of the passivation layer 116 form a symmetrical protrusion 110 d. In the present embodiment, the upper surface 116S of the passivation layer 116, the sidewall 116W of the passivation layer 116, a portion of the upper surface 112S of the gate insulating layer 112, and the sidewall 112W on one side of the gate insulating layer 112 form a stepped profile of the protrusion 110 d. The stepped protrusion 110 d has the same technical effect as the protrusion 110 c shown in FIG. 6B , and will not be described in detail herein.

Referring to FIG. 6D , the amorphous silicon layer 114 and the passivation layer 116 of the protrusion 110e each have a plurality of sections, and the gate insulating layer 112 is continuous and covers the first metal layer 102 and the bonding pad BP. In the present embodiment, the width of the section of the passivation layer 116 is greater than the width of the section of the amorphous silicon layer 114, and the passivation layer 116 and the gate insulating layer 112 surround the amorphous silicon layer 114. The passivation layer 116 forms a stair-shaped section through the pattern of the amorphous silicon layer 114, so that a stair-shaped protrusion 110e can be formed. In the present embodiment, the upper surface 116S and the sidewall 116W of the passivation layer 116 constitute the stair-shaped profile of the protrusion 110e. The stair-shaped protrusion 110e has the same technical effect as the protrusion 110c shown in FIG. 6B , and will not be described in detail here.

Referring to FIG. 6E , the protrusion 110 f is substantially the same as the protrusion 110 e in FIG. 6D , except that the gate insulating layer 112 of the protrusion 110 f also has a plurality of segments. The vertical projection of the segment of the passivation layer 116 at the bonding pad BP overlaps with the segment of the gate insulating layer 112, and the vertical projection of the segment of the amorphous silicon layer 114 at the bonding pad BP overlaps with the segment of the gate insulating layer 112. In the present embodiment, the width of the gate insulating layer 112 is greater than the widths of the amorphous silicon layer 114 and the passivation layer 116, so that a stepped protrusion 110 f can be formed. In the present embodiment, the upper surface 116S of the passivation layer 116, the sidewall 116W of the passivation layer 116, a portion of the upper surface 112S of the gate insulating layer 112, and the sidewall 112W on one side of the gate insulating layer 112 form a three-layer stepped profile of the protrusion 110 f, but the present invention is not limited thereto. In other embodiments, different processes may be used to form a stepped structure with more layers. For example, a half-tone mask may be used to generate different etching depths to form a protrusion with more layers of stepped structures. The stepped protrusion 110f has the same technical effect as the protrusion 110e shown in FIG. 6D , and will not be described in detail here.

6F , the protrusion 110g is substantially the same as the protrusion 110e in FIG. 6D , and the difference is that the vertical projection of the passivation layer 116 section of the protrusion 110g on the bonding pad BP at least partially overlaps with the vertical projection of the amorphous silicon layer 114 section on the bonding pad BP. For example, the section of the passivation layer 116 on the left side of FIG. 6F completely covers the section of the amorphous silicon layer 114 below it, but the sections of the passivation layer 116 on the right side and in the middle of FIG. 6F only cover a portion of the sections of the amorphous silicon layer 114, so the passivation layer 116 on the right side and in the middle of FIG. 6F and the amorphous silicon layer 114 together form an asymmetric stepped protrusion 110g. The upper surface 116S of the passivation layer 116, the sidewall 116W of the passivation layer 116, a portion of the upper surface 114S of the amorphous silicon layer 114, and the sidewall 114W of one side of the amorphous silicon layer 114 form a three-layer stepped profile of the right and middle protrusions 110g, but the present invention is not limited thereto. The stepped protrusions 110g have the same technical effects as the protrusions 110e shown in FIG. 6D, and are not described in detail here.

In summary, the present invention can increase the contact area between the conductive particles and the flexible substrate by setting a protrusion on the bonding pad of the flexible substrate. In other words, by making the conductive particles contact the protrusion, the deformation of the conductive particles can be increased, thereby improving the bonding stability between the electronic device and the flexible substrate. In addition, in the embodiment where the conductive particles have an insulating layer, the protrusion is also helpful to break through the insulating layer. In this way, in the bonding process, the external force required to achieve effective contact between the electronic component and the flexible substrate can be reduced, thereby avoiding the collapse of the bonding pad of the flexible substrate. In addition, since the interval between the electrical connector and the top of the protrusion is small, even if the interval between the electrical connector and the bonding pad increases with time or environmental changes, it can still ensure that the contact area between the conductive particles and the flexible substrate is sufficient to maintain effective contact and effective electrical connection between the electronic component and the flexible substrate.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Any technician in the field can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be based on the scope defined by the claims.

Claims (19)

1. An electronic device, comprising:

A flexible substrate comprising an active region, a bond pad, and a plurality of protrusions on the bond pad, wherein a space is provided between two adjacent protrusions, and the protrusions comprise a passivation layer;

An anisotropic conductive paste comprising a plurality of conductive particles, wherein the plurality of conductive particles contact the plurality of protrusions, each of the conductive particles having a diameter, the spacing being greater than 50% of the diameter of the conductive particles, and the spacing being less than 3 times the diameter of the conductive particles; and

And the passivation layer protrudes towards the electronic component relative to the bonding pad.

2. The electronic device of claim 1, wherein each of the plurality of protrusions has a width in a range of 1 micron to 2 microns.

3. The electronic device of claim 1, wherein each of the protrusions has a height in a range of 0.1 microns to 1 micron.

4. The electronic device of claim 1, wherein the pitch is in a range of 1.2 microns to 2 microns.

5. The electronic device of claim 1, wherein each of the protrusions has a width, each of the conductive particles has a diameter, the width is greater than 20% of the diameter, and the width is less than 3 times the diameter.

6. The electronic device of claim 1, wherein each of the protrusions has a height, each of the conductive particles has a diameter, the height is greater than 5% of the diameter, and the height is less than 30% of the diameter.

7. The electronic device of claim 1, wherein the plurality of conductive particles have an amount of deformation greater than 15%.

8. The electronic device of claim 1, wherein the passivation layer has a thickness in a range of 0.3 microns to 0.4 microns.

9. The electronic device of claim 1, wherein the passivation layer has a plurality of segments.

10. The electronic device of claim 9, wherein the protrusion comprises a gate insulating layer having a thickness in a range of 0.3 microns to 0.4 microns.

11. The electronic device of claim 10, wherein the gate insulation layer has a plurality of segments.

12. The electronic device of claim 11, wherein vertical projections of the plurality of sections of the gate insulating layer onto the bond pad overlap the plurality of sections of the gate insulating layer, respectively.

13. The electronic device of claim 11, wherein a portion of the passivation layer is located between adjacent two of the plurality of sections of the gate insulating layer and extends onto the bond pad.

14. The electronic device of claim 10, wherein the protrusion further comprises an amorphous silicon layer between the passivation layer and the gate insulating layer, the amorphous silicon layer having a thickness in a range of 0.05 microns to 0.15 microns.

15. The electronic device of claim 14, wherein the passivation layer has a plurality of segments and the amorphous silicon layer has a plurality of segments.

16. The electronic device of claim 15, wherein a perpendicular projection of the plurality of sections of the passivation layer onto the bond pad at least partially overlaps a perpendicular projection of the plurality of sections of the amorphous silicon layer onto the bond pad.

17. The electronic device of claim 15, wherein the gate insulating layer has a plurality of sections, a vertical projection of the plurality of sections of the passivation layer onto the bond pad overlaps the plurality of sections of the gate insulating layer, and a vertical projection of the plurality of sections of the amorphous silicon layer onto the bond pad overlaps the plurality of sections of the gate insulating layer.

18. The electronic device of claim 9, wherein the protrusion further comprises a gate insulating layer and an amorphous silicon layer between the passivation layer and the gate insulating layer, wherein the gate insulating layer has a plurality of segments, the amorphous silicon layer has a plurality of segments.

19. The electronic device of claim 18, wherein a portion of the passivation layer is located between adjacent two of the plurality of sections of the gate insulating layer and extends onto the bond pad.