CN113764361A - Chip packaging structure and chip packaging method - Google Patents
Chip packaging structure and chip packaging method Download PDFInfo
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- CN113764361A CN113764361A CN202110838233.9A CN202110838233A CN113764361A CN 113764361 A CN113764361 A CN 113764361A CN 202110838233 A CN202110838233 A CN 202110838233A CN 113764361 A CN113764361 A CN 113764361A
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Abstract
本公开涉及一种芯片封装结构及芯片封装方法，其中芯片封装结构包括基底框架、芯片、导电支架以及封装材料体；芯片设于基底框架的一侧；导电支架设置在基底框架上，且导电支架与基底框架之间绝缘设置，导电支架的一端与芯片电连接，导电支架的另一端朝向背离基底框架的方向延伸；封装材料体通过注塑的方式形成在基底框架上，以将芯片和导电支架包裹在内，且导电支架的另一端突出于封装材料体，以形成用于连接外围器件的焊接盘，即通过设置导电支架的一端与芯片电连接，另一端背离基底框架延伸并伸出于封装材料体外并形成焊接盘连接外围器件，从而实现三维封装，且可以减小芯片封装结构在水平方向的尺寸，有利于实现芯片封装结构的小型化。
The present disclosure relates to a chip packaging structure and a chip packaging method, wherein the chip packaging structure includes a base frame, a chip, a conductive support and a packaging material body; the chip is arranged on one side of the base frame; the conductive support is arranged on the base frame, and the conductive support It is insulated from the base frame, one end of the conductive support is electrically connected to the chip, and the other end of the conductive support extends in a direction away from the base frame; the packaging material body is formed on the base frame by injection molding to wrap the chip and the conductive support. inside, and the other end of the conductive support protrudes from the packaging material body to form a solder pad for connecting peripheral devices, that is, one end of the conductive support is electrically connected to the chip, and the other end extends away from the base frame and protrudes from the packaging material. A welding pad is formed outside the body to connect peripheral devices, so as to realize three-dimensional packaging, and the size of the chip packaging structure in the horizontal direction can be reduced, which is conducive to realizing the miniaturization of the chip packaging structure.
Description
Technical Field
The present disclosure relates to the field of chip packaging technologies, and in particular, to a chip packaging structure and a chip packaging method.
Background
Chip packaging refers to the assembly of hundreds of thousands or even millions of chips into a compact package that is externally powered and communicates with the chip.
With the increasing complexity of various electronic products, the requirements for the high integration and miniaturization packaging technology of the chip of the electronic product are higher and higher, and the chip packaging structure formed when the chip is packaged by adopting the traditional two-dimensional packaging technology has a larger size in the horizontal direction, so that the requirement for the miniaturization of the chip packaging cannot be met.
Disclosure of Invention
In order to solve the technical problems or at least partially solve the technical problems, the present disclosure provides a chip packaging structure and a chip packaging method.
The present disclosure provides a chip package structure, including a substrate frame, a chip, a conductive support and a package material body;
the chip is arranged on one side of the substrate frame;
the conductive support is arranged on the substrate frame, the conductive support and the substrate frame are arranged in an insulating mode, one end of the conductive support is electrically connected with the chip, and the other end of the conductive support extends towards the direction departing from the substrate frame; the packaging material body is formed on the base frame in an injection molding mode so as to wrap the chip and the conductive support inside, and the other end of the conductive support protrudes out of the packaging material body so as to form a welding pad for connecting a peripheral device.
According to an embodiment of the present disclosure, the conductive bracket includes a first bracket and a second bracket, the first bracket is disposed in the package material body, one end of the first bracket is electrically connected to the chip, the other end of the first bracket is connected to the second bracket, the second bracket is parallel to the substrate frame and partially protrudes out of the package material body, and one side of the second bracket departing from the substrate frame forms the bonding pad.
According to an embodiment of the present disclosure, the first stent comprises a first sub-stent and a second sub-stent; one end of the second sub-bracket is connected with the first sub-bracket, and the other end of the second sub-bracket extends towards the direction departing from the base frame and is connected with the second bracket; the first sub-bracket is parallel to the substrate frame, and the first sub-bracket is arranged on the substrate frame and electrically connected with the chip.
According to an embodiment of the present disclosure, the second sub-mount has a flat plate shape or an arc shape.
According to an embodiment of the present disclosure, the second sub-mount is planar, and the first sub-mount and the second sub-mount are respectively disposed on two sides of the second sub-mount.
According to an embodiment of the present disclosure, an insulating adhesive member is disposed between the first sub-mount and the base frame, so that the conductive mount and the base frame are connected and insulated by the insulating adhesive member.
According to an embodiment of the present disclosure, the conductive brackets include at least two, and the at least two conductive brackets are respectively disposed on two sides of the chip.
According to an embodiment of the present disclosure, the conductive supports include two, and the two conductive supports respectively disposed at two sides of the chip are symmetrically disposed with respect to the chip.
According to an embodiment of the present disclosure, the chip is electrically connected to the one end of the conductive support through a wire.
The present disclosure also provides a chip packaging method for manufacturing the chip packaging structure, including the following steps:
arranging a chip on one side of the substrate frame;
arranging a conductive bracket on one side of the substrate frame, and electrically connecting one end of the conductive bracket with the chip; wherein the conductive bracket and the base frame are arranged in an insulating way, and the other end of the conductive bracket extends towards the direction away from the base frame;
injecting a packaging material on one side of the base frame to form a packaging material body, and enabling the packaging material body to package the chip and the conductive support inside; wherein, one side of the packaging material body far away from the base frame protrudes out of the conductive bracket;
and polishing one side of the packaging material body, which is far away from the base frame, so that the other end of the conductive support protrudes out of the packaging material body and forms a welding pad for connecting a peripheral device.
Compared with the prior art, the technical scheme provided by the embodiment of the disclosure has the following advantages:
the embodiment of the disclosure provides a chip packaging structure and a chip packaging method, wherein the chip packaging structure comprises a substrate frame, a chip, a conductive support and a packaging material body; the chip is arranged on one side of the substrate frame; the conductive support is arranged on the substrate frame, the conductive support and the substrate frame are arranged in an insulating mode, one end of the conductive support is electrically connected with the chip, and the other end of the conductive support extends towards the direction departing from the substrate frame; the packaging material body is formed on the base frame in an injection molding mode so as to wrap the chip and the conductive support, and the other end of the conductive support protrudes out of the packaging material body to form a welding disc for connecting a peripheral device.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure.
In order to more clearly illustrate the embodiments or technical solutions in the prior art of the present disclosure, the drawings used in the description of the embodiments or prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without inventive exercise.
Fig. 1 is a schematic structural diagram of a chip package structure according to an embodiment of the disclosure;
fig. 2 is a schematic flow chart of a chip packaging method according to an embodiment of the disclosure.
Wherein, 1, a base frame; 2. a chip; 3. a conductive support; 31. a first bracket; 311. a first sub-mount; 312. a second sub-mount; 32. a second bracket; 4. a packaging material body; 5. welding a disc; 6. a bottom pad; 7. an insulating adhesive member; 8. and (4) conducting wires.
Detailed Description
In order that the above objects, features and advantages of the present disclosure may be more clearly understood, aspects of the present disclosure will be further described below. It should be noted that the embodiments and features of the embodiments of the present disclosure may be combined with each other without conflict.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure, but the present disclosure may be practiced in other ways than those described herein; it is to be understood that the embodiments disclosed in the specification are only a few embodiments of the present disclosure, and not all embodiments.
As shown in fig. 1, an embodiment of the present disclosure provides a chip package structure, which includes a substrate frame 1, a chip 2, a conductive support 3, and a package material body 4; the chip 2 is disposed on one side of the base frame 1, for example, on the upper surface of the base frame 1 as shown in fig. 1; the conductive support 3 is arranged on the substrate frame 1, the conductive support 3 and the substrate frame 1 are arranged in an insulating mode, one end of the conductive support 3 is electrically connected with the chip 2, and the other end of the conductive support 3 extends towards the direction departing from the substrate frame 1, so that the conductive support 3 is arranged vertically and three-dimensionally on the whole; the packaging material body 4 is formed on the base frame 1 in an injection molding mode to wrap the chip 2 and the conductive support 3 inside, and the other end of the conductive support 3 protrudes out of the packaging material body 4 to form a welding pad 5 for connecting peripheral devices, namely, the chip packaging structure disclosed by the invention is electrically connected with the chip 2 through the conductive support 3 which is arranged in a three-dimensional and vertical mode, and the other end of the conductive support extends away from the base frame 1 and extends out of the packaging material body 4 to form the welding pad 5 for connecting the peripheral devices, so that three-dimensional packaging is realized, the welding pad 5 formed on the packaging material body 4 is used for connecting the peripheral devices, the size of the chip packaging structure in the horizontal direction can be reduced, and the miniaturization of the chip packaging structure is favorably realized.
Specifically, as shown in fig. 1, the substrate frame 1 may be a copper frame or other conductive support, and the bottom of the copper frame may be provided with bottom pads 6.
The chip 2 is disposed on one side of the base frame 1, for example, as shown in the drawing direction of fig. 1, the chip 2 is disposed on the upper surface of the base frame 1, and the outline size of the chip 2 is smaller than that of the base frame 1.
Conductive support 3 sets up on basement frame 1, and the insulating setting between conductive support 3 and the basement frame 1, in order to avoid taking place the electricity between conductive support 3 and the basement frame 1 and be connected, conductive support 3's one end is connected with chip 2 electricity, specifically can realize the electricity through the mode of lead bonding between conductive support 3's bottom and the chip 2 and be connected, conductive support 3's the other end orientation extends away from the direction of basement frame 1, and conductive support 3 is higher than the top surface of chip 2 on the direction of height of chip 2 (be as shown in fig. 1 upper and lower direction), make conductive support 3 wholly be vertical setting in order to make things convenient for follow-up three-dimensional packaging structure that forms, in order to reduce the size of chip packaging structure on the horizontal direction. In addition, peripheral devices connected to the bonding pad 5 are directly connected with the chip 2 in a three-dimensional mode through the vertically arranged conductive support 3, and parasitic impedance and parasitic inductance of related signals or power supplies caused by the connection mode can be reduced to a certain extent.
In addition, the conductive support 3 can be a copper support, the copper support has good heat conduction performance besides good electric conduction performance, and working heat generated by the chip 2 can be transmitted out through the conductive support 3 made of copper, so that the heat dissipation effect of the chip 2 is enhanced.
The packaging material body 4 is formed on the base frame 1 by injection molding to wrap the chip 2 and the conductive bracket 3 inside, and the other end of the conductive bracket 3 protrudes out of the packaging material body 4, that is, the upper end of the conductive bracket 3 protrudes out of the packaging material body 4 to form a bonding pad 5 for connecting peripheral devices, such as capacitors or inductors, so as to save the size of the packaging structure in the horizontal direction, that is, reduce the placement area of the peripheral devices on the base frame 1.
Specifically, when the encapsulant 4 is injection-molded on the base frame 1 and encapsulates the chip 2 and the conductive bracket 3, the encapsulant 4 has a regular shape such as a rectangle as a whole, for example, the upper surface of the encapsulant 4 may be a plane parallel to the base frame 1. The encapsulating material body 4 may be formed by injection molding of an encapsulating material, such as encapsulating plastic.
As shown in fig. 1, the conductive bracket 3 includes a first bracket 31 and a second bracket 32, the first bracket 31 is disposed in the packaging material body 4, one end of the first bracket 31 is electrically connected to the chip 2, the other end of the first bracket 31 is connected to the second bracket 32, the second bracket 32 is parallel to the base frame 1 and partially protrudes out of the packaging material body 4, and a bonding pad 5 is formed on one side of the second bracket 32 departing from the base frame 1, that is, the first bracket 32 is vertically disposed as a whole, and the second bracket 32 is horizontally disposed.
As shown in fig. 1, the first holder 31 includes a first sub-holder 311 and a second sub-holder 312; one end of the second sub-bracket 312 is connected to the first sub-bracket 311, and the other end of the second sub-bracket 312 extends in a direction away from the base frame 1 and is connected to the second bracket 32; the first sub-frame 311 is parallel to the substrate frame 1, the first sub-frame 311 is disposed on the substrate frame 1 and electrically connected to the chip 2, that is, the first sub-frame 311 is disposed horizontally, and the second sub-frame 312 is disposed vertically and extends out of the package material 4. The second sub-mount 312 may have a flat plate shape, an arc shape, or any other shape.
As shown in fig. 1, in the present embodiment, the second sub-mount 312 is planar, and the first sub-mount 311 and the second sub-mount 32 are respectively disposed on two sides of the second sub-mount 312, so as to form a z-shaped mount as shown in fig. 1, and the z-shaped conductive mount 3 can have better stability. Of course, the conductive support 3 may also be formed in a c shape or other shapes, which is not limited in this embodiment.
As shown in fig. 1, an insulating adhesive member 7 is disposed between the first sub-mount 311 and the base frame 1, so that the conductive mount 3 and the base frame 1 are connected and insulated by the insulating adhesive member 7, that is, the first sub-mount 311 of the conductive mount 3 is fixed by adhesion between the insulating adhesive member 7 and the base frame 1, and the insulating adhesive member 7 itself has insulation, so that insulation between the first sub-mount 311 and the conductive mount 3 can be realized. In addition, the placement of the conductive holder 3 on the base frame 1 is performed simultaneously during the adhesion between the conductive holder 3 and the base frame 1 by the insulating adhesive 7. In this embodiment, the insulating adhesive member 7 is specifically an insulating adhesive.
As shown in fig. 1, the number of the conductive supports 3 is at least two, and at least two conductive supports 3 are respectively disposed on two sides of the chip 2, specifically, two conductive supports 3 may be disposed as shown in fig. 1, and the two conductive supports 3 are respectively disposed on two sides of the chip 2; or in other embodiments, the conductive support 3 is provided in plurality, and the plurality of conductive supports 3 may be respectively provided at intervals on both sides of the chip 2 or circumferentially around the outer circumference of the chip 2.
In this embodiment, when two conductive supports 3 are provided, the two conductive supports 3 respectively disposed on the two sides of the chip 2 are symmetrically disposed with respect to the chip 2.
According to an embodiment of the present disclosure, the chip 2 is electrically connected to the bottom of the conductive support 3 through a wire 8, and the wire 8 is, for example, a metal wire or the like.
As shown in fig. 2, the present disclosure further provides a chip packaging method for manufacturing the chip packaging structure, including the following steps:
s101: arranging a chip on one side of the substrate frame;
s102: arranging a conductive bracket on one side of the substrate frame, and electrically connecting one end of the conductive bracket with the chip; the conductive bracket and the base frame are arranged in an insulating mode, and the other end of the conductive bracket extends towards the direction departing from the base frame;
s103: injecting a packaging material on one side of the substrate frame to form a packaging material body, and enabling the packaging material body to package the chip and the conductive support inside; wherein, one side of the packaging material body far away from the substrate frame protrudes out of the conductive bracket;
s104: and polishing one side of the packaging material body, which is far away from the base frame, so that the other end of the conductive support protrudes out of the packaging material body and forms a welding pad for connecting a peripheral device.
Specifically, in step S101, the base frame may be a copper frame, and the chip is a bare chip. In step S102, the conductive bracket may be a copper bracket, and the conductive bracket is vertically and vertically disposed integrally, so that a three-dimensional package structure is formed subsequently. In step S103, for the convenience of injection molding, a side of the encapsulant body away from the base frame is protruded from the conductive bracket, and the encapsulant body is further polished by the polishing process in step S104, so that the upper end of the conductive bracket is exposed and a bonding pad connected to a peripheral device is formed.
It is noted that, in this document, relational terms such as "first" and "second," and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The foregoing are merely exemplary embodiments of the present disclosure, which enable those skilled in the art to understand or practice the present disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the disclosure. Thus, the present disclosure is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. The chip packaging structure is characterized by comprising a substrate frame (1), a chip (2), a conductive support (3) and a packaging material body (4);
the chip (2) is arranged on one side of the substrate frame (1);
the conductive support (3) is arranged on the substrate frame (1), the conductive support (3) and the substrate frame (1) are arranged in an insulating mode, one end of the conductive support (3) is electrically connected with the chip (2), and the other end of the conductive support (3) extends towards the direction departing from the substrate frame (1); the packaging material body (4) is formed on the base frame (1) in an injection molding mode so as to wrap the chip (2) and the conductive support (3) inside, and the other end of the conductive support (3) protrudes out of the packaging material body (4) so as to form a welding pad (5) for connecting a peripheral device.
2. The chip package structure according to claim 1, wherein the conductive support (3) comprises a first support (31) and a second support (32), the first support (31) is disposed in the package body (4) and one end of the first support (31) is electrically connected to the chip (2), the other end of the first support (31) is connected to the second support (32), the second support (32) is parallel to the base frame (1) and partially protrudes out of the package body (4), and a side of the second support (32) facing away from the base frame (1) forms the bonding pad (5).
3. The chip packaging structure according to claim 2, wherein the first support (31) comprises a first sub-support (311) and a second sub-support (312); one end of the second sub-bracket (312) is connected with the first sub-bracket (311), and the other end of the second sub-bracket (312) extends towards the direction departing from the base frame (1) and is connected with the second bracket (32); the first sub-bracket (311) is parallel to the base frame (1), and the first sub-bracket (311) is arranged on the base frame (1) and electrically connected with the chip (2).
4. The chip packaging structure according to claim 3, wherein the second sub-mount (312) has a flat plate shape or an arc shape.
5. The chip package structure according to claim 3, wherein the second sub-frame (312) is planar, and the first sub-frame (311) and the second sub-frame (32) are respectively disposed at two sides of the second sub-frame (312).
6. The chip packaging structure according to claim 3, wherein an insulating adhesive member (7) is disposed between the first sub-mount (311) and the base frame (1), so that the conductive mount (3) and the base frame (1) are connected and insulated by the insulating adhesive member (7).
7. The chip packaging structure according to any one of claims 1 to 6, wherein the number of the conductive supports (3) is at least two, and at least two of the conductive supports (3) are respectively disposed on two sides of the chip (2).
8. The chip packaging structure according to claim 7, wherein the number of the conductive supports (3) is two, and the two conductive supports (3) respectively disposed at two sides of the chip (2) are symmetrically disposed with respect to the chip (2).
9. The chip packaging structure according to any one of claims 1 to 6, wherein the chip (2) is electrically connected to one end of the conductive support (3) by a wire (8).
10. A chip packaging method for manufacturing the chip packaging structure according to any one of claims 1 to 9, comprising the steps of:
arranging a chip on one side of the substrate frame;
arranging a conductive bracket on one side of the substrate frame, and electrically connecting one end of the conductive bracket with the chip; wherein the conductive bracket and the base frame are arranged in an insulating way, and the other end of the conductive bracket extends towards the direction away from the base frame;
injecting a packaging material on one side of the base frame to form a packaging material body, and enabling the packaging material body to package the chip and the conductive support inside; wherein, one side of the packaging material body far away from the base frame protrudes out of the conductive bracket;
and polishing one side of the packaging material body, which is far away from the base frame, so that the other end of the conductive support protrudes out of the packaging material body and forms a welding pad for connecting a peripheral device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110838233.9A CN113764361A (en) | 2021-07-23 | 2021-07-23 | Chip packaging structure and chip packaging method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110838233.9A CN113764361A (en) | 2021-07-23 | 2021-07-23 | Chip packaging structure and chip packaging method |
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| CN113764361A true CN113764361A (en) | 2021-12-07 |
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| CN202110838233.9A Pending CN113764361A (en) | 2021-07-23 | 2021-07-23 | Chip packaging structure and chip packaging method |
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| JP2007234845A (en) * | 2006-03-01 | 2007-09-13 | Nec Corp | Semiconductor device |
| US20080230876A1 (en) * | 2007-03-22 | 2008-09-25 | Stats Chippac, Ltd. | Leadframe Design for QFN Package with Top Terminal Leads |
| US20140210062A1 (en) * | 2013-01-28 | 2014-07-31 | Texas Instruments Incorporated | Leadframe-Based Semiconductor Package Having Terminals on Top and Bottom Surfaces |
| CN104170083A (en) * | 2012-02-24 | 2014-11-26 | 英闻萨斯有限公司 | Method for package-on-package assembly with wire bonds to encapsulation surface |
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2021
- 2021-07-23 CN CN202110838233.9A patent/CN113764361A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007234845A (en) * | 2006-03-01 | 2007-09-13 | Nec Corp | Semiconductor device |
| US20080230876A1 (en) * | 2007-03-22 | 2008-09-25 | Stats Chippac, Ltd. | Leadframe Design for QFN Package with Top Terminal Leads |
| CN104170083A (en) * | 2012-02-24 | 2014-11-26 | 英闻萨斯有限公司 | Method for package-on-package assembly with wire bonds to encapsulation surface |
| US20140210062A1 (en) * | 2013-01-28 | 2014-07-31 | Texas Instruments Incorporated | Leadframe-Based Semiconductor Package Having Terminals on Top and Bottom Surfaces |
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