CN104170083A - Method for package-on-package assembly with wire bonds to encapsulation surface - Google Patents

Abstract

A microelectronic assembly (10) includes a substrate (12) having a first and second opposed surfaces. A microelectronic element (22) overlies the first surface and first electrically conductive elements (28) can be exposed at at least one of the first surface or second surfaces. Some of the first conductive elements (28) are electrically connected to the microelectronic element (22). Wire bonds (32) have bases (34) joined to the conductive elements (28) and end surfaces (38) remote from the substrate and the bases, each wire bond defining an edge surface extending between the base and the end surface. An encapsulation layer (42) can extend from the first surface and fill spaces between the wire bonds, such that the wire bonds can be separated by the encapsulation layer. Unencapsulated portions of the wire bonds (32) are defined by at least portions of the end surfaces (38) of the wire bonds that are uncovered by the encapsulation layer (42).

Description

Method for stacked package assembly with wire bonding to package surface

Cross References to Related Applications

This application is a continuation of U.S. Patent Application No. 13/752,485 filed on January 29, 2013, which is a continuation of U.S. Patent Application No. 13/405,125 filed on February 24, 2012 , a continuation of what is now US Patent No. 8,372,741, issued February 12, 2013, the disclosure of which is incorporated herein by reference.

Background of the invention

Embodiments of the present invention relate to various structures and manners of fabricating microelectronic packages that may be used in package-on-package assemblies, and more particularly to structures that include wire bonds as part of package-on-package connections.

Microelectronic devices, such as semiconductor chips, typically require input and output connections to other electronic components. The input and output contacts of a semiconductor chip or other similar device are typically arranged in a grid-like pattern (commonly referred to as an "area array") that substantially covers the surface of the device, or may be arranged parallel to and adjacent to each of the front surfaces of the device. Elongated rows extending from the edges, or set in the center of the front surface. Typically, a device (such as a chip) must be physically mounted on a substrate (such as a printed circuit board), and the contacts of the device must be electrically connected to conductive features of the circuit board.

Semiconductor chips are typically provided in packages to facilitate handling of the chips during fabrication and mounting of the chips to an external substrate such as a circuit board or other circuit panel. For example, many semiconductor chips are provided in packages suitable for surface mounting. A number of packages of this general type have been proposed for various applications. Generally, such packages include a dielectric element, commonly referred to as a "chip carrier," with terminals formed as plated or etched metal structures on the dielectric. These terminals are typically connected to the contacts of the chip itself by features such as thin traces running along the chip carrier itself and by fine leads or wires extending between the contacts of the chip and the terminals or traces. In a surface mount operation, the package is placed on the circuit board so that each terminal on the package aligns with a corresponding contact pad on the circuit board. Solder or other bonding material is provided between the terminals and the contact pads. The package can be permanently bonded in place by heating the component to melt or "reflow" the solder or activate the bonding material.

Many packages include solder bumps in the form of solder balls (typically about 0.1 mm and 0.8 mm (5 and 30 mils) in diameter) attached to the terminals of the package. A package with an array of solder balls protruding from its bottom surface is commonly referred to as a ball grid array or "BGA" package. Other packages, known as land grid array or "LGA" packages, are secured to the substrate by thin layers or lands of solder. This type of package can be quite compact. Certain packages, commonly referred to as "chip-scale packages," occupy a circuit board area equal to or only slightly larger than the device placed within the package. The advantage of this package is that it reduces the overall size of the assembly and allows the use of short interconnects between the various devices on the substrate, which in turn limits the signal propagation time between the devices, thereby facilitating high-speed operation of the assembly.

Packaged semiconductor chips are typically arranged in a "stacked" arrangement, where one package is placed on, for example, a circuit board, and another package is mounted on top of the first package. These arrangements can allow many different chips to be mounted within a single footprint on a circuit board, and can further facilitate high speed operation by providing short interconnects between packages. Typically, this interconnect distance is only slightly greater than the thickness of the chip itself. In order to achieve interconnection within a stack of chip packages, it is necessary to provide structures for mechanical and electrical connections on both sides of each package (except the topmost package). This step can be performed, for example, by providing contact pads or lands on both sides of the substrate on which the chip is mounted, the pads being connected through the substrate by conductive vias or the like. Use solder balls or the like to bridge the gap between the contact on the top of the lower substrate and the contact on the bottom of the next upper substrate. Solder balls must be higher than the height of the chip to connect the contacts. Examples of stacked chip arrangements and interconnect structures are provided in US Patent Application Publication No. 2010/0232129 ("the 129th publication"), the disclosure of which is incorporated herein by reference in its entirety.

Microcontact elements in the form of elongated posts or pins may be used to connect the microelectronic package to a circuit board and for other connections to the microelectronic package. In some examples, microcontacts are formed by etching a metal structure including one or more metal layers. The etching process limits the size of the microcontacts. Typically, conventional etching processes cannot form microcontacts with large aspect ratios (referred to herein as "aspect ratios"). It is difficult or even impossible to form microcontact arrays with appreciable heights and very small spacing or gaps between adjacent microcontacts. In addition, the configuration of micro-contacts formed by conventional etching processes is limited.

Despite the advantages of the prior art described above, further improvements in the fabrication and testing of microelectronic packages are desired.

Contents of the invention

A microelectronic assembly can include a substrate having opposing first and second surfaces. The microelectronic element can cover the first surface, and the first conductive element can be exposed on at least one of the first surface or the second surface. Some of the first conductive elements can be electrically connected to the microelectronic elements. A wire bond has a base coupled to a conductive element and an end face remote from the substrate and base. Each wire bond may define an edge surface extending between the base and the end surface. The encapsulation layer may extend from the first surface and fill spaces between the wire bonds so that the wire bonds may be separated from each other by the encapsulation layer. The unencapsulated portion of the wire bond may be defined by at least a portion of the end face of the wire bond that is not covered by the encapsulation layer.

Various packaging structures disclosed herein include wire bonds used as vertical connections extending upward from conductive elements (eg, conductive pads on a substrate). Such wire bonds can be used to form package-on-package electrical connections with the microelectronic package overlying the surface of the dielectric package. Additionally, various embodiments of methods for fabricating microelectronic packages or microelectronic assemblies are disclosed herein.

Therefore, according to one aspect of the present invention, a method of manufacturing a microelectronic package may include: a) feeding a metal wire segment having a predetermined length from a capillary of a bonding tool; b) bonding a part of the metal wire using a bonding tool to a conductive element exposed on the first surface of the substrate, thereby forming a base of a wire bond on the conductive element; c) clamping a portion of the wire within the bonding tool; d) between the clamped portion and the base portion Cutting the metal wire at a position between to at least partially define the end surface of the wire bond, the edge surface of the wire bond is defined between the base and the end surface; e) repeating steps (a)-(d) to form a substrate and e) then forming a dielectric encapsulation layer covering the surface of the substrate, wherein the encapsulation layer is formed to at least partially cover the surface of the substrate and portions of the wire bonds such that The unencapsulated portion of the wire bond is defined by the portion of at least one of the end face or edge surface of the wire bond that is not covered by the encapsulation layer.

Therefore, according to an aspect of the present invention, a metal wire segment having a predetermined length may be fed from a capillary of a bonding tool. A bonding tool may be used to bond a portion of the metal wire to the conductive element exposed on the first surface of the substrate. This bonding can form the basis of a wire bond on the conductive element. A portion of the wire may be clamped after forming the bond to the conductive element. The portion of the wire that is clamped may be within the bonding tool. The metal wire may be cut at a location between the clamped portion and the base portion, and cutting the wire may at least partially define an end face of the wire bond. A wire bonded edge surface may be defined between the base and the end surface. The steps described above may be repeated to form multiple wire bonds to multiple conductive elements of the substrate. A dielectric encapsulation layer may then be formed covering the surface of the substrate. The encapsulation layer may be formed to at least partially cover the surface of the substrate and portions of the wire bonds. The unencapsulated portion of the wire bond may be defined by the portion of at least one of an end face or an edge surface of the wire bond not covered by the encapsulation layer.

In one example, the wire may be cut only partially therethrough. The bonding tool can be removed from the surface of the substrate while portions of the wire are still clamped. During this process, the wire can be caused to break at the cut site. End faces can be formed by cutting and breaking.

In one example, the cut may be made completely through the wire segment in a direction generally perpendicular to the edge surface of the wire bond. The end faces of the wire bonds can be formed by cutting.

In one example, at least one microelectronic element can cover the first surface of the substrate. The substrate can have a first region and a second region, and the microelectronic element can be located within, such as overlying, the first region. A conductive element may be located within the second region, such as a conductive element exposed on the first surface within the second region. The conductive element can be electrically connected to at least one microelectronic element. The dielectric encapsulation layer may be formed to cover the first surface of the substrate at least in the second region of the substrate, but may cover at least a portion of the first surface in both the first region and the second region.

In one example, the package can be configured such that a first wire bond of the class of wire bonds is adapted to carry a first signal potential and a second wire bond of the class of wire bonds is adapted to simultaneously carry a signal potential different from that of the first signal potential. A second signal potential of the first signal potential.

In one example, the metal wire segments may be cut using a laser mounted on a bonding tool. In this example, the capillary of the bonding tool may define its face for feeding the wire segments. The laser may be mounted on or with the bonding tool so that the cutting beam may be directed to a position arranged on a line segment between the face of the bonding tool and the base of the wire bond.

In one example, the bonding tool may include a capillary defining its face for feeding the wire segments. The capillary may include an opening in its side wall, and the laser may be mounted on or with the bonding tool so that the cutting beam may pass through the opening to a location on the wire segment disposed within the capillary.

In one example, the laser may be one of a _CO2 , Nd:YAG, or copper vapor laser.

In one example, the wire may be cut using a cutting edge extending within the capillary. In one example, the cutting edge may extend in a direction towards the wall of the capillary opposite the line segment. In one example, the metal wire may be cut through the combined use of a cutting edge as a first cutting edge and a second cutting edge extending within the capillary. The second cutting edge may be arranged opposite the first cutting edge.

In one example, a capillary may define its face for feeding a wire segment. The wire may be cut using a cutting device having opposed first and second cutting edges. A cutting device may be mounted on or with the bonding tool so that the wire may be cut at a location between the face of the bonding tool and the base of the wire bond.

An example of the method may include disposing a template on a substrate. The template can have a plurality of openings covering and exposing at least part of the conductive elements. The openings may define respective edges disposed on the substrate at a first height. The wire segment may be cut by lateral movement of the wire against the edge of the template opening.

According to one aspect of the present invention, a method of fabricating a microelectronic package may include disposing a template on a processing unit including a substrate having a first surface and a second surface remote from the first surface. A microelectronic element can be mounted to the first surface of the substrate. A plurality of conductive elements may be exposed on the first surface. In one example, at least some of the conductive elements can be electrically connected to the microelectronic element. The template can have a plurality of openings covering and exposing at least part of the conductive elements. The openings may define respective edges disposed on the substrate at a first height.

According to this aspect, the method may include forming a wire bond by a process comprising feeding a wire from a capillary of a bonding tool such that a predetermined length extends beyond a face of the capillary and defines a wire segment. A portion of the wire segment may be coupled to one of the plurality of conductive elements to form the basis of a wire bond. At least a portion of the metal wire segment may be sheared from another portion of the wire to which it is connected by lateral movement of the wire against the edge of the stencil opening to separate the wire bond from the remainder of the wire. Shearing of the metal wire may define an end face of the wire bond, the wire bond having an edge surface extending between the base and the end face. The feeding, bonding, and shearing of wires as described above may be repeated multiple times using one or more openings of the template to form multiple wire bonds on multiple conductive elements.

In one example of this method, a dielectric encapsulation layer may be formed on the processing unit, wherein the encapsulation layer is formed to at least partially cover the first surface and portions of the wire bonds. The unencapsulated portion of the wire bond may be defined by the portion of at least one of the end face or edge surface of the wire bond not covered by the encapsulation layer.

In one example of this method, the portion of the wire that extends beyond the face of the capillary and remains after shearing the wire has a length sufficient to form the base of at least one next wire bond.

In one example of this method, the template may define a thickness in a direction extending along the axis of one of the hole types (eg, perpendicular to the surface facing away from the substrate). Some or all of such holes may have a consistent or constant diameter throughout the thickness of the template.

In one example of this method, the template may define a thickness in the direction of the axis of one of such holes or openings (eg, perpendicular to the surface facing away from the substrate). Some or all of such holes or openings in the template may taper from a first width or smaller diameter at an exposed edge within the opening to a first width at another location within the hole or opening closer to the substrate. 2. Larger width or larger diameter.

In one example, the template may include an edge piece having a first thickness in the direction of the thickness of the substrate and extending along one or more edges of the substrate. The first thickness may define a first height. The central portion may comprise such holes or openings and may be bounded by edge pieces. The central portion may have an outer surface facing away from the substrate. The outer surface may be disposed at a first height. The central portion may have a thickness less than the first thickness.

Description of drawings

Figure 1 shows a microelectronic package according to an embodiment of the invention;

Figure 2 shows a top elevation view of the microelectronic package in Figure 1;

Figure 3 shows a microelectronic package according to an alternative embodiment of the present invention;

Figure 4 shows a microelectronic package according to an alternative embodiment of the present invention;

Figure 5 shows a microelectronic package according to an alternative embodiment of the present invention;

6 illustrates a stacked microelectronic assembly including a microelectronic package according to an embodiment of the invention;

Figure 7 shows a microelectronic package according to an alternative embodiment of the present invention;

8A-8E show detailed views of a portion of a microelectronic package according to various embodiments of the invention;

Figure 9 shows a detailed view of a portion of a microelectronic package according to an alternative embodiment of the present invention;

10A-10D illustrate detailed views of a portion of a microelectronic package according to various embodiments of the invention;

11-14 illustrate a microelectronic package at various manufacturing steps according to an embodiment of the invention;

Figure 15 shows a microelectronic package in one manufacturing step according to an alternative embodiment of the present invention;

16A-16C show detailed views of a portion of a microelectronic package at various fabrication steps according to an embodiment of the invention;

17A-17C illustrate detailed views of a portion of a microelectronic package at various manufacturing steps according to an alternative embodiment of the present invention;

Figure 18 shows a top elevation view of a microelectronic package according to an alternative embodiment of the present invention;

Figure 19 shows a top elevation view of a portion of a microelectronic package according to an alternative embodiment of the present invention;

Figure 20 shows a top view of a microelectronic package according to another alternative embodiment of the present invention;

21 shows a front elevational view of the microelectronic package of claim 20;

Figure 22 shows a front elevation view of a microelectronic package according to another alternative embodiment of the present invention;

Figure 23 shows a system according to another embodiment of the present invention;

Figure 24 shows a front elevation view of a microelectronic package according to another alternative embodiment of the present invention;

Figure 25 shows a front elevation view of a microelectronic package according to another alternative embodiment of the present invention;

Figure 26 shows a top view of a microelectronic package according to a variation of the embodiment shown in Figure 25;

Figure 27 shows a front elevation view of a microelectronic package according to another alternative embodiment of the present invention;

Figure 28 shows a top view of a microelectronic package according to a variation of the embodiment shown in Figure 27;

Figure 29 shows a cross-sectional view of a microelectronic package according to another embodiment;

Figure 30 shows a cross-sectional view of a microelectronic package according to another embodiment;

31A-C are cross-sectional views of examples of microelectronic package embodiments according to further embodiments;

32A and 32B illustrate a portion of a machine used to form various wirebond vias at various stages of a method according to another embodiment of the invention;

Figure 33 shows a portion of a machine used to form various wirebond vias in a method according to another embodiment of the invention;

34A-C illustrate various forms of apparatus used in a method of making wire bonds according to an embodiment of the invention.

Detailed ways

Turning now to the drawings, in which like numerals are used to designate like features, FIG. 1 shows a microelectronic assembly 10 in accordance with an embodiment of the present invention. The embodiment shown in FIG. 1 is a microelectronic assembly (eg, a semiconductor chip assembly for a computer or other electronic device) in the form of a packaged microelectronic component.

The microelectronic assembly 10 shown in FIG. 1 includes a substrate 12 having a first surface 14 and a second surface 16 . Substrate 12 is typically in the form of a substantially planar dielectric element. The dielectric element can be sheet-like and can be very thin. In certain embodiments, the dielectric element may include, but is not limited to, one or more layers of organic dielectric materials or composite dielectric materials, such as polyimide, polytetrafluoroethylene ("PTFE"), epoxy, glass epoxy , FR-4, BT resin, thermoplastic material or thermosetting plastic material. First surface 14 and second surface 16 are preferably substantially parallel to each other and spaced apart from each other in a direction perpendicular to surfaces 14 and 16 to define the thickness of substrate 12 . The thickness of the substrate 12 is preferably within the generally acceptable thickness range of the present invention. In one embodiment, the distance between the first surface 14 and the second surface 16 is approximately 25 μm-500 μm. The first surface 14 may be disposed opposite to or remote from the second surface 16 for the purposes described above. This description and any other description of the relative position of elements (ie, the vertical or horizontal position of these elements) used herein is only a schematic illustration corresponding to the position of the elements in the drawings, and is not intended to limit the present invention.

In a preferred embodiment, substrate 12 may be divided into a first region 18 and a second region 20 . The first region 18 is located within the second region 20 and includes and extends outwardly from a central portion of the substrate 12 . The second region 20 substantially surrounds the first region 18 and extends outward from the first region 18 to the outer edge of the substrate 12 . In this embodiment, there are no specific features on the substrate itself that physically divide these two regions, but for the purposes of this discussion with respect to processes applied to, or features contained in, the two regions, the two regions be distinguished.

Microelectronic element 22 may be mounted to first surface 14 within first region 18 of substrate 12 . Microelectronic element 22 may be a semiconductor chip or another comparable device. In the embodiment of FIG. 1 , microelectronic elements 22 are mounted to first surface 14 in what is referred to as a conventional or "face-up" manner. In this embodiment, leads 24 may be used to electrically connect microelectronic element 22 to some of plurality of conductive elements 28 exposed at first surface 14 . Leads 24 may also be coupled to traces (not shown) or other conductive features within substrate 12 that in turn connect to conductive elements 28 .

The conductive elements 28 include respective “contacts” or pads 30 exposed at the first surface 14 of the substrate 12 . As used herein, when a conductive element is described as being "exposed on" the surface of another element having a dielectric structure, this means that the conductive structure can be moved in a direction perpendicular to the surface of the dielectric structure from outside the dielectric structure to the surface of the dielectric structure. Theoretical point of contact. Accordingly, a terminal or other conductive structure exposed on a surface of a dielectric structure may protrude from such surface; may be flush with such surface; or may be recessed relative to such surface and exposed through a hole or recess in the dielectric. Conductive element 28 may be a flat and thin element with pad 30 exposed at first surface 14 of substrate 12 . In one embodiment, conductive elements 28 may be substantially circular and may be interconnected with each other or connected to microelectronic elements 22 by traces (not shown). Conductive element 28 is formed at least in second region 20 of substrate 12 . Additionally, in some embodiments, a conductive element 28 may also be formed within the first region 18 . Such an arrangement is particularly useful when microelectronic element 122 ( FIG. 3 ) is mounted to substrate 112 in a configuration known as a "flip-chip" configuration, where contacts on microelectronic element 122 can be placed under microelectronic element 122 The solder bumps 126 etc. are connected to the conductive elements 128 in the first region 118 . In another configuration as shown in FIG. 22 , microelectronic elements 622 may be mounted face down on substrate 612 and electrically connected via leads 624 extending on the outwardly facing surface of substrate 612 (eg, surface 616 ). to conductive features on the chip. In the illustrated embodiment, leads 625 pass through openings 625 in substrate 612 and may be sealed by overmold 699 .

In one embodiment, conductive element 28 may be formed from a solid metallic material such as copper, gold, nickel or other material acceptable for the application, including various alloys comprising copper, gold, nickel or combinations thereof one or more of.

At least some of the conductive elements 28 may be interconnected to corresponding second conductive elements 40 , such as conductive pads exposed at the second surface 16 of the substrate 12 . This interconnection is accomplished using vias 41 formed in substrate 12 lined or filled with conductive metal, which may be lined or filled with the same material as conductive elements 28 and 40 . Optionally, conductive elements 40 may be further interconnected by traces on substrate 12 .

Microelectronic assembly 10 further includes a plurality of wire bonds coupled to at least some of conductive elements 28 , such as pads 30 of conductive elements 28 . Wire bonds 32 are coupled at their bases 34 to conductive elements 28 and may extend away from each base 34 and away from a free end 36 of substrate 12 . The free end portion 36 of the wire bond 32 is characterized in that it is not electrically connected or otherwise coupled to the microelectronic element 22 or any other conductive feature in the microelectronic assembly 10 which in turn is connected to the microelectronic element 22 . In other words, free end 36 may be electrically connected to conductive features external to assembly 10, directly or indirectly through solder balls or other features as described herein. The fact that the end 36 is held in a predetermined position by, for example, the encapsulation layer 42 or is otherwise coupled or electrically connected to another conductive feature does not mean that the end 36 is not "free" as described herein, So long as any such features are not electrically connected to microelectronic element 22 . Conversely, as described herein, base 34 is not free because it is directly or indirectly electrically connected to microelectronic element 22 . As shown in FIG. 1 , the base 34 is substantially circular in shape and extends outwardly from an edge surface 37 of the wire bond 32 defined between the base 34 and the end 36 . The particular size and shape of base 34 may vary depending on the type of material used to form wire bond 32 , the desired strength of the connection between wire bond 32 and conductive element 28 , or the particular process used to form wire bond 32 . Exemplary methods of making wire bonds 28 are described in U.S. Pat. All are incorporated herein by reference in their entirety. Alternative embodiments are also possible in which wire bonds 32 may additionally or alternatively be coupled to conductive elements 40 exposed on and extending from second surface 16 of substrate 12 .

Wire bonds 32 may be made of conductive materials such as copper, gold, nickel, solder, aluminum, and the like. In addition, wire bonds 32 may be made from a combination of materials, such as a core made of a conductive material such as copper or aluminum, and a coating applied to the core. The coating can be made of a second conductive material (eg aluminum, nickel, etc.). Alternatively, the coating can be made of insulating material such as an insulating jacket. In one embodiment, the wires used to form wire bonds 32 may have a thickness (ie, a dimension across the length of the wire) of about 15 μm-150 μm. In other embodiments, including where wedge bonds are used, wire bonds 32 may have a thickness of up to about 500 μm. In general, wire bonds are formed on conductive elements (eg, conductive elements 28, pads, traces, etc.) using specialized equipment known in the art. The leading end of the wire segment is heated and pressed against a receiving surface to which the wire segment is bonded, typically forming a spherical or ball-like base 34 coupled to the surface of the conductive element 28 . A desired length of the wire segment used to form the wire bond is drawn from the bonding tool, which can then cut the wire bond at the desired length. For example, wedge bonding, which may be used to form aluminum wire bonds, is a process in which a heated portion of the wire is drawn across a receiving surface to form a wedge generally parallel to the surface. The wire bonds formed by wedge bonding can then be bent upwards (if desired) and extended to a desired length or position before cutting. In certain embodiments, the cross-section of the wires used to form the wire bonds may be cylindrical. Additionally, the wire fed from the tool to form the wire bond or wedge-bonded wire bond may have a polygonal cross-section, such as a rectangle or a trapezoid.

The free end 36 of the wire bond 32 has an end face 38 . End face 38 may form at least a portion of a contact in an array formed by each end face 38 of plurality of wire bonds 32 . FIG. 2 shows an exemplary pattern of such a contact array formed by end faces 38 . Such arrays can be formed in an area array configuration, and array variations can be achieved using the structures described herein. Such an array can be used to electrically and mechanically connect microelectronic assembly 10 to another microelectronic structure, such as a printed circuit board ("PCB"), or other packaged microelectronic component (FIG. 6 shows an example). In such a stack arrangement, wire bonds 32 and conductive elements 28 and 40 may carry multiple electronic signals through the arrangement, each electronic signal having a different signal potential to allow different signals to be transmitted by different microelectronic elements in a single stack. deal with. Solder bumps 52 may be used for interconnection of microelectronic components in such a stack, for example by electrically and mechanically attaching end faces 38 to conductive elements 40 .

The microelectronic assembly 10 further includes an encapsulation layer 42 formed of a dielectric material. In the embodiment shown in FIG. 1 , encapsulation layer 42 is formed on portions of first surface 14 of substrate 12 not covered or occupied by microelectronic elements 22 or conductive elements 28 . Similarly, encapsulation layer 42 is formed over portions of conductive elements 28 (including pads 30 of conductive elements 28 ) not covered by wire bonds 32 . Encapsulation layer 42 may also substantially cover microelectronic element 22, wire bonds 32 (including bases 34 of wire bonds 32 and at least a portion of edge surfaces 37 of wire bonds 32). A portion of wire bond 32 may remain uncovered by encapsulation layer 42 , which portion may also be referred to as unencapsulated, thereby enabling the wire bond to electrically connect to features or components located outside encapsulation layer 42 . In one embodiment, end faces 38 of wire bonds 32 remain uncovered by encapsulation layer 42 within major surface 44 of encapsulation layer 42 . Other embodiments are possible in which a portion of the edge surface 37 is not covered by the encapsulation layer 42 , in addition to or instead of having the end face 38 not covered by the encapsulation layer 42 . In other words, encapsulation layer 42 may cover all features of microelectronic assembly 10 on and above first surface 14 except a portion of wire bonds 36 (eg, end surface 38 , edge surface 37 , or a combination of both). In the illustrated embodiment, a surface (eg, major surface 44 ) of encapsulation layer 42 may be spaced from first surface 14 of substrate 12 by a distance sufficient to cover microelectronic element 22 . Accordingly, embodiments of microelectronic assembly 10 in which end faces 38 of wire bonds 32 are flush with surface 44 will include wire bonds 32 above microelectronic element 22 and any underlying solder bumps for flip-chip connection. However, other configurations of encapsulation layer 42 are possible. For example, an encapsulation layer may have multiple surfaces of different heights. In such a configuration, the surface 44 in which the end surface 38 is disposed may be higher or lower than the upwardly facing surface under which the microelectronic element 22 is disposed.

Encapsulation layer 42 serves to protect other components within microelectronic assembly 10 , particularly wire bonds 32 . This ensures a more robust structure so that it is less likely to be damaged during inspection or transport or assembly to other microelectronic structures. The encapsulation layer 42 may be formed of a dielectric material having insulating properties, such as described in US Patent Application Publication No. 2010/0232129, the disclosure of which is incorporated herein by reference in its entirety.

FIG. 3 illustrates an embodiment of a microelectronic assembly 110 that includes a wire bond 132 having an end 136 that is not disposed directly over each base 34 of the wire bond 132 . In other words, considering that the first surface 114 of the substrate 112 extends in two lateral directions to substantially define a plane, the end portion 136 or at least one wire bond 132 extends from the corresponding lateral direction of the base 134 in at least one of these lateral directions. The location moves. As shown in FIG. 3 , wire bond 132 is substantially straight along its longitudinal axis, which is angled 146 relative to first surface 114 of substrate 112 as shown in the embodiment of FIG. 1 . Although the cross-sectional view of FIG. 3 only shows an angle 146 at a first plane perpendicular to the first surface 114, the wire bonds 132 are oriented relative to the first surface 114 in another plane perpendicular to the first plane and the first surface 114. an angle. This angle may be substantially equal to or different from angle 146 . In other words, the end 136 is movable in two transverse directions relative to the base 134, and can be moved by the same or different distances in each transverse direction.

In one embodiment, each wire bond 132 can move in different directions and can move different amounts within the assembly 110 . This arrangement allows assembly 110 to have arrays configured at a different level than surface 144 at the level of substrate 12 . For example, compared to first surface 114 of substrate 112 , the array may cover a smaller total area or have a smaller pitch on surface 144 than at the level of first surface 114 . Further, some of the wire bonds 132 may have ends 136 disposed over the microelectronic elements 122 to accommodate stacked arrangements of different sized packaged microelectronic elements. In another example as shown in FIG. 19 , the wire bonds 132 may be configured such that the end surface 138A of one wire bond 132A is disposed substantially above the base 134B of the other wire bond 132B, and the end surface 138B of the wire bond 132B is disposed on the base 134B of another wire bond 132B. other places. This arrangement may be referred to as changing the relative position of the contact end faces 138 within the contact array relative to the position of the corresponding contact array on the second surface 116 . In such an array, the relative positions of the contact end faces can be changed or varied as desired depending on the application or other requirements of the microelectronic assembly.

In a further example as shown in FIG. 30 , the wire bonds 132 may be arranged such that the bases 134 are arranged in a first pattern with a pitch. The wire bonds 132 may be configured in a pattern such that an unencapsulated portion 139 (including the end face 138 ) may be arranged in a pattern at the location of the major surface 144 of the encapsulation layer 142 , the unencapsulated portion 139 having a larger diameter than the wire bond attached to the conductive element 128. The minimum spacing between each adjacent base 134 of the minimum spacing. Accordingly, the minimum spacing between adjacent wire bonds on package surface 146 may be greater than the corresponding minimum spacing between conductive elements 128 of the substrate to which the wire bonds are attached.

To accomplish this, the wire bonds may be angled (as shown in FIG. 30), or may be curved as shown in FIG. 4, so that the end face 138 moves in one or more lateral directions from the base 134 as described above. As further shown in FIG. 30, the conductive elements 128 and end faces 138 may be arranged in rows or columns, and the lateral displacement of the end faces 138 in one row may be greater than in another row. To achieve this, the wire bonds 132 may be at different angles 146A, 146B relative to the surface 116 of the substrate 112 (for example).

FIG. 4 shows a further embodiment of a microelectronic subassembly 210 that includes a wire bond 232 having an end 236 in a shifted lateral position relative to a base 234 . In the embodiment of FIG. 4 , the wire bonds 132 enable lateral movement by including their curved portions 248 . The bent portion 248 may be formed in an additional step of the wire bond formation process, and may occur, for example, when the wire portion is stretched to a desired length. This step can be performed with available wire bonding equipment, including the use of a single machine.

The curved portion 248 may take a variety of shapes to achieve the desired location of the end 236 of the wire bond 232 as desired. For example, the curved portion 248 may be formed in various shapes of an S-shaped curve (such as an S-shaped curve as shown in FIG. 4 ) or a smoother form (as shown in FIG. 5 ). Furthermore, the curved portion 248 may be disposed closer to the base 234 than to the end 236, and vice versa. The curved portion 248 may be helical or annular, or a combination including curves in multiple directions or of different shapes or properties.

FIG. 5 shows a further exemplary embodiment of a microelectronic package 310 that includes a combination of wire bonds 332 having various shapes that result in various relative lateral displacements between base 334 and end 336 . Some of the wire bonds 332A are substantially straight with ends 336A disposed over the respective bases 334A of the wire bonds, while other wire bonds 332B include a slight curvature resulting in a slight relative lateral displacement between the ends 336B and bases 334B. Section 348B. Further, some of the wire bonds 332C include a curved portion 348C having a streamlined shape that causes the end 336C to move laterally from the associated base 334C by a distance that is greater than the distance that the end 334B moves. FIG. 5 also shows an exemplary pair of such wirebonds 332Ci and 332Cii having bases 334Ci and 334Cii arranged in the same row in the array at the level of the substrate and arranged on the corresponding substrate. Different row ends 336Ci and 336Cii of the array at the horizontal plane.

A further variant of the wire bond 332D is configured not to be covered by the encapsulation layer 342 on its side surface 47 . In this embodiment, free end portion 336D is uncovered, however, a portion of edge surface 337D may additionally or alternatively be uncovered by encapsulation layer 342 . This configuration can be used to ground the microelectronic assembly 10 through electrical connections to appropriate features, or for mechanical or electrical connections to other features disposed laterally on the microelectronic assembly 310 . Furthermore, FIG. 5 shows regions of encapsulation layer 342 that have been etched, molded, or otherwise formed to define a concave surface 345 disposed closer to substrate 12 than major surface 342 . One or more wire bonds (eg, wire bond 332A) may be uncovered in an area along recessed surface 345 . In the exemplary embodiment shown in FIG. 5 , portions of end surface 338A and edge surface 337A are not covered by encapsulation layer 342 . This configuration may provide a connection to another conductive element, such as through a solder ball or the like, by allowing solder to absorb on edge surface 337A and couple to edge surface 337A and end surface 338 . Other configurations in which a portion of the wire bond may not be covered by the encapsulation layer 342 along the recessed surface 345 are possible, including configurations in which the end faces are generally flush with the recessed surface 345 or as shown here with respect to the encapsulation layer 342. Any other configuration for any other surface. Similarly, other configurations in which wire bonds 332D are not covered by encapsulation layer 342 along a portion of side surface 347 may be similar to the variations described elsewhere herein with respect to the major surface of the encapsulation layer.

FIG. 5 further illustrates microelectronic assembly 310 having two microelectronic elements 322 and 350 in one exemplary arrangement, where microelectronic element 350 is stacked face-up on microelectronic element 322 . In this arrangement, leads 324 are used to electrically connect microelectronic element 322 to conductive features on substrate 312 . Various leads are used to electrically connect microelectronic element 350 to various other features of microelectronic element 310 . For example, leads 380 electrically connect microelectronic element 350 to conductive features of substrate 312 , and leads 382 electrically connect microelectronic element 350 to microelectronic element 322 . Additionally, wire bonds 384 similar in structure to individual wire bonds 332 are used to form contact surfaces 386 on surface 344 of encapsulation layer 342 electrically connected to microelectronic element 350 . This can be used to electrically connect features of another microelectronic assembly to microelectronic element 350 from above encapsulation layer 342 . When only the microelectronic element is included without the second microelectronic element 350 attached thereto, leads connected to the microelectronic element 322 may also be included. An opening (not shown) is formed in encapsulation layer 342 and extends from surface 344 of encapsulation layer 342 to a point along, for example, lead 380, thereby providing access to lead 380 for electrical connection through components located outside surface 344. to lead 380. Similar openings may be formed on any of the other leads or wire bonds 332 , for example, on wire bond 332C at a point remote from end 336C of wire bond 332 . In this embodiment, end 336C may be disposed below surface 344 with the opening providing the only pathway for electrical connection thereto.

FIG. 6 shows a stack package of microelectronic assemblies 410 and 488 . In this arrangement, solder bump 452 electrically and mechanically connects end face 438 of component 410 to conductive element 440 of component 488 . The stacked package may include additional components and may eventually be attached to contacts 492 on a PCB 490 or the like for use in an electronic device. In such a stack arrangement, wire bonds 432 and conductive elements 430 may carry multiple electronic signals therethrough, each signal having a different signal potential to allow different signals to be transmitted by different microelectronic elements (such as microelectronics) in a single stack. electronic components 422 or microelectronic components 489) processing.

In the exemplary configuration of FIG. 6 , wire bonds 432 may be configured with curved portions 448 such that ends 436 of at least some of wire bonds 432 extend into a region overlying major surface 424 of microelectronic element 422 . This area may be defined by the periphery of the microelectronic element 422 and extend upwardly from the periphery. 18 shows an example of such a configuration from a perspective facing the first surface 414 of the substrate 412, where wire bonds 432 cover the major surface of the backside of the microelectronic element 422, which is inverted at its front 425. bonded to the substrate 412. In another configuration ( FIG. 5 ), microelectronic element 422 may be mounted face-up to substrate 312 with front surface 325 facing away from substrate 312 and at least one wire bond 336 covering the front surface of microelectronic element 322 . In one embodiment, such wire bonds 336 are not electrically connected to the microelectronic element 322 . Wire bonds 336 bonded to substrate 312 may also cover the front or back side of microelectronic element 350 . The embodiment of the microelectronic assembly 410 shown in FIG. 18 has the conductive elements 428 arranged in a pattern forming a first array, wherein the conductive elements 428 are arranged to surround the rows and columns of the microelectronic elements 422, and there may be a difference between each conductive element 428. predetermined distance between. Wire bonds 432 are coupled to conductive elements 428 such that individual bases 434 of wire bonds 432 follow the pattern of the first array of conductive elements 428 disposed. However, the wire bonds 432 are configured such that respective ends 436 of the wire bonds 432 may be arranged in a different pattern according to the second array configuration. In the illustrated embodiment, the pitch of the second array may be different, and in some cases smaller, than the pitch of the first array. However, other embodiments are possible where the pitch of the second array is greater than the pitch of the first array, or where the conductive elements 428 are not arranged in a predetermined array and the ends 436 of the wire bonds 432 are arranged in a predetermined array. Furthermore, conductive elements 428 may be arranged in array sets throughout substrate 412 and wire bonds 432 are arranged with ends 436 in different array sets or in a single array.

FIG. 6 further illustrates insulating layer 421 extending along the surface of microelectronic element 422 . Before forming the wire bonds, the insulating layer 421 may be formed of a dielectric or other electrically insulating material. The insulating layer 421 can protect the microelectronic element from contacting any of the wire bonds 423 extending thereover. In particular, the insulating layer 421 can prevent short circuits between wire bonds and short circuits between the wire bonds and the microelectronic element 422 . In this way, insulating layer 421 can help avoid malfunction or possible damage due to false electrical contact between wire bonds 432 and microelectronic element 422 .

The wire bonding configurations shown in FIGS. 6 and 18 may allow microelectronic assembly 410 to be connected to another microelectronic assembly, such as microelectronic assembly 488, where, for example, the relative dimensions of microelectronic assembly 488 and microelectronic assembly 422 do not permit. certain circumstances. In the embodiment of FIG. 6 , microelectronic assembly 488 is dimensioned such that some contact pads 440 are located in an array in an area smaller than the area of front surface 424 or rear surface 426 of microelectronic element 422 . In microelectronic assemblies having generally vertical conductive features, such as posts, instead of wire bonds 432, a direct connection between conductive elements 428 and pads 440 is not feasible. However, as shown in FIG. 6 , wire bonds 432 with appropriately configured bends 448 may have ends 436 in place to make the necessary electrical connection between microelectronic assembly 410 and microelectronic assembly 488 . This arrangement can be used to make a package-on-package, where the microelectronic assembly 418 is, for example, a DRAM chip or the like with a predetermined array of pads, and where the microelectronic element 422 is a logic chip for controlling the DRAM chip. This allows a single type of DRAM chip to be used with multiple different logic chips of different sizes (including those that are larger than the DRAM chip), because the wire bonds 432 can have the necessary locations to make the desired connection with the DRAM chip. The end 436 of. In an alternative embodiment, microelectronic package 410 may be mounted on printed circuit board 490 in another configuration wherein unpackaged surface 436 of wire bond 432 is electrically connected to pad 492 of circuit board 490 . Additionally, in this embodiment, another microelectronic package, such as a variation of package 488 , may be mounted on package 410 via solder balls 452 coupled to pads 440 .

Other arrangements of microelectronic packages having multiple microelectronic elements are shown in Figures 31A-C. These arrangements may be used in conjunction with arrangements of wire bonding, such as in the package-on-package arrangements shown in Figures 5 and 6, as discussed further below. In particular, FIG. 31A shows an arrangement in which a lower microelectronic element 1622 is flip-chip bonded to a conductive element 1628 on a surface 1614 of a substrate 1612 . The second microelectronic element 1650 is mounted face-up on top of the first microelectronic element 1622 and is connected to other conductive elements 1628 by wire bonds 1688 . FIG. 31B shows an arrangement in which first microelectronic element 1722 is mounted face-up on surface 1714 and is connected to conductive element 1728 by wire bonds 1788 . The second microelectronic element 1750 is flip-chip mounted on top of the first microelectronic element 1722 with a set of contacts 1726 of the second microelectronic element 1750 facing and coupled to the front surface of the first microelectronic element 1722 corresponding contacts. The contacts on the first microelectronic element 1722 can in turn be connected by the circuit pattern of the first microelectronic element 1722 and by some wire bonds 1788 to the conductive elements 1728 on the substrate 1712 .

FIG. 31C shows an arrangement in which a first microelectronic element 1822 and a second microelectronic element 1850 are mounted side-by-side on a surface 1814 of a substrate 1812 . One or both of the microelectronic elements (and further microelectronic elements) may be mounted in a face-up or flip-chip configuration as described above. In addition, any of the microelectronic components employed in such an arrangement may be interconnected by circuit patterns on one or both such microelectronic components, or on the substrate, or both, the circuit patterns being electrically connected to the microelectronic components. The electronic components are electrically connected to individual conductive elements 1828 .

FIG. 7 shows a microelectronic assembly 10 of the type shown in FIG. 1 with a redistribution layer 54 extending along the surface 44 of the encapsulation layer 42 . As shown in FIG. 7, trace 58 is electrically connected to inner contact pad 61, which is electrically connected to end face 38 of wire bond 32 and extends through substrate 56 of redistribution layer 54 to the exposed Contact pads 60 on surface 62 of substrate 56 . Another microelectronic component may then be connected to the contact pads 60 by solder bumps or the like. A structure similar to redistribution layer 54 , referred to as a fan-out layer, may extend along second surface 16 of substrate 12 . The fan-out layer may allow microelectronic assembly 10 to be connected to an array of different configurations than the array of conductive elements 40 would otherwise allow.

8A-8E illustrate various configurations that may be implemented in structures at or near ends 36 of wire bonds 32 in structures similar to those of FIGS. 1-7. FIG. 8A shows a structure in which a cavity 64 is formed in a portion of the encapsulation layer 42 such that the ends 36 of the wire bonds 32 protrude above the subsurface 43 of the encapsulation layer at the cavity 64 . In the illustrated embodiment, end face 38 is disposed below major surface 44 of encapsulation layer 42 , and cavity 64 is configured to expose end face 38 at surface 44 to allow electronic structures to interface with end face 38 . Other embodiments are possible in which the end face 38 is generally flush with the surface 44 or spaced apart on the surface 44 . Further, cavity 64 may be configured such that a portion of end face 37 near end 36 of wire bond 32 may not be covered by encapsulation layer 42 within cavity 64 . This may allow connections, such as solder connections, to be made from the outside of the assembly 10 to the wire bonds 32 from the uncovered portions of the end faces 37 near the end faces 38 and 36 . This connection is shown in FIG. 8B and may provide a more robust connection to the second substrate 94 using solder bumps 52 . In one embodiment, cavity 64 may have a depth below surface 44 of about 10 μm-50 μm, and may have a width of about 100 μm-300 μm. FIG. 8B shows a cavity having a structure similar to that shown in FIG. 8A but with tapered sidewalls 65 . Further, FIG. 8B shows a second microelectronic assembly 94 electrically and mechanically connected to a wire bond via solder bumps 52 at contact pads 96 at the surface exposed to its substrate 98. 32.

Cavity 64 may be formed by removing a portion of encapsulation layer 42 in the intended area of cavity 64 . This can be done by known processes including laser etching, wet etching, grinding and the like. Alternatively, in an embodiment where encapsulation layer 42 may be formed by injection molding, cavity 64 may be formed by including corresponding features in the mold. This process is discussed in US Patent Application Publication No. 2010/0232129, which is incorporated herein by reference in its entirety. The tapered shape of cavity 64 shown in FIG. 8B may be a result of the special etch process used in its formation.

8C and 8E illustrate an end structure including a generally circular end portion 70 on a wire bond 32 . The circular end portion 70 is configured to have a cross-section that is wider than the cross-section of the portion of the wire bond 32 between the base 34 and the end 36 . Further, the rounded end portion 70 includes an edge surface 71 extending outwardly from the edge surface 37 at its transition with the edge surface 37 of the wire bond 32 . The incorporation of the rounded edge portion 70 can be used to secure the wire bonds 32 within the encapsulation layer 42 by providing an anchoring feature, wherein the change in direction of the surface 71 gives the encapsulation layer 42 a position to surround the end portion 70 on three sides . This may help prevent wire bonds 32 from separating from conductive elements 28 on substrate 12, resulting in failure of the electrical connection. Additionally, rounded end portion 70 may provide increased surface area within surface 44 where electrical connections may be made that is not covered by encapsulation layer 42 . Rounded end portion 70 may extend over surface 44 as shown in FIG. 8E . Optionally, as shown in FIG. 8C , rounded end portion 70 may be further milled or otherwise flattened to provide a surface that is generally flush with surface 44 and may have an area greater than the cross-section of wire bond 32 .

Rounded end portion 70 may be formed by applying localized heat in the form of a flame or spark at the end of the wire used to make wire bond 32 . Known wire bonding machines can be adapted to perform this step, which can be performed immediately after cutting the wire. During this process, the heat melts the wire at its ends. Parts of a liquid metal can become rounded locally by its surface tension and remain round as the metal cools.

FIG. 8D shows a configuration of microelectronic assembly 10 in which ends 36 of wire bonds 32 include surfaces 38 spaced above major surface 44 of encapsulation layer 42 . This configuration may exhibit benefits similar to those described above with respect to cavity 64, specifically providing a more robust connection through the use of solder bump 68 along unencapsulated layer 42 on surface 44 of edge surface 37. The covered part is adsorbed. In one embodiment, end faces 38 may be spaced apart on surface 42 by a distance of about 10 μm-50 μm. Furthermore, in the embodiment shown in FIG. 8D and other embodiments in which a portion of edge surface 37 is on the surface of encapsulation layer 42 and not covered by encapsulation layer 42 , the ends may include a protective layer formed thereon. Such protective layers may include oxide protective layers, including oxide protective layers made of gold, oxide paint, or OSP.

FIG. 9 shows an embodiment of a microelectronic assembly 10 having bumps 72 formed on end faces 38 of wire bonds 32 . Bumps 72 may be formed after fabrication of microelectronic assembly 10 by applying another modified wire bond on top of end face 44 and optionally extending along a portion of surface 44 . The altered wire bond is cut or otherwise sheared in the vicinity of its base without stretching the length of the wire. Bumps 72 containing certain metals can be applied directly to tip 38 without first applying a bonding layer such as a UBM, thus providing a means of forming conductive interconnections to bond pads that are not directly wetted by solder. This is extremely useful when the wire bonds 32 are made of non-wettable metals. In general, bumps consisting essentially of one or more of copper, nickel, silver, platinum, and gold may be applied in this manner. FIG. 9 shows solder bumps 68 formed on bumps 72 for electrical or mechanical connection to additional microelectronic components.

10A-10D illustrate configurations of ends 36 of wire bonds 32 that include bent or bent shapes. In each embodiment, the ends 36 of the wire bonds 32 are bent so that a portion 74 thereof extends generally parallel to the surface 44 of the encapsulation layer 42 such that at least a portion of the edge surface 76 is not covered by, for example, the major surface 44 . Portions of edge surface 37 may extend upwardly beyond surface 44 or may be milled or otherwise flattened so as to extend generally flush with surface 44 . The embodiment of FIG. 10A includes an abrupt bend in wire bond 32 at portion 74 of end 36 that is parallel to surface 44 and terminates in end face 38 that is generally perpendicular to surface 44 . FIG. 10B shows end 36 having a more gradual curvature near portion 74 of end 36 parallel to surface 44 than shown in FIG. 10A . Other configurations are also possible, including wherein a portion of a wire bond according to FIG. 3, FIG. 4 or FIG. The configuration of one end covered by the encapsulation layer 42 . In addition, the embodiment shown in FIG. 10B includes a hooked portion 75 on its end that disposes the end face 38 below the inner surface 44 of the encapsulation layer 42 . This may provide a more robust structure for the end portion 36 that is less likely to move from within the encapsulation layer 42 . FIGS. 10C and 10D show structures similar to those shown in FIGS. 10A and 10B , respectively, but uncovered by encapsulation layer 42 at a location along surface 44 through cavity 64 formed in encapsulation layer 42 . These cavities may be similar in structure to that described in Figures 8A and 8B. Inclusion of the end 36 (including a portion 74 thereof extending parallel to the surface 44 ) may provide increased surface area for connection thereto due to the elongated uncovered edge surface 75 . The length of this portion 74 may be greater than the width of the cross-section of the wire used to form the wire bond 32 .

In a further example as shown in FIG. 29 , multiple wire bonds 1432 may be coupled to a single conductive element 1428 . Such a set of wire bonds 1432 may be used to make additional connection points on encapsulation layer 1442 to electrically connect to conductive elements 1428 . The exposed portions 1439 of the commonly coupled wire bonds 1432 may be grouped on the surface 1444 of the encapsulation layer 1442 in an area of a size, for example, approximately the size of the conductive element 1428 itself, or another area close to the predetermined size of the bond pad, to form Wire bond the external connections of the 1432 group. As shown, such wire bonds 1432 may be ball bonds or edge bonds on conductive elements 1428 as described above. In forming multiple wire bonds to conductive elements on a substrate, the various techniques described herein for severing metal wires during the wire bonding process (eg, by a laser or other cutting device) may be employed.

11-15 illustrate microelectronic assembly 10 at various steps in a method of fabricating microelectronic assembly 10 . Figure 11 shows the microelectronic assembly 10' As shown in FIG. 11 , the microelectronic elements 22 are mounted on the substrate 12 in a flip-chip arrangement, eg, with contacts on the microelectronic elements 22 facing and coupled to corresponding contacts on the opposite surface 14 of the substrate. For example, the connection between the contacts of the microelectronic element and the contacts of the substrate can be made by a conductive material such as block 26 (such as conductive paste, conductive matrix material, solder bump), and the contact can be used such as Pads, posts (such as micropillars, bumps, etc.), and any other suitable configuration. As used herein, "flip-chip bonding" means an arrangement of face-to-face electrical bonding between corresponding contacts of a microelectronic element and a substrate, or between a microelectronic element and another microelectronic element.

Alternatively, face-up wire bonding of the contacts of the microelectronic element to the substrate such as shown in the example of FIG. 1 may be used instead. In the embodiment of this method step shown in FIG. 11 , dielectric fill layer 66 is disposed between microelectronic element 22 and substrate 12 .

12 shows a microelectronic assembly 10″ having wire bonds 32 applied to pads 30 of conductive elements 28 exposed on first surface 14 of substrate 12. As discussed, wire bonds 32 may Apply by heating the end of the wire segment to soften the end so that when pressed to the conductive element 28, a deposited bond is formed to the conductive element 28, forming the base 34. The wire is then pulled from the conductive element 28 , if desired, before being severed or otherwise severed to form the ends 36 and end faces 38 of the wire bonds 32. Alternatively, the wire bonds 32 may be formed from, for example, aluminum wire by wedge bonding. The bond is formed by heating the portion of the wire adjacent the end of the wire bond and pulling that portion along the conductive element 28 by applying pressure thereon. This process is further described in U.S. Patent No. 7,391,121, the disclosure of which All are incorporated herein by reference.

In FIG. 13 , encapsulation layer 42 is affixed to microelectronic assembly 10 ″ by applying on first surface 14 of the substrate, extending upwardly from first surface 14 and along edge surface 37 of wire bonds 32 . Encapsulation layer 42 also covers fill layer 66. As shown in Figure 12, encapsulation layer 42 is formed by depositing a resin over microelectronic assembly 10". This is done by placing the assembly 10'' in a suitably configured mold having a cavity of the desired shape in the encapsulation layer 42 that accommodates the assembly 10'. Such a mold and this method of forming the encapsulation layer can be found in U.S. Patent Application Publication No. 2010/0232129 is shown and described, the disclosure of which is incorporated herein by reference in its entirety. Optionally, encapsulation layer 42 is prefabricated into a desired shape using at least partially flexible material. In this configuration , the flexible nature of the dielectric material allows the encapsulation layer 42 to be pressed into place over the wire bonds 32 and the microelectronic element 22. In this step, the wire bonds 32 pass through the flexible material to form various holes in it, and the encapsulation layer 42 The edge surface 37 is contacted through each hole. In addition, the microelectronic element 22 can deform the flexible material so that the microelectronic element 22 can be accommodated. The flexible dielectric material can be compressed to expose the end surface 38 on the outer surface 44. Optionally, any Additional flexible dielectric material may be removed from the encapsulation layer to form surface 44 on which end faces 38 of wire bonds 32 are uncovered, or to form cavities 64 to uncover end faces 38 at locations within surface 63 .

In the embodiment shown in FIG. 13 , the encapsulation layer is formed such that its surface 44 is initially spaced above the end faces 38 of the wire bonds 32 . To expose end face 38, the portion of encapsulation layer 42 over end face 38 may be removed, exposing a new surface 44' that is generally flush with end face 42 (as shown in FIG. 14). Optionally, a cavity 64 (such as that shown in FIGS. 8A and 8B ) is formed in which the end face 38 is uncovered by the encapsulation layer 42 . Further optionally, the encapsulation layer 42 may be formed such that the surface 44 is substantially flush with the end surface 48 , or the surface 44 is disposed below the end surface 48 (as shown in FIG. 8D ). If necessary, portions of encapsulation layer 42 may be removed by milling, dry etching, laser etching, wet etching, grinding, or the like. If desired, portions of ends 36 of wire bonds 32 may also be removed in the same or additional steps to obtain a generally planar end surface 38 that is generally flush with surface 44 . If desired, cavities 64 are formed after this step, or bumps as shown in FIG. 10 can also be applied. The resulting microelectronic assembly 10 can be attached to a PCB or otherwise incorporated into another assembly, such as the package-on-package shown in FIG. 6 .

In an alternative embodiment shown in FIG. 15, wire bonds 32 are initially formed in pairs as portions 32' of wire loop 86. In this embodiment, ring 86 is made in the wire bonded fashion described above. The line segment is stretched upwards, then bent and stretched in the direction of the first surface 14 of the substrate 13 in the direction with at least one part thereof to a position substantially covering the adjacent conductive element 28 . The wire is then drawn generally down to a location in the vicinity of adjacent conductive elements 28 before cutting or otherwise severing. The wire is then heated and connected to adjacent conductive elements 28 by deposition bonding or the like to form loop 86 . Encapsulation layer 42 is then formed to substantially cover ring 86 . A portion of encapsulation layer 42 is then removed by milling, etching, etc., by a process that also removes a portion of ring 86 so that the ring is severed and split into two parts 32' thereof, thereby forming Wire bond 32 of end face 38 not covered by encapsulation layer 42 at a location on surface 44 on encapsulation layer 42 . Subsequent finishing steps may be applied to assembly 10, as described above.

16A-16C illustrate steps in an alternative embodiment for making cavity 64 around end 36 of wire bond 32 (as described above). Figure 16A shows a wire bond 32 of the general type described with respect to Figures 1-6. The wire bond 32 has a block of sacrificial material 78 applied on the end 36 thereof. The shape of the mass of sacrificial material 78 is generally spherical (this may be caused by the surface tension of the material during its formation), or other desired shape as will be understood by those skilled in the art. The mass of sacrificial material 78 may be formed by dipping the ends 36 of the wire bonds 32 in solder paste to coat the ends thereof. The viscosity of the solder paste can be adjusted prior to dipping to control the amount of solder mass that attaches to tip 36 due to adsorption and surface tension. Correspondingly, this may affect the size of the block 78 applied on the end 36 . Alternatively, mass 78 may be formed by depositing a soluble material on end 36 of wire bond 32 . Other possible bumps 78 could be individual solder balls, or other bumps on the ends, or by other means using other materials used in the microelectronic component fabrication process that are later removable, such as copper or gold flash plating.

In FIG. 16B , a dielectric layer 42 is shown having been added to the assembly 10 , including up the edge surfaces 37 of the wire bonds 32 . The dielectric layer also extends along a portion of the surface of the block of sacrificial material 78 so that it is thereby spaced from the ends 36 of the wire bonds 32 . Subsequently, the block 78 of sacrificial material is removed, such as by washing or rinsing in a solvent, melting, chemical etching, or other techniques, thereby leaving a generally negative-shaped cavity within the dielectric layer 42 prior to removal of the block 78 64 , and expose a portion of edge surface 37 near end 36 of wire bond 32 .

Alternatively, a block of sacrificial material 78 may be formed to coat substantially all of the wire bonds 32 by extending along the edge surfaces 37 of the wire bonds 32 . This arrangement is shown in Figure 17A. The coating may be applied over the wire bonds 32 after the assembly 10 is formed (as described above), or may be applied as a coating on the wires making the wire bonds 32 . Basically, this will be in the form of a coated wire or a two-part wire, for example with a copper core and a solder coating. 17B shows the dielectric layer 42 applied to the wire bond 32 and the sacrificial block 78 to extend along the edge surface 79 of the sacrificial block 78, thereby connecting the dielectric layer 42 to the wire bond 32 substantially along the length of the wire bond. Spaced out.

FIG. 17C shows the structure resulting from the removal of a portion of the sacrificial material block 78 forming cavity 64 around end 36 and exposing a portion of edge surface 37 . In this embodiment, most or at least a portion of the mass of sacrificial material 78 may remain at a location between the dielectric layer 42 and the wire bonds 32 . FIG. 17C further illustrates solder bumps 52 electrically and mechanically connecting wire bonds 32 to contact pads 40A of another microelectronic structure 10A.

After forming a wire segment and bonding it to a conductive element to form a wire bond (especially the ball bond described above), the wire bond (such as 32 in FIG. The remainder of the line is separated. This can be done at any location away from the base 34 of the wire bonds 32 , and preferably at a distance away from the base 34 that is at least sufficient to define the desired height of the wire bonds 32 . The separation described above may be performed by a mechanism disposed within the capillary 804 or disposed outside the capillary 804 between the face 806 and the base 34 of the wire bond 32 . In one approach, the line segments 800 may be separated by effectively burning with a spark or flame across the line 800 at the desired separation point. In order to obtain greater precision in the wire bond height, the wire segment 800 may be cut in different forms. As described herein, cutting may be used to describe partial cutting, and the wire may be frayed or completely severed at the desired location to completely separate the wire bond 32 from the remaining wire segment 800 .

In the example shown in FIG. 32 , dicing blade 805 may be integrated into a bond head assembly, such as capillary 804 . As shown, an opening 807 can be included in the sidewall 820 of the capillary 804 through which the cutting blade 805 can extend. The cutting blade 805 can be moved in and out of the interior of the capillary 804 to alternately allow the wire 800 to pass freely or engage the wire 800 . Correspondingly, wire 800 may be pulled and wire bond 32 formed and bonded to conductive element 28 with dicing blade 805 at a location outside the interior of the capillary. After the bond is formed, the wire segment 800 is clamped using a clamp 803 integrated into the bond head assembly to secure the wire position. The cutting blade 803 can then be moved into the wire segment to completely cut the wire or partially cut or wear the wire. A complete cut can form the end face 38 of the wire bond 32 at which point the capillary 804 can be moved away from the wire bond 32 to form another wire bond, for example. Similarly, if the wire segment 800 is worn by the cutting blade 805, movement of the bond head unit while the wire is still held by the wire clamp 803 may cause separation by breaking the wire segment 800 at the area worn by the partial cutting.

Movement of the cutting disc 805 can be initiated by pneumatic means or a servo motor using an eccentric cam. In other examples, movement of cutting disc 805 may be activated by a spring or diaphragm. The trigger signal to initiate the dicing blade 805 may be based on a time delay timed from the formation of the ball bond, or by moving the capillary 804 to a predetermined height above the wire bond substrate 34 to initiate the trigger signal. Such a signal may be correlated with other software operating the bonding machine to reset the position of the dicing blade 805 prior to any subsequent bond formation. The cutting mechanism may also include a second cutting blade (not shown) opposite and spaced from cutting blade 805 to cut the wire from opposite sides of the wire.

In another example, the laser 809 is assembled with the bond head unit and positioned to cut the wire segments. As shown in FIG. 33 , the laser head 809 may be disposed external to the capillary 804 , for example by mounting to the capillary 804 or at another point on the bond head unit including the capillary 804 . The laser may be activated at a desired time (such as discussed above with respect to dicing blade 805 in FIG. 32 ) to cut line 800 to form end face 38 of wire bond 32 at a predetermined height above substrate 34 . In other implementations, the laser 809 may be arranged to direct the cutting beam through or into the capillary 804 itself, and into the interior of the bond head unit. In one example, a carbon dioxide laser may be used, or alternatively, a Nd:YAG or copper vapor laser may be used.

In another embodiment, the template 824 shown in FIGS. 34A-C is used to separate the wire bonds 32 from the remaining wire segments 800 . As shown in FIG. 34A , the template 824 may be a structure having a body defining an upper surface 826 at or near the desired height of the wire bonds 32 . Stencil 824 may be configured to contact conductive elements 28 or any portion of substrate 12 between conductive elements 28 . Stencil 824 includes a plurality of holes 828 corresponding to desired locations of wire bonds 32 (eg, over conductive elements 28 ). The hole 828 may be sized to receive the capillary 804 of the bond head unit therein such that the capillary extends into the hole to a position relative to the conductive element 28 to bond the wire 800 to the conductive element 28 to form the base 34 (eg, via ball bonding, etc.). The capillary 804 can move vertically out of the hole 828 when the wire segment is drawn to the desired length. Once cleared from the hole 828, the wire segment can be clamped (e.g., by the clamp 803) within the bond head unit, and the capillary 804 moved in a lateral direction (e.g., parallel to the surface 826 of the template 824) to move the wire segment 800 The edge 829 of the template 824 defined by the intersection of the surface of the hole 828 and the outer surface 826 of the template 824 is contacted. This movement may cause wire bond 32 to separate from the remainder of wire segment 800 that remains within capillary 804 . The above process is repeated to form a desired number of wire bonds 32 at desired locations. In an implementation, prior to wire separation, the capillary is moved vertically so that the remaining wire segment protrudes beyond the face 806 of the capillary 804 by a distance 802 sufficient to form the next spherical bond. FIG. 34B shows a variation of the template 824 in which the holes 828 can be tapered so that the diameter of the holes increases from a first diameter at the surface 826 to a larger diameter away from the surface 826 . In another variation shown in FIG. 34C , a template may be formed having an outer frame 821 of a thickness sufficient to space surface 826 from substrate 12 by a desired distance. A frame 821 may at least partially surround the cavity 823, the frame 821 is configured to be disposed adjacent to the substrate 12, the thickness of the template 824 extends between the surface 826 and the open area 823 such that the portion of the template 824 including the hole 828 is in contact with the substrate 12. are arranged on the substrate 12 at intervals.

20 and 21 illustrate a further embodiment of a microelectronic assembly 510 in which wire bonds 532 are formed on a lead frame structure. Examples of lead frame structures are shown and described in US Patent Nos. 7,176,506 and 6,765,287, the disclosures of which are incorporated herein by reference. In general, a lead frame is a structure formed of a conductive metal sheet, such as copper, that is patterned into segments including a plurality of leads and may further include a paddle and a frame. If used during component manufacturing, this frame can be used to fasten the leads and chassis. In one embodiment, a microelectronic element, such as a wafer or chip, may be face-up coupled to the chassis and electrically connected to leads using wire bonds. Alternatively, the microelectronic component may be mounted directly to leads extending beneath the microelectronic component. In this embodiment, the contacts on the microelectronic element may be electrically connected to the respective leads by solder balls or the like. The leads can then be used to form electrical connections to various other conductive structures for carrying electrical signal potentials to or from the microelectronic components. When the assembly of the structure, including forming the encapsulation layer thereon, is complete, the temporary elements of the frame can be removed from the leads and chassis of the leadframe to form individual leads. For the purposes of the present invention, the individual leads 513 and chassis 515 are considered to be separate parts collectively forming the substrate 512 including the conductive element 528 in a part integrally formed therewith. Furthermore, in this embodiment, the chassis 515 is considered to be within a first region 518 of the substrate 512 and the leads 513 are considered to be within a second region 520 . In the front view of FIG. 21 , wire bonds 524 connect the microelectronic element 22 carried on the chassis 515 to the conductive elements 528 of the leads 515 . Wire bond 532 may be further coupled to additional conductive element 528 on lead 515 at base 534 of the wire bond. Encapsulation layer 542 is formed onto assembly 510 such that ends 538 of wire bonds 532 are uncovered at locations within surface 544 . In corresponding structures with respect to other embodiments described herein, wire bonds 532 may have additional or alternative portions not covered by encapsulation layer 542 .

24-26 illustrate a further alternative embodiment of a microelectronic package 810 having a closed loop wire bond 832 . The wire bond 832 of this embodiment includes two bases 834a and 834b (as shown in FIG. 24 ) that can be coupled to adjacent conductive elements 828a and 828b. Optionally, both bases 834a and 834b may be coupled to a common conductive element 828 (as shown in FIGS. 25 and 26 ). In this embodiment, the wire bond 832 defines an edge surface 837 extending in a ring between the two bases 834a, 834b such that the edge surface 837 extends upwardly from the base to the base on the substrate 812 in respective portions 837a and 837b. Vertex 839 at surface 844 of encapsulation layer 842 . The encapsulation layer 842 extends along at least some of the edge surface portions 837a, 837b such that the portions are separated from each other and from other wire bonds 832 in the package 810 . At apex 839, at least a portion of edge surface 837 is uncovered by encapsulation layer 842 so that wire bonds 832 are available for electrical interconnection with another component, which may be another microelectronic component or other component, such as a discrete Components such as capacitors or inductors. As shown in FIGS. 24-26 , wire bonds 832 are formed with apex 839 offset from conductive element 828 in at least one lateral direction across the surface of substrate 812 . In one example, apex 839 may cover a major surface of microelectronic element 820 , or otherwise cover a first region of substrate 812 that is aligned with microelectronic element 820 . Other configurations of wire bonds 832 are possible, including configurations in which apex 839 is disposed at any one of the end faces of the wire bonds described in other embodiments. Further, apex 839 may be uncovered in the hole (as shown in FIG. 8A ). Still further, apex 839 may be stretched and may be uncovered over surface 844 and extend the length of surface 844, as shown with respect to the edge surfaces in FIGS. 10A-10D . By providing a connection feature in the form of an uncovered edge surface 837 surrounding the apex 839 supported by a wire bond 832 extending between two bases 834a, 834b (rather than one), it is possible to achieve More precise placement of connection features in defined directions.

Figures 27 and 28 show a variation of the embodiment in Figures 24-26 in which bond ribbons 934 are used instead of wire bonds 834. The bond ribbon may be a generally flat sheet of conductive material, such as any of the previously described wire bond forming materials. In contrast to wire bonds, which are generally circular in cross-section, the bond ribbon structure can be wider than it is thick. As shown in FIG. 27 , each bond ribbon 934 includes a first base 934a bonded to and extending along a portion of the conductive element 928 . The second base 934b of the bonding ribbon 932 may be coupled to a portion of the first base 934a. Edge surface 937 extends between bases 934a and 934b to apex 939 in two corresponding portions 937a and 937b. A portion of the edge surface in the region of apex 939 is uncovered by encapsulant 942 and is disposed along a portion of major surface 944 . Further variations are also possible, such as those described with respect to the wire bonding used in other embodiments disclosed herein.

The structures discussed above can be used to construct different electronic systems. For example, a system 711 according to a further embodiment of the invention includes a microelectronic assembly 710 (described above) and other electronic components 713 and 715 . In the example described, component 713 is a semiconductor chip and component 715 is a display screen, but any other components may be used. Of course, although FIG. 23 depicts only two additional components (for clarity of illustration), the system may include any number of such components. The microelectronic assembly 710 as described above can be, for example, the microelectronic assembly described above in connection with FIG. 1 , or a structure comprising a plurality of microelectronic assemblies as described with reference to FIG. 6 . Assembly 710 may further include any of the embodiments described in FIGS. 2-22. In further variations, multiple variations may be provided, and any number of such structures may be used.

Microelectronic assembly 710 and components 713 and 715 are mounted within a common housing 719 (shown schematically in phantom) and are optionally electrically interconnected with each other to form the desired circuitry. In the exemplary system, the system includes a circuit board 717, such as a flexible printed circuit board, that includes a number of conductors 721 (only one of which is shown in FIG. 23) interconnecting components. However, this is merely exemplary and any suitable structure suitable for making electrical connections may be used.

Housing 719 is described as a portable housing of the type usable in, for example, a mobile phone or personal digital assistant, with screen 715 exposed at the surface of the housing. Where the microelectronic assembly 710 includes a photosensitive element such as an imaging chip, a lens 723 or other optical device may also be provided for directing light to the structure. Likewise, the simplified system shown in FIG. 23 is merely exemplary, and other systems can be made using the structures described above, including systems that are generally considered fixed structures, such as desktop computers, routers, and the like.

The above-described embodiments and modifications of the present invention may be combined in other ways than those specifically described above. All such variations within the scope and spirit of the invention are intended to be covered herein.

Although the invention has been described herein with reference to specific embodiments, it should be understood that these embodiments are merely illustrative of the principles and applications of the invention. It is therefore to be understood that various modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (41)

1. a manufacture method for microelectronics Packaging, comprising:

A) from the capillary feeding of bonding tool, there is the metal wire sections of predetermined length;

B) use described bonding tool a part for described metal wire to be bonded to the conducting element on the first surface that is exposed to substrate, thereby on described conducting element, form the base of line bonding;

C) part for described line is clamped in described bonding tool;

D) described metal wire is cut to limit at least in part the end face of described line bonding in the position between holding portion and described base section, and the edge surface of described line bonding is limited between described base and described end face;

E) repeating step (a)-(d) to be formed to a plurality of line bondings of a plurality of described conducting elements of described substrate; And

E) then form the medium encapsulated layer on the described surface that covers described substrate, wherein, described encapsulated layer forms and covers at least in part the described surface of described substrate and the part of described line bonding, so that the not packed part of described line bonding is limited by the end face not covered by described encapsulated layer of described line bonding or at least one the part in edge surface.

2. method according to claim 1, wherein, described metal wire is only passed and cuts by part, wherein, from the described surface of described substrate, remove described bonding tool, and the described part of described line is still held so that described line ruptures in location of cut, described end face by described cutting and described in break to form.

3. method according to claim 1, wherein, passes completely through described line segment in the direction in cardinal principle perpendicular to the described edge surface of described line bonding and cuts, and the described end face of described line bonding forms by described cutting.

4. method according to claim 1, wherein, at least one microelectronic element covers the described first surface of described substrate, wherein, described substrate has first area and second area, and described microelectronic element is positioned at described first area, and described conducting element is positioned at described second area and is electrically connected to described at least one microelectronic element, wherein, described medium encapsulated layer forms the described first surface that at least covers described substrate in the described second area of described substrate.

5. method according to claim 4, wherein said package arrangements is applicable to carry first signal current potential and second described line bonding is applicable to carry the secondary signal current potential that is different from described first signal current potential simultaneously for line bonding described in first.

6. method according to claim 1, wherein, is used the laser being arranged on described bonding tool to cut described metal wire sections.

7. method according to claim 6, wherein, described capillary limits it for the face of line segment described in feeding, and wherein said laser is arranged on described bonding tool cutting light beam to be guided to a position of the described line segment between the described base that is arranged in described of described bonding tool and described line bonding.

8. method according to claim 6, wherein, described bonding tool comprises its capillary for the face of line segment described in feeding of restriction, described capillary is included in the wall forming in its sidewall, wherein, described laser is arranged on described bonding tool and passes described opening to a position that is arranged in the described line segment in described capillary with guiding cutting light beam.

9. method according to claim 6, wherein, described laser is CO ₂, a kind of in Nd:YAG or copper-vapor laser.

10. method according to claim 1, wherein, uses the cutting edge extending in described capillary to cut described metal wire.

11. methods according to claim 10, wherein, described cutting edge extends upward in the side of the described wall capillaceous towards relative with described line segment.

12. methods according to claim 10, wherein, are combined with cut described metal wire with extending in described capillary with the second cutting edge relative with described the first cutting edge by the described cutting edge as the first cutting edge.

13. methods according to claim 1, wherein, described capillary limits it for the face of line segment described in feeding, wherein, with the cutter sweep with the first relative cutting edge and the second cutting edge, cut described metal wire, wherein, described cutter sweep is arranged on described bonding tool with the position between the described base of described of described bonding tool and described line bonding and cuts described line segment.

14. methods according to claim 1, further comprise template is arranged on described substrate, described template has at least part of a plurality of openings that cover and expose described conducting element, described opening limits each edge that is arranged in the first At The Height on described substrate, wherein, by described line, against the transverse shifting at the described edge of described template opening, cut described line segment.

The manufacture method of 15. 1 kinds of microelectronics Packaging, comprising:

A) template is arranged in to processing with on unit, this processing comprises having first surface and away from the substrate of the second surface of described first surface with unit, microelectronic element is mounted to the described first surface of described substrate, a plurality of conducting elements are exposed on described first surface, described at least some, conducting element is electrically connected to described microelectronic element, described template has at least part of a plurality of openings that cover and expose described conducting element, and described opening limits each edge that is arranged in the first At The Height on described substrate;

B) by a technique, form line bonding, described technique comprises the metal wire sections from the capillary feeding of bonding tool with predetermined length, the part of described line segment is attached to a described conducting element to form the base of described line bonding, and against the transverse shifting at the described edge of described template opening, shear described line segment by described line, with the remainder of the described line bonding of separation and described line segment and at described line bonding upper limit fixed end face, described line bonding is limited to the edge surface extending between described base and described end face; And

C) repeating step (b) to form a plurality of line bondings on a plurality of described conducting elements.

16. methods according to claim 15, further be included in described processing with forming medium encapsulated layer on unit, wherein, described encapsulated layer forms the part that covers at least in part described first surface and described line bonding, so that the not packed part of described line bonding is limited by the described end face not covered by described encapsulated layer of described line bonding or at least one the part in described edge surface.

17. methods according to claim 15, wherein, the described remainder that extends beyond the described line segment of described capillaceous has the length of the base that is enough to form at least next line bonding.

18. methods according to claim 15, wherein, described template is limited to the thickness on the axis direction in a described hole, and wherein, described at least some, hole has the consistent diameter of the described thickness that runs through described template.

19. methods according to claim 15, wherein, described template is limited to the thickness on the axis direction in a described hole, and wherein, described at least some, hole becomes the larger diameter of the position between described edge and described substrate gradually from the small diameter at contiguous described edge.

20. methods according to claim 15, wherein, described template comprises the first thickness of having in the direction of the thickness of described substrate and the fringeware extending along one or more edges of described substrate, described the first thickness limits described the first height, and core comprises described hole and is defined by described fringeware, described core has the outer surface that deviates from described substrate, described outer surface is arranged on described the first At The Height, and described core further has the thickness that is less than described the first thickness.

The manufacture method of 21. 1 kinds of microelectronics Packaging, comprising:

A) from the capillary feeding of bonding tool, there is the metal wire sections of predetermined length;

B) use described bonding tool a part for described metal wire to be bonded to the conducting element on the first surface that is exposed to substrate, thereby on described conducting element, form the base of line bonding;

C) part for described line is clamped in described bonding tool; And

D) in described capillary, described metal wire is cut to limit at least in part apart from the end face of the described line bonding of the described base preset distance of described line bonding in the position between holding portion and described base.

22. methods according to claim 21, further comprise:

E) repeating step (a)-(d) to be formed to a plurality of line bondings of a plurality of described conducting elements of described substrate; And

F) then form the medium encapsulated layer of the described first surface that covers described substrate, wherein, described encapsulated layer forms the part of the described first surface and the described line bonding that cover at least in part described substrate, so that the not packed part of described line bonding is limited by the described end face not covered by described encapsulated layer of described line bonding or at least one the part in the edge surface extending between described base and described end face.

23. methods according to claim 21, wherein, described metal wire is only passed and cuts by part, wherein, from the described first surface of described substrate, remove described bonding tool, and the described part of described line is still held so that described line ruptures in location of cut, described end face by described cutting and described in break to form.

24. methods according to claim 21, wherein, in direction in cardinal principle perpendicular to the edge surface of the described line bonding extending between described base and described end face, pass completely through described line segment and cut, the described end face of described line bonding forms by described cutting.

25. methods according to claim 22, wherein, at least one microelectronic element covers the described first surface of described substrate, wherein, described substrate has first area and second area, and described microelectronic element is positioned at described first area, and described conducting element is positioned at described second area and is electrically connected to described at least one microelectronic element, wherein, described medium encapsulated layer forms the described first surface that at least covers described substrate in the described second area of described substrate.

26. methods according to claim 25, wherein said package arrangements is applicable to carry first signal current potential and second described line bonding is applicable to carry the secondary signal current potential that is different from described first signal current potential simultaneously for line bonding described in first.

27. methods according to claim 21, wherein, are used the laser being arranged on described bonding tool to cut described metal wire.

28. methods according to claim 21, wherein, are used the cutting edge extending in described capillary to cut described metal wire.

29. methods according to claim 28, wherein, described cutting edge extends upward in the side towards described wall capillaceous.

30. methods according to claim 21, wherein, described capillary limits it for the face of line described in feeding, wherein, with the cutter sweep with the first relative cutting edge and the second cutting edge, cut described metal wire, wherein, described cutter sweep is arranged on described bonding tool with at line described in described capillary internal cutting.

The manufacture method of 31. 1 kinds of microelectronics Packaging, comprising:

A) provide the surface of the structure being associated with the substrate of processing with unit, described substrate has first surface and away from the second surface of described first surface, a plurality of conducting elements are exposed on described first surface, and described structure has at least part of a plurality of openings that cover and expose described conducting element; And

B) by a technique, form line bonding, described technique comprises the capillary feeding metal wire from bonding tool, the part of described line is attached to a described conducting element to form the base of described line bonding, with respect to the described base of described line bonding, move described bonding tool and think that described line bonding provides the described line of predetermined length, and by described bonding tool, with respect to the movement on the described surface of described structure, carry out the remainder of separated described line bonding and described line, to limit the free end away from the described line bonding of the described base of described line bonding.

32. methods according to claim 31, wherein, described structure is removable template.

33. methods according to claim 31, wherein, described structural configuration is on the described first surface of described substrate.

34. methods according to claim 31, wherein, the described surface of described structure is included in the edge of opening part described at least one, wherein, by described line, against the movement at described edge, shears described line, until described line bonding is separated with described line.

35. methods according to claim 31, wherein, microelectronic element is mounted to the described first surface of described substrate, and described at least some, conducting element is electrically connected to described microelectronic element.

36. methods according to claim 31, further comprise:

C) repeating step (b) to form a plurality of line bondings on a plurality of described conducting elements.

37. methods according to claim 36, further be included in described processing with forming medium encapsulated layer on unit, wherein, described medium encapsulated layer forms described first surface and the part that covers at least in part described line bonding, so that the not packed part of described line bonding is limited by the end face of the described free end not covered by described encapsulated layer of described line bonding or at least one the part in the edge surface extending between described base and described end face.

38. methods according to claim 31, wherein, the described remainder that extends beyond the described line of described capillaceous has the length of the base that is enough to form at least next line bonding.

39. methods according to claim 31, wherein, the thickness of described structure qualification on the axis direction of a described opening, wherein, described at least some, opening has the consistent diameter of the thickness that runs through described structure.

40. methods according to claim 31, wherein, the thickness of described structure qualification on the axis direction of a described opening, wherein, described at least some, the small diameter at opening edge on the described surface of the described structure of the first At The Height on described substrate from disposed adjacent becomes the larger diameter of the position between described edge and described substrate gradually.

41. methods according to claim 31, wherein, described structure comprises the first thickness of having in the direction of the thickness of described substrate and the fringeware extending along one or more edges of described substrate, described the first thickness limits the first height that the edge on the described surface of described structure is arranged on described substrate, and core comprises described opening and is defined by described fringeware, described core has the outer surface that deviates from described substrate, described outer surface is arranged on described the first At The Height, described core further has the thickness that is less than described the first thickness.