CN101330075B - Three-dimensional packaging structure - Google Patents
Three-dimensional packaging structure Download PDFInfo
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- CN101330075B CN101330075B CN 200710111853 CN200710111853A CN101330075B CN 101330075 B CN101330075 B CN 101330075B CN 200710111853 CN200710111853 CN 200710111853 CN 200710111853 A CN200710111853 A CN 200710111853A CN 101330075 B CN101330075 B CN 101330075B
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- semiconductor package
- lead frame
- packaging structure
- energy storage
- dimensional packaging
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 29
- 239000004065 semiconductor Substances 0.000 claims abstract description 73
- 238000004146 energy storage Methods 0.000 claims abstract description 51
- 230000005291 magnetic effect Effects 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims description 22
- 239000003292 glue Substances 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 7
- 229910052802 copper Inorganic materials 0.000 claims description 7
- 239000010949 copper Substances 0.000 claims description 7
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 7
- 239000000853 adhesive Substances 0.000 claims description 5
- 230000001070 adhesive effect Effects 0.000 claims description 5
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 claims description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 4
- 229910052709 silver Inorganic materials 0.000 claims description 4
- 239000004332 silver Substances 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 239000003822 epoxy resin Substances 0.000 claims description 2
- 229910052742 iron Inorganic materials 0.000 claims description 2
- 229910052759 nickel Inorganic materials 0.000 claims description 2
- 229920000647 polyepoxide Polymers 0.000 claims description 2
- 230000005669 field effect Effects 0.000 claims 2
- 229910044991 metal oxide Inorganic materials 0.000 claims 2
- 150000004706 metal oxides Chemical class 0.000 claims 2
- 229920001296 polysiloxane Polymers 0.000 claims 1
- 238000005538 encapsulation Methods 0.000 description 23
- 238000004804 winding Methods 0.000 description 11
- 238000005516 engineering process Methods 0.000 description 7
- 239000004020 conductor Substances 0.000 description 6
- 238000000034 method Methods 0.000 description 6
- 238000000465 moulding Methods 0.000 description 5
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 208000032365 Electromagnetic interference Diseases 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000002699 waste material Substances 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- NHDHVHZZCFYRSB-UHFFFAOYSA-N pyriproxyfen Chemical compound C=1C=CC=NC=1OC(C)COC(C=C1)=CC=C1OC1=CC=CC=C1 NHDHVHZZCFYRSB-UHFFFAOYSA-N 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 239000000741 silica gel Substances 0.000 description 1
- 229910002027 silica gel Inorganic materials 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
A three-dimensional packaging structure comprises a semiconductor packaging body, an energy storage element and a shielding layer, wherein the semiconductor packaging body is provided with a first conductive element, a second conductive element and a control element, the energy storage element is stacked on the semiconductor packaging body, the energy storage element is electrically connected with the second conductive element and comprises a magnetic body, and the shielding layer is arranged between the control element and at least part of the magnetic body so as to block or reduce electromagnetic interference and enable the packaging structure to be more miniaturized. The three-dimensional packaging structure can be applied to a load point converter.
Description
Technical field
The present invention relates to a kind of encapsulating structure, particularly relate to a kind of semi-conductive stereo encapsulation structure.
Background technology
The common trend of each electronic product is nothing more than light, thin, short, little now, how in limited space, puts maximum element or circuit, and this is that the designer of present design electronic products wants the target that reaches most.Therefore, based on this idea, three-dimensional encapsulating structure also becomes the settling mode that improves component density.
POL (Point-of-Load, POL) transducer is called DC-to-DC converter (DC/DC converter) again, traditional POL transducer is that (Ball GridArray, BGA) (Land Grid Array, LGA) mode such as encapsulation encapsulates for encapsulation or Organic Land Grid Array with ball grid array.
As shown in Figure 1, known load point transducer 1 comprises control element 11, MOS (metal-oxide-semiconductor) memory (MOSFET) 13 and choking-winding (choke) 15, with the BGA Package is example, control element 11, MOS (metal-oxide-semiconductor) memory chip 13 and choking-winding 15 are electrically connected on the substrate 17 (for example printed circuit board (PCB)) with line design, are packaged into a POL transducer encapsulating structure with mould envelope (Molding) technology again.
Because being control element, MOS (metal-oxide-semiconductor) memory chip, choking-winding and other element with POL transducer 1, known method for packing is electrically connected on the same plane of substrate, shared area is bigger, can't satisfy light, thin, short, little demand, and the equal mould of all elements is encapsulated in the single packaging body, so use poor flexibility, and when component wear is arranged, promptly need whole encapsulating structure replacing is caused waste of material.In addition, choking-winding also can to control element produce electromagnetic interference (Electro-Magnetic Interference, EMI).
Summary of the invention
One of the present invention purpose proposes a kind of stereo encapsulation structure, to solve the problem of known package structure.
Another object of the present invention proposes a kind of stereo encapsulation structure, and the setting that utilizes screen is to block or to reduce electromagnetic interference.
The present invention's another purpose proposes a kind of stereo encapsulation structure, and energy-storage travelling wave tube is stacked on the semiconductor package body, makes the encapsulating structure that obtains more miniaturization.
The present invention's a purpose again proposes a kind of stereo encapsulation structure, can promote the integral heat sink effect.
The present invention's another purpose, a kind of stereo encapsulation structure is proposed, be applied to a POL transducer, and with remaining component package except choking-winding in the POL transducer in the semiconductor packaging body, adopt vertical stacking to form stereo encapsulation structure, to obtain the encapsulating structure of more miniaturization semiconductor package body and choking-winding again.
For achieving the above object, the stereo encapsulation structure of one embodiment of the invention comprises semiconductor packaging body, an energy-storage travelling wave tube and a screen, semiconductor package body has one first conducting element, one second conducting element and a control element, energy-storage travelling wave tube is stacked on the semiconductor package body, energy-storage travelling wave tube is electrically connected at this second conducting element and comprises a magnetic, screen is arranged at control element and between this magnetic of small part, use and block or reduce electromagnetic interference, and make the encapsulating structure that obtains more miniaturization.Stereo encapsulation structure of the present invention can be applicable to the POL transducer in addition.
By above-mentioned technical characterictic, beneficial effect of the present invention shows as: adopt the mode of vertical stacking to assemble stereo encapsulation structure, can improve well known elements problem on the same plane all is set, make the encapsulating structure that obtains more miniaturization.And utilize the advantage of the elevated track density of substrate with circuit arrangement, and enable under small size, but can do highly integrated circuit design, meet market miniaturization demand.In addition, utilize the setting of screen can effectively block or reduce electromagnetic interference.
Description of drawings
Fig. 1 is the encapsulating structure schematic diagram of known POL transducer.
Fig. 2 is one embodiment of the invention stereo encapsulation structure schematic side view.
Fig. 3 A to Fig. 3 D is second conducting element of semiconductor package body of the present invention and the various structural profile schematic diagrames of screen.
Fig. 4 A is the generalized section of the stereo encapsulation structure of POL transducer of the present invention.
Fig. 4 B is second half conductor package interior structural representation of the present invention.
Symbol description among the figure
1 POL transducer
11 control elements
13 MOS (metal-oxide-semiconductor) memory (MOSFET)
15 choking-windings (choke)
17 substrates
2 stereo encapsulation structures
21 semiconductor package body
23 energy-storage travelling wave tubes
25 screens
27 follow glue
211 second surfaces
212 control elements
213 first surfaces
215 sidewalls
216 first conducting elements
217,217a, 217b, 217c second conducting element
218 lead frames
The 218a pin
219 conductor structures
231 electrodes
232 magnetics
3 POL transducers
31,31a, 31b semiconductor package body
311 lead frames
3111 first surfaces
312 substrates
313 control elements
314 MOS (metal-oxide-semiconductor) memory
315 resistance
316 electric capacity
33 energy-storage travelling wave tubes
331 electrodes
332 coils
333 magnetics
35 screens
Embodiment
Being described in detail as follows of some embodiments of the invention, however except this was described in detail, the present invention can also be widely implements at other embodiment.That is scope of the present invention is not subjected to the restriction of the embodiment that proposed, and should be as the criterion with the claim that the present invention proposes.In addition, for clearer description being provided and being more readily understood the present invention, each several part is not drawn according to its relative size in the accompanying drawing, and some size is compared with other scale dependent and exaggerated; Uncorrelated detail section is not drawn fully yet, succinct in the hope of accompanying drawing.
As shown in Figure 2, the stereo encapsulation structure 2 of one embodiment of the invention comprises semiconductor package body 21, energy-storage travelling wave tube 23 and screen 25.Semiconductor package body 21 has first surface 213, with respect to the second surface 211 of first surface 213, and be connected in sidewall 215 between first surface 213 and the second surface 211.The second surface 211 of semiconductor package body 21 or sidewall 215 can have a plurality of first conducting elements 216, but not as limit.First conducting element 216 in order to extraneous (for example: motherboard) electrically connect.First conducting element 216 can be pin (lead), weld pad (pad) or tin ball (solder ball), but not as limit.Semiconductor package body 21 has more a plurality of second conducting elements 217, in order to electrically connect with energy-storage travelling wave tube 23.First conducting element 216 can be arranged at first surface 213, but not as limit.Semiconductor package body 21 can for example be: quad flat non-pin package (Quad Flat No-lead package, QFN), quad flat formula encapsulating structure (Quad Flat Package, QFP) or microminiature encapsulation (SSO) etc., but not as limit.Semiconductor package body 21 also comprises a control element 212, for example is control chip (IC) or chip for driving (IC) etc.
Energy-storage travelling wave tube 23 is stacked on the first surface 213 of semiconductor package body 21.Energy-storage travelling wave tube 23 is electrically connected at second conducting element 217, and in present embodiment, energy-storage travelling wave tube 23 for example is an inductance (Inductor), and has coil (not shown), a magnetic 232 and electrode 231.Electrode 231 is in order to electrically connecting with second conducting element 217, and electrode 231 can directly form by the coil two ends, or forms in coil two ends connection lead frame, but not as limit.
Encapsulating structure with Fig. 2 experimentizes, and supposes that the frequency of operation of control element 212 is 200KHz, and when screen 25 adopted the sheet metal of copper materials, the frequency of operation that measures was vibrated in 200～300KHz; When screen 25 adopted the sheet metal of aluminium material, the frequency of operation that measures was vibrated in 200～400KHz; And when screen 25 was not set, the frequency of operation that measures was vibrated in 200～600KHz; Hence one can see that, can be subjected to the interference of magnetic 232 when control element 212 is operated, and makes the frequency of control element 212 produce vibration, can effectively reduce the amplitude of hunting of frequency by screen 25.
In addition, when screen 25 is sheet metal, two kinds of implantation modes are arranged still.First method is in semiconductor package body 21 or energy-storage travelling wave tube 23 models (molding) processing procedure, screen 25 is inserted in semiconductor package body 21 or the energy-storage travelling wave tube 23, make screen 25 be coated on (as Fig. 3 B) or energy-storage travelling wave tube 23 interior (as Fig. 3 C) in the semiconductor package body 21.In detail, shown in Fig. 3 B, screen 25 is provided with in the semiconductor package body 21, and when semiconductor package body 21 electrically connected with energy-storage travelling wave tube 23, screen 25 can block or reduce the electromagnetic interference of 23 pairs of semiconductor package body 21 of energy-storage travelling wave tube (particularly control element 212).Shown in Fig. 3 C, screen 25 is provided with in the energy-storage travelling wave tube 23, and when semiconductor package body 21 electrically connected with energy-storage travelling wave tube 23, screen 25 can block or reduce the electromagnetic interference of 23 pairs of semiconductor package body 21 of energy-storage travelling wave tube (particularly control element 212).
Second method is to utilize the part of lead frame of the part of the lead frame of semiconductor package body 21 (lead frame) 218 or energy-storage travelling wave tube 23 as screen 25, shown in Fig. 3 D, when lead frame 218 designs, reserve a part of lead frame as screen 25, before mould envelope (molding) processing procedure, earlier lead frame 218 is bent to control element 212 and, carries out mould envelope (molding) processing procedure again between the small part magnetic 232.Perhaps, can utilize the lead frame (being electrode 231) of energy-storage travelling wave tube 23 to be bent to earlier between semiconductor package body 21 and the energy-storage travelling wave tube 23, do with semiconductor package body 21 or energy-storage travelling wave tube 23 with the then glue of high-termal conductivity again and be connected as screen 25.
About second conducting element, 217 generation types and and the mode of energy-storage travelling wave tube 23 electric connections, be described in detail in down.As shown in Figure 3A, utilize the lead frame 218 of semiconductor package body 21 to form first conducting element 216 (as shown in Figure 2), reserving pin 218a simultaneously extends outside the semiconductor package body 21, and after semiconductor package body 21 moulds envelopes (molding) are finished, upwards be bent to first surface 213 to form the second conducting element 217a along semiconductor package body 21 surfaces, (for example: (SurfaceMounting Technology SMT) assembles and finishes electric connection with the second conducting element 217a to the electrode 231 of energy-storage travelling wave tube 23 lead frame) to utilize the surface adhering technology again.Perhaps, shown in Fig. 3 B, conductor structure 219 (for example copper post) is set on lead frame 218 and conductor structure 219 is extended to towards first surface 213 directions and expose first surface 213, form the second conducting element 217b, the second conducting element 217b utilize again the surface adhering technology (Surface Mounting Technology, SMT) with the electrode 231 of energy-storage travelling wave tube 23 (for example: lead frame) electrically connect.Moreover, shown in Fig. 3 C, conductor structure 219 (for example copper post) is set on lead frame 218 and conductor structure 219 is extended to towards first surface 213 directions and expose first surface 213, form the second conducting element 217c, second conducting element 217 utilizes the electrode 231 of scolding tin (Solder) mode and energy-storage travelling wave tube 23 to electrically connect again.
Shown in Fig. 4 A and Fig. 4 B, stereo encapsulation structure 2 of the present invention can be applicable to POL transducer 3 and claims DC-to-DC converter (DC/DC converter) again.POL transducer 3 comprises semiconductor package body 31a (31b), energy-storage travelling wave tube 33 and screen 35, dependency structure between relevant energy-storage travelling wave tube 33, semiconductor package body 31 and the screen 35 is as described in energy-storage travelling wave tube 23, semiconductor package body 21 and the screen 25 in the above-mentioned stereo encapsulation structure 2, so do not repeat them here.
And bilge construction within semiconductor package body 31a (31b) and the energy-storage travelling wave tube 33, shown in Fig. 4 A.Semiconductor package body 31a comprises lead frame 311, substrate 312 and a plurality of element (for example: control element 313, MOS (metal-oxide-semiconductor) memory 314, resistance 315 and electric capacity 316).Lead frame 311 is arranged on the second surface (being second surface 211) of semiconductor package body 31a.Substrate 312 is stacked on the first surface 3111 of lead frame 311, and in detail, substrate 312 is with glue material (for example elargol) or utilize scolding tin (Solder) mode to pile up to be fixed on the lead frame 311.Substrate 312 is one to have the substrate of circuit arrangement, for example: printed circuit board (PCB) (PCB), use the raising current densities.The subelement of POL transducer 3 can be arranged on the substrate 312, and all the other elements can be arranged on the lead frame 311, to reduce the required area that takies lead frame 311, to obtain the area of littler semiconductor package body 31a.Element on the substrate 312 can form lead or upside-down mounting (flip chip) mode is electrically connected to the circuit on the substrate 312 by the routing mode, with lead the circuit on the substrate 312 is electrically connected to element on lead frame 311 or the lead frame 311 again, the element on the lead frame 311 can form lead or upside-down mounting (flip chip) mode is electrically connected on the lead frame 311 by the routing mode.In the present embodiment, control element 313 and passive device (for example: resistance 315 and electric capacity 316) are set on the substrate 312, power component (for example: MOS (metal-oxide-semiconductor) memory MOSFET 314) is set on the lead frame 311, power component can provide heat radiation by lead frame 311, it is excellent that radiating effect more directly is arranged at substrate, uses the integral heat sink effect that promotes encapsulating structure.Energy-storage travelling wave tube 33 is a choking-winding (Choke) and comprises electrode 331, coil 332 and magnetic 333, magnetic 333 coats coil 332, electrode 331 extends outside the magnetic 333, and electrode 331 can directly be formed by coil 332 two ends or form in coil 332 two ends connection lead frame.
In addition, bilge construction also can be shown in Fig. 4 B within the semiconductor package body 31b, and semiconductor package body 31b comprises lead frame 311, at least one control element 313 and at least one MOS (metal-oxide-semiconductor) memory 314.Control element 313 and MOS field transistor 314 directly are fixed on the lead frame 311, form lead by the routing mode, and control element 313 and MOS field transistor 314 and lead frame 311 are electrically connected.
The present invention adopts the mode of vertical stacking to assemble stereo encapsulation structure, can improve well known elements problem on the same plane all is set, and makes the encapsulating structure that obtains more miniaturization.And utilize the advantage of the elevated track density of substrate with circuit arrangement, and enable under small size, but can do highly integrated circuit design, meet market miniaturization demand.In addition, utilize the setting of screen can effectively block or reduce electromagnetic interference.
Stereo encapsulation structure of the present invention, be applied to the POL transducer, and with remaining component package except choking-winding in the POL transducer in the semiconductor packaging body, adopt vertical stacking to form stereo encapsulation structure, to obtain the encapsulating structure of more miniaturization semiconductor package body and choking-winding again.
Among the present invention choking-winding and remaining element are divided into two independently unit, can make things convenient for the different users to electrical and package dimension requirement, and can do optimal collocation and combination, can make product diversification and reduce slow-witted material risk, elasticity is used in increase.Compared to the prior art, the equal mould of all elements of known technology is encapsulated in the single packaging body, so use poor flexibility, and when component wear is arranged, promptly needs whole encapsulating structure changed and cause waste of material.
The embodiment of the above only is explanation technological thought of the present invention and characteristics, its purpose makes the personage who has the knack of this skill can understand content of the present invention and is implementing according to this, when not limiting claim of the present invention with this, promptly the equalization of doing according to disclosed spirit generally changes or modifies, and must be encompassed in the claim of the present invention.
Claims (19)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200710111853 CN101330075B (en) | 2007-06-20 | 2007-06-20 | Three-dimensional packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200710111853 CN101330075B (en) | 2007-06-20 | 2007-06-20 | Three-dimensional packaging structure |
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| CN101330075A CN101330075A (en) | 2008-12-24 |
| CN101330075B true CN101330075B (en) | 2010-06-02 |
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| CN 200710111853 Active CN101330075B (en) | 2007-06-20 | 2007-06-20 | Three-dimensional packaging structure |
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Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104934188B (en) * | 2010-08-26 | 2018-04-10 | 乾坤科技股份有限公司 | Electronic packaging structure and packaging method thereof |
| US9723766B2 (en) * | 2010-09-10 | 2017-08-01 | Intersil Americas LLC | Power supply module with electromagnetic-interference (EMI) shielding, cooling, or both shielding and cooling, along two or more sides |
| CN102456684B (en) * | 2010-10-15 | 2016-05-04 | 乾坤科技股份有限公司 | Power transfer module |
| TWI449136B (en) * | 2011-04-20 | 2014-08-11 | Cyntec Co Ltd | Metal core printed circuit board and electronic package structure |
| WO2013181768A1 (en) * | 2012-06-06 | 2013-12-12 | 益芯科技股份有限公司 | Precast mold cavity stereoscopic package module having wire layout |
| CN111415813B (en) | 2019-01-07 | 2022-06-17 | 台达电子企业管理（上海）有限公司 | Preparation method of inductor with vertical winding and injection mold thereof |
| CN111415909B (en) | 2019-01-07 | 2022-08-05 | 台达电子企业管理（上海）有限公司 | Multi-chip packaged power module |
| US11676756B2 (en) | 2019-01-07 | 2023-06-13 | Delta Electronics (Shanghai) Co., Ltd. | Coupled inductor and power supply module |
| CN111415908B (en) | 2019-01-07 | 2022-02-22 | 台达电子企业管理（上海）有限公司 | Power module, chip embedded type packaging module and preparation method |
| US11063525B2 (en) | 2019-01-07 | 2021-07-13 | Delta Electronics (Shanghai) Co., Ltd. | Power supply module and manufacture method for same |
| CN111415925B (en) * | 2019-01-07 | 2023-01-24 | 台达电子企业管理（上海）有限公司 | Power module and preparation method thereof |
| CN120033159A (en) * | 2023-11-22 | 2025-05-23 | 华为技术有限公司 | Packaging module, manufacturing method thereof, power supply module and electronic equipment |
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| CN1707793A (en) * | 2004-06-11 | 2005-12-14 | 株式会社东芝 | Semiconductor device having inductor |
| CN1825584A (en) * | 2005-01-24 | 2006-08-30 | 株式会社西铁城电子 | Electronic package and packaging method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1707793A (en) * | 2004-06-11 | 2005-12-14 | 株式会社东芝 | Semiconductor device having inductor |
| CN1825584A (en) * | 2005-01-24 | 2006-08-30 | 株式会社西铁城电子 | Electronic package and packaging method |
Non-Patent Citations (1)
| Title |
|---|
| JP特开2003-309185A 2003.10.31 |
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