CN113035888A

CN113035888A - Electronic device

Info

Publication number: CN113035888A
Application number: CN202110259971.8A
Authority: CN
Inventors: 王睦凯; 黄国有; 陈茂松
Original assignee: AU Optronics Corp
Current assignee: AUO Corp
Priority date: 2020-08-21
Filing date: 2021-03-10
Publication date: 2021-06-25
Anticipated expiration: 2041-03-10
Also published as: CN113035888B

Abstract

An electronic device includes a substrate, a plurality of gate lines, a plurality of data lines, a plurality of pixel structures, a gate transfer line and a transfer structure. A plurality of pixel structures arranged in the same row are electrically connected to data lines on different sides in sequence. The film layer where the gate transfer wire is located is the same as the film layer where the data line is located. The gate connecting line passes through between the pixel structure and the data line to form a cross-line area on the substrate. The film layer where the transfer structure is located is different from the film layer where the gate wiring and the data line are located. In the crossover region, one of the gate transition line and the data line crosses the other of the gate transition line and the data line through the active element of the transition structure or the pixel structure.

Description

Electronic device

Technical Field

The present disclosure relates to electronic devices, and particularly to an electronic device with an adapter structure.

Background

With the progress of science and technology, large-sized panels are developed toward narrow-bezel designs. Currently, TGP (Tracking Gate-line in Pixel) narrow frame technology is mostly adopted to further reduce the width of the panel frame.

However, the TGP is usually designed as a trace having multiple turns, and the TGP needs to bypass the active devices of the pixels. Thus, the resistance-capacitance loading (RC loading) of the panel is increased by 1.5-2 times, and problems such as coupling with adjacent data lines or gate-drain capacitance (Cgd) are easily caused, thereby affecting the quality of signal transmission in the electronic device. For example, the display effect of the display panel or the sensitivity of the touch panel may be affected. Therefore, how to plan the layout of the circuits, reduce the coupling effect between the circuits, and avoid the increase of the resistance-capacitance load has become a subject of attention of the present researchers.

Disclosure of Invention

The invention provides an electronic device, which is designed to be beneficial to reducing resistance-capacitance load and avoid coupling between circuits so as to improve the quality of the electronic device.

At least one embodiment of the invention provides an electronic device, which includes a substrate, a plurality of gate lines, a plurality of data lines, a plurality of pixel structures, a gate transfer line and a transfer structure. The plurality of gate lines are arranged on the substrate and extend along a first direction. The data lines are configured on the substrate and extend along a second direction, wherein the first direction is intersected with the second direction. The plurality of pixel structures are arrayed on the substrate. Each pixel structure is surrounded by two adjacent grid lines and two adjacent data lines and comprises an active element, wherein the plurality of pixel structures arranged in the same row along the second direction are electrically connected with the data lines on different sides in sequence. The grid transfer line is arranged on the substrate and extends along the second direction. The grid transfer line is electrically connected with one of the grid lines, the film layer where the grid transfer line is located is the same as the film layers of the data lines, and in the top view of the electronic device, the grid transfer line penetrates through the space between one of the pixel structures and the data lines electrically connected with the pixel structures to form a line crossing area on the substrate. The switching structure is arranged on the substrate, and the film layer of the switching structure is different from the film layer of the grid switching line and the data line. In the line crossing region, one of the gate transfer line and the data line crosses over the other of the gate transfer line and the data line through an active device of the transfer structure or the pixel structure.

In an embodiment of the invention, in the wire crossing region, the data line crosses the gate transfer line through a via structure, the via structure extends along the first direction, two ends of the via structure are respectively connected to the data line and the active device of the pixel structure, and the via structure intersects the gate transfer line in a top view of the electronic device.

In an embodiment of the invention, the active device of the pixel structure further includes a vertical wire, wherein the vertical wire is disposed on the substrate, two ends of the vertical wire are connected to the adapting structure and the active device, and the gate adapting line is located between the data line and the vertical wire in a top view of the electronic device.

In an embodiment of the invention, the electronic device further includes a first insulating layer, wherein the first insulating layer covers the gate line and has a first via and a second via, and in a top view of the electronic device, the first via overlaps the data line, and the second via overlaps the vertical conductive line, wherein the first via and the second via respectively expose a portion of the adapting structure, the data line is connected to the adapting structure through the first via, and the adapting structure is connected to the vertical conductive line through the second via.

In an embodiment of the invention, the pixel structure further includes a pixel electrode, the pixel electrode and the data line are electrically connected to the drain and the source on two opposite sides of the active device, respectively, and the pixel electrode and the gate transfer line are separated by a distance in a top view of the electronic device.

In an embodiment of the invention, the electronic device further includes a second insulating layer covering the data line and the gate transfer line and having a third through hole, wherein the third through hole exposes a portion of the active device, and the pixel electrode covers a portion of a surface of the third through hole to connect to the active device.

In an embodiment of the invention, the second insulating layer includes a lower insulating layer conformally disposed on the first insulating layer and an upper insulating layer disposed on the lower insulating layer.

In an embodiment of the invention, the second insulating layer has a single-layer structure.

In an embodiment of the invention, in the cross-line region, the gate patch cord crosses the data line through the via structure, the via structure extends along the second direction, two ends of the via structure are respectively connected to the gate patch cord, and the via structure intersects the data line in a top view of the electronic device.

In an embodiment of the invention, the data line has a main line segment and a branch line segment, the main line segment extends along the second direction, two ends of the branch line segment are respectively connected to the main line segment and the active device of the pixel structure, and the switching structure intersects with the branch line segment in a top view of the electronic device.

In an embodiment of the invention, the electronic device further includes a first insulating layer covering the gate line and having a plurality of fourth through holes, in a top view of the electronic device, the plurality of fourth through holes overlap the gate patch cord, wherein the plurality of fourth through holes expose a portion of the adapting structure, the gate patch cord at one end of the adapting structure is connected to the adapting structure through one of the plurality of fourth through holes, and the adapting structure is connected to the gate patch cord at the other end of the adapting structure through another one of the plurality of fourth through holes.

In an embodiment of the invention, the electronic device further includes a common electrode, and the common electrode is disposed on the substrate and at least overlaps the data line, the gate via and the via structure in a top view of the electronic device.

In an embodiment of the invention, the active device of the pixel structure is a top gate thin film transistor and includes a semiconductor channel layer, and in the line crossing region, the data line crosses the gate transfer line through the via structure and the semiconductor channel layer.

In an embodiment of the invention, the semiconductor channel layer includes a first line segment, a curved line segment and a second line segment, the first line segment and the second line segment extend along the second direction, two ends of the curved line segment are adjacent to the first line segment and the second line segment, in a top view of the electronic device, the first line segment overlaps the data line, and the curved line segment intersects the gate transfer line.

In an embodiment of the invention, the gate line further includes an extension structure, the extension structure extends from the gate line along the second direction, and the gate transfer line is electrically connected to the gate line through the extension structure. The length of the extending structure is 1/10-1/2 of the length of the pixel structure.

In an embodiment of the invention, the electronic device further includes an interlayer dielectric layer interposed between the gate transfer line and the gate line and having a through hole, wherein the gate transfer line covers a surface of the through hole to connect to the extension structure.

In an embodiment of the invention, the electronic device further includes a third insulating layer covering the data line and the gate transfer line and having a trench. The groove extends along the second direction, and in a top view of the electronic device, the groove is located between the data line and the gate transfer line.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

Fig. 1 is a schematic top view of an electronic device according to a first embodiment of the invention.

Fig. 2A is an enlarged schematic view of the crossover region CR according to an embodiment of the electronic device in fig. 1.

FIG. 2B is a schematic diagram of one embodiment of a cross-section along section line A' -A-B-C in the electronic device of FIG. 2A.

FIG. 2C is a schematic diagram of another embodiment of a cross-section of the electronic device of FIG. 2A taken along cross-section line A' -A-B-C.

Fig. 3A is an enlarged schematic view of the crossover region CR of another embodiment in the electronic device of fig. 1.

Fig. 3B is a schematic cross-sectional view of the electronic device of fig. 3A along the sectional line a-a'.

Fig. 4A is a schematic top view of an electronic device according to a second embodiment of the invention.

Fig. 4B is an enlarged schematic view of the crossover region CR in the electronic device of fig. 4A.

Fig. 5A is a schematic top view of an electronic device according to a third embodiment of the invention.

Fig. 5B is a schematic cross-sectional view of the electronic device of fig. 5A taken along the sectional line a-a'.

Fig. 6 is a schematic top view of an electronic device according to a fourth embodiment of the invention.

Description of reference numerals:

10. 10A, 10A1, 10A2, 10B, 20, 30, 40: electronic device

100: substrate

102: buffer layer

110: grid patch cord

120. 200 and 300: switching structure

130: longitudinal wire

140: a first insulating layer

150. 150': a second insulating layer

152: lower insulating layer

154: upper insulating layer

160: a third insulating layer

310: semiconductor channel layer

312: first line segment

314: curved line segment

316: second line segment

320: extension structure

AA: active region

B: blue sub-pixel

CH: semiconductor pattern

COM: common electrode

CR: over-line region

CS: conduction structure

D1: a first direction

D2: second direction

DE: drain electrode

DL, DL1, DL 2: data line

DLa: main line segment

DLb: branch line segment

G: green sub-pixel

GE: grid electrode

GI: gate insulating layer

GL: gate line

ILD: interlayer dielectric layer

M1: first conductor layer

M2: second conductor layer

PE: pixel electrode

R: red sub-pixel

And SE: source electrode

SP: pixel structure

T1, T2: active component

TH: through hole

TR: groove

VIA 1: first through hole

VIA 2: second through hole

VIA 3: third through hole

VIA 4: fourth through hole

Detailed Description

In the drawings, the thickness of layers, films, panels, regions, etc. have been exaggerated for clarity. Like reference numerals refer to like elements throughout the specification. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected to" or "overlapping" another element, it can be directly on or connected to the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, "connected" may refer to physical and/or electrical connections. Further, "electrically connected" or "coupled" may mean that there are additional elements between the elements.

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a "first element," "component," "region," "layer," or "portion" discussed below could be termed a second element, component, region, layer, or portion without departing from the teachings herein.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, including "at least one", unless the content clearly indicates otherwise. "or" means "and/or". As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions integers, steps, operations, elements, components, and/or groups thereof.

Furthermore, relative terms, such as "lower" or "bottom" and "upper" or "top," may be used herein to describe one element's relationship to another element, as illustrated. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures. For example, if the device in one of the figures is turned over, elements described as being on the "lower" side of other elements would then be oriented on "upper" sides of the other elements. Thus, the exemplary term "lower" can include both an orientation of "lower" and "upper," depending on the particular orientation of the figure. Similarly, if the device in one of the figures is turned over, elements described as "below" or "beneath" other elements would then be oriented "above" the other elements. Thus, the exemplary terms "lower" or "upper" may include both an orientation of above and below.

As used herein, "about" includes the stated value and an average value within an acceptable range of deviation of the specified value as determined by one of ordinary skill in the art, taking into account the measurement in question and the specified amount of error associated with the measurement (i.e., the limitations of the measurement system). For example, "about" may mean within one or more standard deviations of the stated value, or within ± 30%, ± 20%, ± 10%, ± 5%. Further, as used herein, "about" may be selected with respect to optical properties, etching properties, or other properties, with a more acceptable range of deviation or standard deviation, and not all properties may be applied with one standard deviation.

Unless defined otherwise, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present invention and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Exemplary embodiments are described herein with reference to cross-sectional views that are schematic illustrations of idealized embodiments. Thus, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, the embodiments described herein should not be construed as limited to the particular shapes of regions as illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, a region shown or described as flat may generally have rough and/or nonlinear features. Further, the acute angles shown may be rounded. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region and are not intended to limit the scope of the claims.

Fig. 1 is a schematic top view of an electronic device according to a first embodiment of the invention. For convenience of explanation, the position of the insulating layer is omitted in fig. 1.

Referring to fig. 1, an electronic device 10 includes a substrate 100, a plurality of gate lines GL, a plurality of data lines DL, a plurality of pixel structures SP, and a gate transfer line 110. The substrate 100 may have an active area AA and a peripheral area (not shown) outside the active area AA. In the embodiment, the material of the substrate 100 may include glass or other suitable materials, but the invention is not limited thereto. The gate line GL is disposed on the substrate 100 and extends along a first direction D1. The data line DL is disposed on the substrate 100 and extends along a second direction D2 intersecting the first direction D1.

A plurality of pixel structures SP are arranged in an array on the substrate 100. In other words, the pixel structures SP may be arrayed along the first direction D1 and the second direction D2, wherein the first direction D1 may be understood as a transverse direction and the second direction D2 may be understood as a longitudinal direction. Therefore, the lateral direction and the longitudinal direction described in the following embodiments can be regarded as the first direction D1 and the second direction D2 in fig. 1, respectively. In the present embodiment, each pixel structure SP is surrounded by two adjacent gate lines GL and two adjacent data lines DL. For example, the pixel structures SP aligned in a row along the first direction D1 are sandwiched between two gate lines GL; the pixel structures SP aligned in a row along the second direction D2 are sandwiched between two data lines DL. Therefore, the pixel structures SP in the same column and the pixel structures SP in the same row described in the following embodiments can be regarded as the pixel structures SP arranged along the first direction D1 and the pixel structures SP arranged along the second direction D2 in fig. 1, respectively.

Each pixel structure SP may include an active device T1 and a pixel electrode PE connected to the active device T1, wherein the active device T1 is electrically connected to the corresponding gate line GL and the data line DL. In the present embodiment, the pixel structures SP arranged in the same row along the second direction D2 can be electrically connected to the data lines DL on different sides in sequence. For example, the active devices T1 of the same row of pixel structures SP may be alternately electrically connected to the data line DL1 on a first side (e.g., the right side of fig. 1) and the data line DL2 on an opposite second side (e.g., the left side of fig. 1). In some embodiments, in the pixel structures SP arranged in a plurality of rows along the first direction D1, the active device T1 of a single row of the pixel structures SP may be electrically connected to the data line DL1 at the first side thereof, and the active device T1 of a double row of the pixel structures SP may be electrically connected to the data line DL2 at the second side thereof, but the invention is not limited thereto.

In some embodiments, the plurality of pixel structures SP may include a plurality of red sub-pixels R, a plurality of green sub-pixels G, and a plurality of blue sub-pixels B respectively arranged along the second direction D2. For example, taking the data line DL1 as labeled in fig. 1 as an example, the data line DL1 can be alternately electrically connected to the blue sub-pixel B and the red sub-pixel R when the data line DL1 is located between the same row of blue sub-pixels B and the same row of red sub-pixels R; taking the data line DL2 shown in fig. 1 as an example, in the case that the data line DL2 is located between the green sub-pixel G and the blue sub-pixel B in the same row, the data line DL2 can be alternately electrically connected to the green sub-pixel G and the blue sub-pixel B, and those skilled in the art can adjust the arrangement and connection relationship of the data line DL and the pixel structure SP according to the design requirement, which is not limited by the invention.

In the present embodiment, the pixel electrode PE and the data line DL can be electrically connected to the drain and the source on two opposite sides of the active layer of the active device T1, respectively. For example, the active device T1 may be a transistor having a gate electrode connected to one of the gate lines GL, a source electrode connected to one of the data lines DL, and a drain electrode connected to the pixel electrode PE. In addition, in order to avoid short circuit between the gate line GL and the data line DL, the gate line GL and the data line DL may be formed of different films, and one or more insulating layers may be interposed between the gate line GL and the data line DL.

The gate interposer 110 is disposed on the substrate 100 and extends along the second direction D2. In the present embodiment, the gate transfer line 110 may be parallel to the data line DL. For example, the gate transfer line 110 and the data line DL may be in a parallel line pattern, or may have a parallel zigzag pattern, but the invention is not limited thereto. In fig. 1, the gate transfer line 110 is located between the data line DL1 and the pixel structure SP adjacent to the pixel structure SP indicated by the dashed frame, for example, and the gate transfer line 110 is not directly connected to the pixel structure SP. In the top view direction of the substrate 100, the gate transfer line 110 directly crosses the connection path between the active device T1 and the data line DL1 of the pixel structure SP. In some embodiments, the pixel electrode PE may not overlap with the gate transfer line 110 in a top view direction of the substrate 100. For example, the pixel electrode PE is spaced apart from the gate transfer line 110 by a distance, but the invention is not limited thereto. In other embodiments, the pixel electrode PE may also overlap the gate transfer line 110.

The gate transfer line 110 and the data line DL may be located in the same film layer. In the present embodiment, the gate transfer line 110 may be electrically connected to one of the gate lines GL, and a layer on which the gate line GL is located may be located in a different layer from the gate transfer line 110 and the data line DL. The active device T1 can be connected to the gate line 110 through one of the gate lines GL. Accordingly, the signal of the gate of the active device T1 can be transmitted to the gate line GL through the gate transfer line 110, and then input to the gate through the gate line GL. In some embodiments, in order to transmit signals from the gate patch lines 110 to the gate lines GL, a conducting structure (e.g., a conducting structure CS indicated by a dashed frame) may be disposed between the corresponding gate patch line 110 and the gate line GL. Thus, the signal of the gate of the active device T1 can be transmitted from the gate switching line 110 to the gate line GL through the conducting structure CS, and then transmitted from the gate line GL to the gate.

In some embodiments, the signal of the gate of the active device T1 is, for example, a signal output from a driving circuit (not shown) located in the peripheral region. In some embodiments, the driving circuit may be located at one end of the gate transfer line 110 and the data line DL. The gate lines GL can receive the signals from the gate patch lines 110 through the corresponding conducting structures CS, and the gate lines GL can receive the signals from the gate patch lines 110 through the corresponding conducting structures CS. As such, the electronic device 10 can achieve the narrow frame design without providing the wires or related circuits for transmitting signals at the two ends of the first direction D1, and the outline of the electronic device 10 is not limited. For example, the electronic device 10 may have a non-rectangular outline as viewed in a top-down direction of the substrate 100. In some embodiments, other vertical signal lines (not shown) may be included in the electronic device 10, and the vertical signal lines may not be used for transmitting signals required by the gate lines GL, but may be inputted with dc potentials. For example, the vertical signal lines may not be connected to any gate lines GL, but may be applied to the implementation of touch control or other functions.

In fig. 1, the gate transfer line 110 can pass through between one of the pixel structures SP and the data line DL1 electrically connected to the pixel structure SP to form a cross-line region CR on the substrate 100. More specifically, in the cross-line region CR, the electronic device 10 further includes a via structure (to be described in detail later) disposed on the substrate 100, wherein a film layer of the via structure is different from a film layer of the gate via line 110 and a film layer of the data line DL1, such that in the cross-line region CR, one of the gate via line 110 and the data line DL1 can cross over the other of the gate via line 110 and the data line DL1 through the active device T1 of the via structure or the pixel structure SP, and therefore, by the via structure in the cross-line region CR, the number of signal line turns can be reduced, and problems such as an increase in resistance-capacitance load and adverse effects caused by coupling between lines can be avoided, thereby improving functions (such as image display, touch sensing, etc.) performed by the electronic device, but the invention is not limited thereto. In other embodiments, the configuration of the adapting structure may be adjusted according to different design or process requirements, which will be described in detail later.

Hereinafter, an embodiment applicable to the above-described embodiment of the relay structure will be described by way of example, but the present invention is not limited to the embodiment described below.

FIG. 2A is an enlarged schematic view of the over line region CR of one embodiment of the electronic device of FIG. 1; FIG. 2B is a schematic diagram of one embodiment of a cross-section of the electronic device of FIG. 2A along section line A' -A-B-C; FIG. 2C is a schematic diagram of another embodiment of a cross-section of the electronic device of FIG. 2A taken along cross-section line A' -A-B-C. Fig. 2A corresponds to the crossover region CR of fig. 1. It should be noted that fig. 2A to 2C use the same or similar reference numbers to indicate the same or similar elements along with the element numbers and part of the contents of the embodiment of fig. 1, and the description of the same technical contents is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, which are not repeated herein.

Referring to fig. 2A and fig. 2B, in the electronic device 10A, the data line DL1 may cross the gate via 110 through the via structure 120 to connect with the active device T1. In the present embodiment, the through structure 120 extends along the first direction D1, and two ends of the through structure 120 are respectively connected to the data line DL1 and the active device T1 of the pixel structure SP. In this way, the via structure 120 and the gate via 110 have an intersection in the planar direction of the substrate 100, thereby constituting the line crossing region CR described in fig. 1. The via structure 120 of the present embodiment is disposed on a same film layer as the gate line GL, and the via structure 120 may be formed of a same material as the gate line GL, but the invention is not limited thereto.

In the present embodiment, the active device T1 of the pixel structure SP may further have a vertical conductive line 130. The vertical wires 130 are disposed on the substrate 100, and two ends of the vertical wires 130 can be connected to the active devices T1 of the adapting structure 120 and the pixel structure SP, respectively. In the top view of the substrate 100, the gate interposer 110 is located between the data line DL1 and the vertical conductive line 130, for example.

For clarity of the film layer relationship of each component in the electronic device, the description will be made with reference to fig. 2A and 2B. Referring to fig. 2A and fig. 2B, the active device T1 includes: a gate electrode GE, a semiconductor pattern CH (serving as a channel layer), a source electrode SE, and a drain electrode DE. In the present embodiment, the active device T1 is illustrated as a bottom gate structure, but the invention is not limited thereto. The gate GE of the active device T1 can be electrically connected to a corresponding gate line GL, and the gate line GL can be electrically connected to a corresponding gate transfer line 110 through the conducting structure CS. The gate electrode GE and the gate line GL belong to the same layer, for example. The semiconductor pattern CH is disposed above the gate electrode GE, for example. The source SE and the drain DE are disposed above the semiconductor pattern CH, for example. In the embodiment, the vertical conductive line 130 may be regarded as an extension of the source SE, but the invention is not limited thereto. In the present embodiment, the gate line GL and the via structure 120 are located on the first conductive layer M1, and the data line DL1 and the gate via 110 are located on the second conductive layer M2, for example, but the invention is not limited thereto. In addition, the first insulating layer 140 may be further included between the first conductive layer M1 and the second conductive layer M2. The first insulating layer 140 covers the gate line GL and the VIA structure 120, and has a first VIA1 and a second VIA 2. As shown in fig. 2A, the first VIA1 overlaps the data line DL1, and the second VIA2 overlaps the vertical conductive line 130 as an extension of the source SE, wherein the first VIA1 and the second VIA2 respectively expose a portion of the VIA structure 120. Thus, the data line DL1 of the second conductive layer M2 can be connected to the VIA structure 120 of the first conductive layer M1 through the conductive structure of the first VIA1, and the VIA structure 120 of the first conductive layer M1 can be connected to the vertical conductive line 130 of the second conductive layer M2 through the conductive structure of the second VIA 2. Therefore, the signal of the data line DL1 of the second conductive layer M2 can be transmitted to the vertical conductive line 130 of the second conductive layer M2 and the source SE of the active element T1 of the pixel structure SP through the via structure 120 of the first conductive layer M1. Accordingly, even though the data line DL1 and the gate via 110 are located in the same film layer, the data line DL1 can cross over the gate via 110 through the via structure 120 in the cross-over region CR, so as to reduce the number of turns in the trace design of the gate via 110, and to avoid the problems of increased resistance-capacitance load and adverse effects caused by the coupling between the lines, thereby improving the functions performed by the electronic device.

As shown in fig. 2B, the electronic device 10a1 of the present embodiment may further include a second insulating layer 150. The second insulating layer 150 covers the data line DL1, the gate transfer line 110, the vertical conductive line 130 and the active device T1 of the pixel structure SP, for example. In this embodiment, the second insulating layer 150 may have a third VIA3, the third VIA3 may expose a portion of the active device T1, and the pixel electrode PE may cover a portion of the surface of the third VIA3 to connect to the active device T1.

The second insulating layer 150 may have a single-layer or multi-layer structure. For example, as shown in fig. 2B, the second insulating layer 150 comprises a lower insulating layer 152 and an upper insulating layer 154, wherein the lower insulating layer 152 can be conformally disposed on the first insulating layer 140, and the upper insulating layer 154 can be disposed on the lower insulating layer 152. In some embodiments, the lower insulating layer 152 may serve as a passivation layer (passivation layer) and the upper insulating layer 154 may serve as a planarization layer, but the invention is not limited thereto.

On the other hand, the second insulating layer 150' of the electronic device 10a2 of fig. 2C is illustrated as a single layer structure, as compared to the two-layer structure of the second insulating layer 150 of the electronic device 10a1 of fig. 2B. The second insulating layer 150 'may be an oxide layer, and the material of the second insulating layer 150' may be the same as the lower insulating layer 152 in fig. 2B, but the invention is not limited thereto.

Referring to fig. 2A and 2B, the electronic device 10 may further include a common electrode COM. The common electrode COM is disposed on the active area AA of the substrate 100, for example, and overlaps at least the data line DL1, the gate transfer line 110, the transfer structure 120, and the active device T1 of the pixel structure SP in a plan view direction of the substrate 100. In some embodiments, the common electrode COM may be a common electrode for connecting a panel or implementing a touch function. In some embodiments, in the case that the electronic device further includes a touch signal line (TP trace; not shown), the common electrode COM may also include a plurality of common electrodes, and a gap exists between the plurality of common electrodes COM to expose the touch signal line, so that the common electrodes COM may be applied to implement touch control or other functions. For example, the common electrodes COM may be spaced apart by about 2.0 μm to 8.0 μm with the touch signal line as a center.

The electronic device 10 may also include a third insulating layer 160. The third insulating layer 160 covers the common electrode COM and the second insulating layer 150. In some embodiments, the third insulating layer 160 is sandwiched between the common electrode COM and the pixel electrode PE to separate the common electrode COM from the pixel electrode PE. In some embodiments, the third insulating layer 160 may be a passivation layer (passivation layer), but the invention is not limited thereto.

FIG. 3A is an enlarged schematic view of the crossover region CR of another embodiment in the electronic device of FIG. 1; fig. 3B is a schematic cross-sectional view of the electronic device of fig. 3A along the sectional line a-a'. Fig. 3A corresponds to the crossover region CR of fig. 1. It should be noted that fig. 3A and 3B use the same or similar reference numerals to denote the same or similar elements along with the element numerals and part of the contents of the embodiment of fig. 2A, and the description of the same technical contents is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, which are not repeated herein.

Unlike the aforesaid cross-line region CR of the electronic device 10A in fig. 2A, which is a relay station for signal transmission via the switch structure 120 extending along the first direction D1 as the data line DL1, the cross-line region CR of the electronic device 10B in this embodiment is a relay station for signal transmission via the switch structure 200 extending along the second direction D2 as the gate switch line 110. Referring to fig. 3A, in the electronic device 10B of the present embodiment, the gate via 110 can cross over the data line DL1 through the via structure 200. In the present embodiment, the via structure 200 extends along the second direction D2, and two ends of the via structure 200 are respectively connected to the gate wires 110. Thus, the via structure 200 and the data line DL1 have an intersection in the top view direction of the substrate 100, and the cross-line region CR is formed.

In the present embodiment, the data line DL1 may include a main line segment DLa and a branch line segment DLb. The main line segment DLa extends along the second direction D2 and is located between two adjacent rows of pixel structures SP; the branch line segment DLb extends from the main line segment DLa along the first direction D1 and the second direction D2, and two ends of the branch line segment DLb are connected to the main line segment DLa and the active element T1 of the pixel structure SP, respectively. For example, the branch line segment DLb crosses the adapting structure 200 in the top view direction of the substrate 100. That is, the branch line DLb intersects with the via structure 200, and the gate via 110 crosses the branch line DLb of the data line DL1 through the via structure 200.

Referring to fig. 3A and fig. 3B, in the present embodiment, the via structure 200 is located on the first conductive layer M1, and the main line segment DLa, the branch line segment DLb and the gate via 110 are located on the second conductive layer M2, for example. In this way, the signal of the data line DL1 can be transmitted through the second conductive layer M2, and the gate via 110 at the intersection with the data line DL1 can transmit the signal through the via structure 200 to the first conductive layer M1 and then to the second conductive layer M2 so as to cross over the data line DL 1.

Referring to fig. 3B, the first insulating layer 140 covers the gate line GL and has a plurality of fourth through holes VIA 4. As shown in fig. 3A, the fourth VIAs VIA4 overlap the gate transfer line 110 and expose a portion of the transfer structure 200. In this way, the gate VIA 110 at one end of the VIA structure 200 can be connected to the VIA structure 200 through one of the conductor structures penetrating through the fourth VIA4, so that the signal of the gate VIA 110 jumps from the second conductor layer M2 to the first conductor layer M1. In addition, the VIA structure 200 may be connected to the gate transfer line 110 at the other end of the VIA structure 200 through another conductor structure penetrating through the fourth VIA4, so that the signal of the gate transfer line 110 jumps from the first conductor layer M1 to the second conductor layer M2. That is, the two ends of the VIA structure 200 may be connected to the gate VIA 110 through the conductor structure penetrating through the fourth VIA 4. Therefore, the data line DL1 can be located in the same layer as the gate transfer line 110, and the signal of the gate transfer line 110 can be transmitted to the gate transfer line 110 located at the other end through one end of the via structure 200. In addition, the routing design of the gate patch cord 110 can reduce the number of the turning points, thereby avoiding the problems of increasing the resistance-capacitance load, generating adverse effects caused by coupling between lines, and the like, and further improving the functions executed by the electronic device.

FIG. 4A is a schematic top view of an electronic device according to a second embodiment of the invention; fig. 4B is an enlarged schematic view of the crossover region CR in the electronic device of fig. 4A. Fig. 4B corresponds to the crossover region CR of fig. 4A. It should be noted that fig. 4A and 4B use the same or similar reference numerals to indicate the same or similar elements along with the reference numerals and parts of the contents of the embodiment of fig. 2A, and the description of the same technical contents is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, which are not repeated herein. For convenience of explanation, fig. 4A and 4B omit the positions of the pixel electrodes.

Referring to fig. 4A and 4B, the electronic device 20 of the second embodiment differs from the electronic device 10 of the first embodiment in that the active device T1 of the electronic device 10 is illustrated as a bottom gate structure, the active device T2 of the electronic device 20 is illustrated as a top gate structure, and the data line DL1 is connected to the semiconductor channel layer 310 of the active device T2 through the via structure 300. For example, the active device T2 of the pixel structure SP may include the semiconductor channel layer 310, and in the cross-line region CR, the data line DL1 may cross the gate via 110 through the via structure 300 and the semiconductor channel layer 310.

In the present embodiment, the active element T2 of the pixel structure SP includes, for example: a semiconductor channel layer 310, a data electrode (functioning as a source or a drain), and a gate. The semiconductor channel layer 310 is disposed on the substrate 100. The gate insulating layer covers the semiconductor channel layer 310, and the gate electrode is disposed on the gate insulating layer (for example, the gate insulating layer GI shown in fig. 5B), and overlaps the semiconductor channel layer 310 in the plan view direction of the substrate 100. An interlayer dielectric layer covers the gate electrode and insulates the gate electrode and the data electrode from each other (e.g., interlayer dielectric ILD shown in fig. 5B). The data electrodes (source/drain electrodes) are electrically connected to the semiconductor channel layer 310. The gate of the active device T2 is electrically connected to a corresponding gate line GL, for example, and the gate line GL can be connected to the gate transfer line 110 through the conducting structure CS.

In the present embodiment, in order to transmit signals from the data line DL1 to the semiconductor channel layer 310, the via structure 300 can be disposed between the corresponding data line DL1 and the semiconductor channel layer 310. For example, the via structure 300 may penetrate through an interlayer dielectric layer and a gate insulation layer. That is, the layer of the interposer 300 is located between the layer of the data line DL1 and the layer of the semiconductor channel layer 310.

More specifically, the semiconductor channel layer 310 may include a first segment 312, a bent segment 314 and a second segment 316, the first segment 312 and the second segment 316 extend along the second direction D2, for example, and two ends of the bent segment 314 are adjacent to the first segment 312 and the second segment 316. In the present embodiment, the curved line section 314 is, for example, U-shaped, but the invention is not limited thereto. In other embodiments, the shape of the curved line segment 314 may also be adjusted according to design requirements. In the top view direction of the substrate 100, the first line segment 312 overlaps the data line DL1, for example, and the bent line segment 314 has an intersection with the gate transfer line 110. In addition, an end of the first line segment 312 opposite to the adjacent curved line segment 314 is connected to the transition structure 300, and an end of the second line segment 316 opposite to the adjacent curved line segment 314 is connected to the active element T2. In this way, the signal of the data line DL1 can be transmitted to the first line segment 312 through the switch structure 300, and then transmitted to the active device T2 through the curved line segment 314 and the second line segment 316 in sequence. Therefore, the data line DL1 can be located in the same layer as the gate transfer line 110, and the signal of the data line DL1 can cross the gate transfer line 110 through the via structure 300 and be transmitted to the active device T2 of the pixel structure SP. In addition, the routing design of the gate patch cord 110 can reduce the number of the turning points, thereby avoiding the problems of increasing the resistance-capacitance load and generating adverse effects caused by coupling between lines, and further improving the functions (such as image display, touch sensing, etc.) executed by the electronic device.

FIG. 5A is a schematic top view of an electronic device according to a third embodiment of the invention; fig. 5B is a schematic cross-sectional view of the electronic device of fig. 5A taken along the sectional line a-a'. It should be noted that fig. 5A and 5B use the same or similar reference numerals to indicate the same or similar elements along with the reference numerals and parts of the contents of the embodiments shown in fig. 4A and 4B, and the description of the same technical contents is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, which are not repeated herein. For convenience of explanation, fig. 5A and 5B omit the positions of the pixel electrodes.

Referring to fig. 5A and 5B, compared to the electronic device 20 of fig. 4A, the gate line GL of the electronic device 30 of the embodiment further has an extending structure 320 extending along the second direction D2, the conducting structure CS is disposed at an end of the extending structure 320 far from the gate line GL, that is, the gate via 110 can be connected to an end of the extending structure 320 through the conducting structure CS at an end far from the line crossing region CR, and another end of the extending structure 320 is connected to the gate line GL. In the embodiment, the extension structure 320 is located on the same layer as the gate line GL. For example, as shown in fig. 5B, the buffer layer 102, the gate insulating layer GI, the interlayer dielectric ILD and the gate transfer line 110 may be sequentially disposed on the substrate 100, wherein the extension structure 320 and the gate line GL are disposed on a side of the interlayer dielectric ILD close to the gate insulating layer GI, for example, but the invention is not limited thereto. As shown in fig. 5A, the extension structure 320 extends from the gate line GL along the second direction D2 to the middle area of the pixel structure SP. For example, the length of the extension structure 320 may be about 1/10-1/2 of the length of the pixel structure SP. In some embodiments, the length of the extension structure 320 may correspond to 1/2 of the length of the pixel structure SP, but the present invention is not limited thereto.

In the present embodiment, the gate via 110 can be electrically connected to the gate line GL through the extension structure 320. For example, as shown in fig. 5B, an interlayer dielectric layer ILD may be interposed between the gate transfer line 110 and the gate line GL, the interlayer dielectric layer ILD may have a through hole TH, and a portion of the gate transfer line 110 may cover a surface of the through hole TH to serve as the conducting structure CS, but the invention is not limited thereto. Accordingly, the gate transfer line 110 may be connected to the extension structure 320. In other words, the signal of the gate of the active device T2 can be sequentially transmitted to the extension structure 320 and the gate line GL through the gate switch 110, and then input to the gate through the gate line GL. Thus, the position of the conducting structure CS can be flexibly set, and the conducting structure CS does not have to be set at the intersection of the gate via 110 and the gate line GL. Furthermore, the pattern of the extension structure 320 and the position of the gate via 110 connected to the extension structure 320 can be adjusted according to the process considerations, so as to avoid the problems of loading effect (loading effect) or uneven line width of the lines caused by too close distance between the conducting structures or the conductor structures of different lines.

Fig. 6 is a schematic top view of an electronic device according to a fourth embodiment of the invention. It should be noted that fig. 6 uses the element numbers and part of the contents of the embodiment of fig. 1, wherein the same or similar element numbers are used to indicate the same or similar elements, and the description of the same technical contents is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, which are not repeated herein.

Referring to fig. 6, a difference between the electronic device 40 of the fourth embodiment and the electronic device 10 of the first embodiment is that the electronic device 40 further has an insulating layer covering the data line DL and the gate transfer line 110, and the insulating layer has a trench TR.

In the present embodiment, the trench TR extends along the gate transfer line 110 and the data line DL. The projection of the trench TR on the substrate 100 is located between the projection of the gate transfer line 110 on the substrate 100 and the projection of the data line DL on the substrate 100. For example, the sidewalls of the trench TR are separated from the side surfaces of the gate transfer line 110 and the data line DL, respectively, by a distance, for example, and the lower limit of the distance is preferably 2.0 μm, and preferably 3.0 μm. The upper limit of the distance is preferably 6.0. mu.m, and preferably 5.0. mu.m. In some embodiments, the trenches TR can be spaced about 2 μm to about 6 μm from the gate transfer line 110 and the data line DL, respectively. It should be noted that the embodiment of the trench may be adjusted according to design requirements, and the invention is not limited thereto.

For example, taking the embodiment of fig. 2B as an example, the trench TR may be located within the second insulating layer 150. In some embodiments, the depth of the trench TR may correspond to the film thickness of the upper insulating layer 154. In some embodiments, the trench TR may extend from the upper insulating layer 154 into the lower insulating layer 152. For example, the depth of the trench TR may be greater than the film thickness of the upper insulating layer 154 and less than the film thickness of the lower insulating layer 152. In other embodiments, the depth of the trench TR may be less than the film thickness of the upper insulating layer 154. In addition, taking the embodiment of fig. 2C as an example, the trench TR may be located in the second insulating layer 150'. In some embodiments, the depth of the trench TR may correspond to the film thickness of the second insulating layer 150'. In some embodiments, the trench TR may extend from the second insulating layer 150' into the first insulating layer 140. For example, the depth of the trench TR may be greater than the film thickness of the second insulating layer 150' and less than the film thickness of the first insulating layer 140. In other embodiments, the depth of the trench TR may be less than the film thickness of the second insulating layer 150'.

In some embodiments, the common electrode COM covers the surface of the trench TR. Therefore, it can be used to shield (shielding) the gate adaptor line 110 and the data line DL from interfering with each other, so as to reduce the adverse effect caused by the coupling between the lines. For example, the common electrode COM covers the surface of the groove TR, and the groove TR is located between the gate transfer line 110 and the data line DL, so that the electric field generated by the gate transfer line 110 is shielded and is not coupled to the data line DL, thereby ensuring that the data line DL maintains a certain level of output voltage, and further improving the functions (such as image display, touch sensing, etc.) performed by the electronic device.

In summary, the electronic device of the present invention can make one of the gate transfer line and the data line cross over the other of the gate transfer line and the data line through the active device of the transfer structure or the pixel structure in the cross-line region by providing the transfer structure. Therefore, the problems of increasing resistance-capacitance load, generating adverse effects caused by coupling between circuits and the like can be avoided, and functions (such as picture display, touch sensing and the like) executed by the electronic device can be further improved.

Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.

Claims

1. An electronic device, comprising:

substrate;

a plurality of gate lines disposed on the substrate and extending along the first direction;

a plurality of data lines disposed on the substrate and extending along a second direction, wherein the first direction intersects the second direction;

a plurality of pixel structures arranged in an array on the substrate, each of the pixel structures is surrounded by adjacent two of the plurality of gate lines and adjacent two of the plurality of data lines and includes active elements, wherein the plurality of pixel structures arranged in the same row along the second direction are electrically connected to the data lines on different sides in sequence;

a gate transfer wire, disposed on the substrate and extending along the second direction, the gate transfer wire is electrically connected to one of the plurality of gate wires, and the gate transfer wire is located on the The film layer is the same as the film layer where the plurality of data lines are located, and in the top view of the electronic device, the gate wiring line passes through one of the plurality of pixel structures and is electrically connected to the pixel structure A jumper area is formed on the substrate between the connected data lines; and

The transfer structure is disposed on the substrate, and the film layer where the transfer structure is located is different from the film layer where the gate transfer line and the data line are located, and in the cross-line area, the gate One of the pole transfer line and the data line crosses the other of the gate transfer line and the data line through the transfer structure or the active element of the pixel structure.

2. The electronic device according to claim 1, wherein in the jumper region, the data line crosses the gate jumper line through the jumper structure,

The transfer structure extends along the first direction, two ends of the transfer structure are respectively connected to the data line and the active element of the pixel structure, and in a top view of the electronic device, the The transfer structure intersects with the gate transfer line.

3. The electronic device of claim 2, wherein the active element of the pixel structure further comprises:

A vertical wire is arranged on the substrate, two ends of the vertical wire are connected to the switching structure and the active element, and in the top view of the electronic device, the gate switching wire is located on the data line and the longitudinal wire.

4. The electronic device of claim 3, further comprising:

A first insulating layer covers the gate line and has a first through hole and a second through hole. In the top view of the electronic device, the first through hole overlaps with the data line, and the second through hole overlaps with the data line. The through hole overlaps with the vertical wire, wherein the first through hole and the second through hole respectively expose a part of the transfer structure, and the data line is connected to the transfer structure through the first through hole The connecting structure is connected to the longitudinal wire through the second through hole.

5 . The electronic device of claim 2 , wherein the pixel structure further has a pixel electrode, and the pixel electrode and the data line are respectively electrically connected to the drain and the source on opposite sides of the active element. 6 . extremely, and

In a top view of the electronic device, the pixel electrode is separated from the gate wiring by a distance.

6. The electronic device of claim 5, further comprising:

A second insulating layer covers the data line and the gate transition line, and has a third through hole, wherein the third through hole exposes a part of the active element, and the pixel electrode covers the third through hole part of the surface of the through hole to connect to the active element.

7. The electronic device of claim 6, wherein the second insulating layer comprises a lower insulating layer and an upper insulating layer, the lower insulating layer is conformally disposed on the first insulating layer, the upper insulating layer A layer is disposed on the lower insulating layer.

8. The electronic device of claim 6, wherein the second insulating layer is a single-layer structure.

9. The electronic device of claim 1, wherein in the jumper region, the gate jumper line spans the data line through the jumper structure,

The transfer structure extends along the second direction, two ends of the transfer structure are respectively connected to the gate transfer line, and in the top view of the electronic device, the transfer structure and the data line intersect.

10. The electronic device of claim 9, wherein the data line has a main line segment and a branch line segment, the main line segment extends along the second direction, and two ends of the branch line segment are respectively connected to the main line segment and the branch line segment The active element of the pixel structure, and in the top view of the electronic device, the transfer structure intersects the branch line segment.

11. The electronic device of claim 10, further comprising:

a first insulating layer, covering the gate line, and having a plurality of fourth through holes, in a plan view of the electronic device, the plurality of fourth through holes overlap with the gate wiring, wherein the A plurality of fourth through holes expose a part of the transfer structure, and the gate jumper line located at one end of the transfer structure is connected to the transfer through one of the plurality of fourth through holes structure, the transfer structure is connected to the gate transfer line at the other end of the transfer structure through the other one of the plurality of fourth through holes.

12. The electronic device of claim 2 or claim 9, further comprising:

The common electrode is disposed on the substrate and overlaps with at least the data line, the gate transfer line and the transfer structure in a plan view of the electronic device.

13. The electronic device of claim 1, wherein the active element of the pixel structure is a top-gate thin film transistor and includes a semiconductor channel layer, and in the cross-line region, the data line passes through the A via structure and the semiconductor channel layer span the gate via.

14. The electronic device of claim 13, wherein the semiconductor channel layer comprises a first line segment, a curved line segment and a second line segment, the first line segment and the second line segment extending along the second direction , both ends of the curved line segment are adjacent to the first line segment and the second line segment,

In a top view of the electronic device, the first line segment overlaps the data line, and the curved line segment intersects the gate transition line.

15 . The electronic device of claim 13 , wherein the gate line further comprises an extension structure, the extension structure extends from the gate line along the second direction, and the gate patch line passes through the extension. 16 . the structure is electrically connected to the gate line,

The length of the extension structure is 1/10˜1/2 of the length of the pixel structure.

16. The electronic device of claim 15, further comprising:

an interlayer dielectric layer sandwiched between the gate wire and the gate wire and having through holes, wherein the gate wire covers the surface of the through holes to connect to the extension structure .

17. The electronic device of claim 1, further comprising:

A third insulating layer covers the data line and the gate transition line, the third insulating layer has a groove, the groove extends along the second direction, and in the top view of the electronic device, The trench is located between the data line and the gate transition line.