KR100543037B1 - Planar drive type liquid crystal display device and manufacturing method thereof - Google Patents

Abstract

A gate pattern including a double gate line parallel to each other in a horizontal direction and connected through a gate connection line and a gate electrode that is part of a first gate line is formed on the transparent insulating substrate. On the gate insulating film covering the gate pattern, a first data line defining a pixel region crossing the double gate line, a data pattern including a source electrode and a drain electrode, a first common electrode line overlapping the first gate line, and a first common line A common pattern including a plurality of common electrodes connected to each other and vertically parallel to each other through an electrode line, and alternately with a first pixel electrode line and a common electrode overlapping a second gate line of a neighboring pixel region and connected to a drain electrode. A pixel pattern including pixel electrodes formed in parallel and connected to each other through a first pixel electrode line is formed. In the passivation layer covering the common pattern, the pixel pattern, and the data pattern, first, second, and third contact holes exposing a part of the first data line, the common electrode, and the end of the pixel electrode are formed. On the passivation layer, a second pixel connected to the first data line and the first common electrode line connected to the first data line through the first contact hole in the same shape as the first data line, and connected to the pixel electrode through the third contact hole. A second common electrode line overlapping the electrode line and the first pixel electrode line and connected to the common electrode through the second contact hole is formed.

Description

Planar drive type liquid crystal display device, thin film transistor substrate thereof and manufacturing method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device and a manufacturing method thereof, and more particularly, to a liquid crystal display device of a planar driving method and a manufacturing method thereof.

As a liquid crystal display device mainly used to improve the optical viewing angle, an in-plane switching (IPS) type liquid crystal display device that applies an electric field parallel to a substrate has been developed.

Next, the structure of the planar driving liquid crystal display according to the related art will be described in detail with reference to the accompanying drawings.

1 is a layout view illustrating a structure of a thin film transistor substrate for a planar driving liquid crystal display device according to the related art.

As shown in FIG. 1, a gate pattern formed of the gate electrode 20 and a portion of the gate line 20 in the horizontal direction is formed. A common pattern including a common electrode line 10 parallel to the gate line 20 and a plurality of common electrodes 11 connected to the common electrode line 10 and formed in the vertical direction in parallel to each other is formed. A drain facing the source electrode 61 centering on the data line 60 crossing the gate line 20 and defining the pixel region, the source electrode 61 which is a branch of the data line 60, and the gate electrode 21. The date pattern which consists of electrodes 62 is formed. A pixel electrode 91 connected to the drain electrode 62 and overlapping the common electrode line 10 and a pixel electrode line 90 connected to the pixel electrode line 90 and formed between the plurality of common electrodes 11. The pixel pattern which consists of these is formed. The semiconductor layer 40 serving as the channel layer of the thin film transistor is formed at the portion where the gate electrode 21 and the source / drain electrodes 61 and 62 overlap.

However, in the structure of the thin film transistor substrate for a conventional liquid crystal display device, since the gate patterns 20 and 21 and the common patterns 10 and 11 are formed on the same layer, the aperture ratio decreases, thereby decreasing the transmittance. This happens.

An object of the present invention is to solve such a problem, and to improve the aperture ratio of a liquid crystal display device.

In the planar drive type thin film transistor substrate for a liquid crystal display device and a method of manufacturing the same according to the present invention for solving the above problems, a gate line and a common electrode line are formed in different layers on a transparent insulating substrate, and are formed so as to overlap them.

More specifically, a gate pattern including a horizontal gate line and a gate electrode that is a part of the gate line is formed on a transparent insulating substrate, and a gate insulating film covering the gate pattern is formed. Forming a data pattern on the gate insulating layer, the data pattern including a first data line in a vertical direction defining a pixel region intersecting the gate line, a source electrode that is a part of the first data line, and a drain electrode facing the source electrode, centering on the gate electrode; A common pattern is formed in the pixel area including a plurality of vertical common electrodes and a first common electrode line connecting the plurality of vertical common electrodes and overlapping the gate lines. In addition, a pixel pattern including a plurality of pixel electrodes that are alternately parallel to a plurality of common electrodes and a vertical first pixel electrode line connected to the drain electrode is formed on the gate insulating layer. In this case, one of the plurality of common electrodes extends to connect with the common electrodes of neighboring pixels. Subsequently, a passivation layer may be formed to cover the data pattern, the pixel pattern, and the common pattern, and the passivation layer may be patterned to form first and second contact holes on the top of the pixel electrode and the common electrode, and the first common electrode line may be disposed on the passivation layer. A second common electrode line overlapping the second pixel electrode line connecting the plurality of pixel electrodes and the first pixel electrode line and connecting the plurality of common electrodes is formed.

Here, when the extended common electrode and the first pixel electrode line intersect, the first pixel electrode line or the common electrode may be separated, and the common electrode positioned at the edge of the pixel area may be extended.

In addition, in order to prevent disconnection of the gate line and the data line, the gate line may be doubled in parallel so that the data lines overlap each other.

In this case, it is preferable that a third contact hole is formed in the passivation layer and the gate insulating layer or the passivation layer is formed of silicon nitride, silicon oxide, or an organic insulation layer to connect the dual data lines to each other.

In the method of manufacturing the planar drive type thin film transistor substrate for a liquid crystal display device according to the present invention, the aperture ratio is improved by forming the common electrode line and the gate line to overlap each other.

Next, embodiments of the planar driving liquid crystal display and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

First, a structure of a thin film transistor substrate for a flat panel liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 2 and 3.

FIG. 2 is a layout view of a liquid crystal display of a planar driving method according to an exemplary embodiment of the present invention, and FIG. 3 is a cross-sectional view taken along line III-III of FIG. 2.

As shown in FIG. 2 and FIG. 3, the gate electrodes 210, which are part of the double gate lines 200 and 220 and the first gate line 200, which are parallel to each other in the horizontal direction, are disposed on the lower transparent insulating substrate 100. A gate pattern is formed. Here, the double gate lines 200 and 220 are connected through the gate connection line 230 formed in the vertical direction.

The gate insulating layer 300 made of silicon nitride, silicon oxide, or an organic insulating layer is covered on the gate patterns 200, 210, and 220.

The semiconductor layer 400 of the thin film transistor made of amorphous silicon is formed in an island shape on the gate insulating layer 300 on the gate electrode 210, and is heavily doped with phosphorus (P) on the amorphous silicon layer 400. Resistive contact layers 510 and 520 made of silicon are formed on both sides of the gate electrode 210.

Located on the ohmic contact layers 510 and 520, respectively, and connected to the source electrode 610, the drain electrode 620, and the source electrode 610 made of metal, and positioned on the gate insulating layer 300. A data pattern including the first data line 600 in the vertical direction defining the pixel area P is formed to cross the 220. The plurality of common electrodes 660 connected to each other and vertically connected to each other through the first common electrode line 650 and the first common electrode line 650 overlapping the first gate line 200 on the gate insulating layer 300. A common pattern comprising 670 is formed. In this case, the common electrode 670 passing through the center of the pixel region P extends in the vertical direction and is connected to the common electrode 670 of the neighboring pixel region P. FIG. In addition, the first pixel electrode line 630 and the common electrode 660 overlapping the second gate line 220 passing through the neighboring pixel region P and connected to the drain electrode 620 are disposed on the gate insulating layer 300. A pixel pattern including pixel electrodes 640 that are alternately formed in parallel with 670 and connected to each other through the first pixel electrode line 630 is formed. In this case, the first pixel electrode line 630 is disconnected from the portion where the common electrode 670 passes, and is separated into two portions 631 and 632.

The gate electrode 210, the gate insulating layer 300, the amorphous silicon layer 400, the ohmic contact layers 510 and 520, the source and drain electrodes 610 and 620 form a thin film transistor, and the thin film transistor and the remaining data patterns. A protective film 700 covering the 600, 610, and 620, the common patterns 650, 660, and 670, and the pixel patterns 630 and 640 is formed of silicon oxide, silicon nitride, an organic insulating film, or the like.

In the passivation layer 700, first, second, and third contact holes 710, 720, and 730 exposing a part of the first data line 600, the common electrode 660, and the end of the pixel electrode 640 are formed. Formed.

On the passivation layer 700, a second data line 800 is formed along the first data line 600 in the same shape as the first data line 600, and the second data line 800 has a first contact hole ( It is connected to the first data line 600 through 710. In addition, a second pixel electrode line 810 overlapping the first common electrode line 650 and connected to the pixel electrode 640 through the third contact hole 730 is formed on the passivation layer 700. A second common electrode line 820 overlapping the first pixel electrode line 630 and connected to the common electrode 660 through the second contact hole 720 is formed.

In the thin film transistor substrate for a flat panel liquid crystal display device according to the present invention, the gate lines 200 and 220 and the first and second common electrode lines 650 and 820 are interposed between the gate insulating film 300 or the passivation layer 700. It is formed in another layer so as to be able to be formed so as to overlap as shown in FIG. Therefore, the length of the opening in the vertical direction is increased in the pixel region P, thereby improving the opening ratio.

Next, a method of manufacturing a thin film transistor substrate for a flat panel liquid crystal display device according to the present invention shown in FIGS. 2 and 3 will be described in detail with reference to the accompanying drawings.

4A, 4B, 5A, 5B, 6A, and 6B illustrate a method of manufacturing a thin film transistor substrate for a planar driving liquid crystal display device according to the present invention, according to a process sequence. 5A and 6A are layout views illustrating the structure of a thin film transistor substrate, and FIGS. 4B, 5B, and 6B are cross-sectional views taken along lines IVa, Va, and VIa in FIGS. 4A, 5A, and 6A.

First, as shown in FIGS. 4A and 4B, a metal layer is deposited and patterned on a transparent insulating substrate 100 such as glass to form a double first and second gate lines 200 and 220, a gate electrode 210, The gate connection line 230 is formed. In this case, various conductive materials may be used as the gate wiring metal, and the gate wiring may be formed by using a chromium, aluminum, aluminum alloy, molybdenum, or the like, or a combination of these metals. It can be formed by wiring.

Next, an insulating gate insulating film 300 such as silicon oxide, silicon nitride or an organic insulating film, an amorphous silicon layer 400, and an amorphous silicon layer 500 doped with high concentration of impurities such as phosphorus are sequentially deposited on the entire surface of the substrate 100. The doped amorphous silicon layer 500 and the amorphous silicon layer 400 are patterned together to form an island shape on the gate electrode 210.

Subsequently, as shown in FIGS. 5A and 5B, a metal layer such as chromium, an aluminum alloy, or molybdenum is deposited and patterned using a mask to cross first and second gate lines 200 and 220. Data pattern including line 600 and source and drain electrodes 610 and 620, Common pattern including first common electrode line 650 and common electrodes 660 and 670, and first pixel electrode line 630 and pixel A pixel pattern including the electrode 640 is formed. Next, the amorphous silicon layer 500 doped with the source electrode 610 and the drain electrode 620 as a mask is etched to separate the doped amorphous silicon layer 500 into both the gate electrodes 210 to form a resistance contact layer 510. 520). Here, although the common patterns 650, 660, and 670 formed in neighboring pixel regions are connected to each other through the common electrode 670, the common patterns 650, 660, and 670 may be connected to each other through the common electrode. When the common patterns are connected to each other through the common electrode, the pixel electrode line 630 may not be separated into two parts 631 and 632.

6A and 6B, the passivation layer 700 is formed of silicon oxide, silicon nitride, or an organic insulating layer on the entire surface of the substrate 100, and patterned using a mask to form part of the first data line 600 and a common electrode. First, second and third contact holes 710, 720, and 730 exposing 660 and the pixel electrode 640 are formed, respectively.

Finally, as shown in FIGS. 1 and 2, a single film or a plurality of films of molybdenum, molybdenum alloy, or aluminum alloy is deposited and patterned using a mask to form a second, similar in shape to the first data line 600. The plurality of common electrodes 660 are overlapped with the second pixel electrode line 810 and the first pixel electrode line 630 connected to the data line 800 and the first common electrode line 650 and connected to the pixel electrode 640. A second common electrode line 820 is formed to connect.

The second data line 800, the second common electrode line 820, and the second pixel electrode line 810 may be formed of ITO by using indium tin oxide (ITO) or under another metal layer.

As in the embodiment of the present invention, disconnection of the wiring can be prevented by forming the first and second data lines, and the aperture ratio can be improved by forming the gate line and the common electrode line so as to overlap each other.

1 is a layout view illustrating a structure of a thin film transistor substrate for a flat panel liquid crystal display device according to the related art.

2 is a layout view illustrating a structure of a thin film transistor substrate for a flat panel liquid crystal display device according to the present invention;

3 is a cross-sectional view taken along the line III-III of FIG. 2,

4A, 4B, 5A, 5B, 6A, and 6B are diagrams illustrating a method of manufacturing a thin film transistor substrate for a planar liquid crystal display device according to the present invention according to a process sequence thereof.

Claims (19)

A plurality of gate lines formed parallel to each other on a transparent substrate, A plurality of data lines insulated from each other with the gate line and the first insulating layer interposed therebetween and defining a pixel area crossing the gate line; A plurality of common electrodes formed parallel to each other in the pixel region; A first common electrode line connecting the plurality of common electrodes in the pixel area and insulated from the gate line and overlapping the gate line; A plurality of pixel electrodes formed to face the common electrode at predetermined intervals in the pixel area; Flat drive type liquid crystal display device comprising a. In claim 1, And a thin film transistor including a gate electrode, a source electrode, and a drain electrode connected to the gate line, the data line, and the pixel electrode, respectively. In claim 1, And the data line and the first common electrode line are formed on the same layer. In claim 1, And the pixel electrode and the common electrode are formed on the same layer. In claim 2, And a first pixel electrode line connected to the drain electrode and connecting the plurality of pixel electrodes. In claim 5, And a second common electrode line overlapping the first pixel electrode line and the second insulating layer, and connected to the plurality of common electrodes. In claim 6, And a second pixel electrode line overlapping the first common electrode line and the second insulating layer, and connecting the plurality of pixel electrodes. Transparent insulation substrate, A gate pattern including a plurality of first gate lines formed on the insulating substrate in a vertical direction and a gate electrode that is a part of the first gate lines; A gate insulating layer formed on the insulating substrate and covering the gate pattern; A semiconductor layer formed on the gate insulating film of the gate electrode and made of amorphous silicon, A first data line formed on the gate insulating layer and crossing the gate line and the first gate line to define a pixel region, the first data line connected to the semiconductor layer, and a source electrode which is a part of the first data line, and the semiconductor layer; A data pattern including a drain electrode facing the source electrode with respect to a gate electrode; A common pattern formed on the gate insulating layer, the common pattern including a plurality of common electrodes formed in parallel to each other in the pixel area, and a plurality of common electrodes overlapping the gate lines; A first pixel electrode line formed on the gate insulating layer and connecting the plurality of pixel electrodes facing the common electrode at a predetermined interval in the pixel region and the plurality of pixel electrodes; A thin film transistor substrate for a liquid crystal display device of a planar driving method including a pixel pattern including a. In claim 8, A passivation layer formed on the gate insulating layer to cover the data pattern, the common pattern, and the pixel pattern, the passivation layer having first and second contact holes in portions corresponding to ends of the pixel electrode and the common electrode; A second pixel electrode line formed on the passivation layer and overlapping the first common electrode line and connecting the plurality of pixel electrodes through the first contact hole; and And a second common electrode line formed on the passivation layer and overlapping the first pixel electrode line and connecting the plurality of common electrodes through the second contact hole. In claim 9, And a second data line overlapping the first data line on the passivation layer and connected to the first data line through a third contact hole formed in the passivation layer. Method for manufacturing a thin film transistor substrate for a device. In claim 8, And a second gate line formed on the substrate in parallel with the first gate line and connected to the first gate line through a gate connection line. In claim 11, And the second gate line and the first pixel electrode line overlap each other with the gate insulating layer interposed therebetween. In claim 8, And a resistive contact layer formed between the source and drain electrodes and the semiconductor layer. In claim 8, The gate insulating film and the passivation film may be formed of silicon nitride, silicon oxide, or an organic insulating film. In claim 8, And one of the plurality of common electrodes is connected to the common electrode of the neighboring pixel region. Forming a gate pattern including a first gate line and a gate electrode on the substrate; Forming a gate insulating film covering the gate pattern; Forming a semiconductor layer and an ohmic contact layer on the gate insulating layer; Forming a common pattern including a data pattern including a first data line, a source and a drain electrode, a common pattern including a common electrode and a first common electrode line overlapping the first gate line, and a pixel pattern including a pixel electrode and a first pixel electrode line step, Depositing a passivation layer on the data pattern, the common pattern, and the pixel pattern; Forming first and second contact holes in the passivation layer to expose ends of the common electrode and the pixel electrode, respectively; Forming a second common electrode line connected to the common electrode through the first contact hole and a second pixel electrode line connected to the pixel electrode through the second contact hole on the passivation layer; The board | substrate manufacturing method for liquid crystal display devices of this. The method of claim 16, The method of claim 1, wherein the forming of the gate pattern further comprises forming a second gate line parallel to the first gate line and a gate connection line connecting the first and second gate lines. The method of claim 16, Forming a third contact hole exposing the first data line in the forming of the first and second contact holes in the passivation layer, And forming a second data line connected to the first data line through the third contact hole in the step of forming the second common electrode line and the pixel electrode line. The method of claim 16, And the gate insulating film and the protective film are formed of silicon nitride, silicon oxide, or an organic insulating film.