CN101561609A - Active array substrate, liquid crystal display panel and method for manufacturing active array substrate - Google Patents

Abstract

An active array substrate, a liquid crystal display panel and a method for manufacturing the active array substrate are provided. The active array substrate comprises a substrate, a plurality of scanning lines, a plurality of data lines and a plurality of grid transfer lines, wherein the grid transfer lines are arranged on the substrate and are provided with a plurality of first parts; a plurality of wire-turning parts are connected with the corresponding first parts; a plurality of connecting holes; and a plurality of second portions disposed in different layers from the first portions, wherein one of the second portions is electrically connected to the corresponding first portion through one of the connection holes.

Description

Active array substrate, liquid crystal display panel and method for manufacturing active array substrate

technical field

The present invention relates to an active array substrate, a liquid crystal display panel and a method for manufacturing the active array substrate, in particular to a narrow-frame active array substrate with uniform imaging, a liquid crystal display panel, and a narrow-frame active array substrate with uniform imaging Manufacturing method.

Background technique

Flat Panel Display (FPD) is currently the main popular display, among which LCD panels are widely used in computer screens, mobile phones, personal digital assistants (PDAs) because of their thin and light appearance, power saving and no radiation. ), flat-screen TVs and other electronic products. The working principle of the liquid crystal display panel is to change the alignment state of the liquid crystal molecules in the liquid crystal layer by changing the voltage difference between the two ends of the liquid crystal layer to change the light transmittance of the liquid crystal layer, and then cooperate with the light source provided by the backlight module to display images.

FIG. 1 is a schematic diagram of a known liquid crystal display panel. As shown in FIG. 1 , the liquid crystal display panel 100 includes an active array substrate 110 and an opposite substrate 190 , and a liquid crystal layer (not shown) is sandwiched between the active array substrate 110 and the opposite substrate 190 . The opposite substrate 190 can be a color filter. The active array substrate 110 includes a plurality of data lines 130 , a plurality of gate lines 150 , a plurality of auxiliary gate lines 155 , a first frame area 180 , a second frame area 185 , an image display area 195 and a driving module 101 . A plurality of data lines 130 and a plurality of gate lines 150 are disposed in the image display area 195 . A plurality of auxiliary gate lines 155 are disposed in the first frame area 180 and the second frame area 185 . The driving module 101 is electrically connected to a plurality of auxiliary gate lines 155 for feeding the provided plurality of gate signals to the plurality of gate lines 150 through the plurality of auxiliary gate lines 155 . The driving module 101 is also electrically connected to a plurality of data lines 130 for feeding the provided data signals to a plurality of pixel units (not shown) through the plurality of data lines 130 . The liquid crystal display panel 100 controls multiple data signals to be written into multiple pixel units according to multiple gate signals for displaying images.

Since in the structure of the known active array substrate 110, the number of auxiliary gate lines 155 is substantially equal to the number of gate lines 150, the active array substrate 110 needs to provide a sufficiently wide first frame area 180 and a second frame area. 185, for setting a plurality of auxiliary gate lines 155. However, since most of the displays installed in portable electronic devices are small liquid crystal display panels, how to reduce the area of the frame area to reduce the size of the lower substrate is an important issue in designing small liquid crystal display panels.

The active array substrate 110 is mainly composed of multiple conductive layers and insulating layers. The gate lines 150, gate lines and common lines (not shown) are formed by the same metal layer (generally referred to as the first metal layer). Composition. The data line 130 is formed by another metal layer (generally referred to as the second metal layer), and the pixel electrode (not shown) is formed by a transparent conductive layer. In terms of circuit layout, whether it is due to design or under some unavoidable factors, the horizontal (or vertical) distance between the conductive layers will be too close, so that the signals between each other will affect each other, resulting in a loading effect. When the loading effect is not uniformly generated on each pixel, the effect on each pixel will not be consistent, and the uneven loading effect will seriously affect the display quality. Therefore, in the design of the display device, the uneven loading effect should be avoided as much as possible.

Contents of the invention

In view of the foregoing, an object of the present invention is to provide an active array substrate.

Based on the above purpose, the present invention provides an active array substrate, including a substrate; a plurality of scanning lines arranged on the substrate; a plurality of data lines arranged on the substrate and roughly connected to the scanning lines vertical; and a plurality of gate tracking lines (gate tracking lines), arranged on the substrate, wherein each of the gate tracking lines is electrically connected to a corresponding gate line, and each of the gate tracking lines It is generally arranged in parallel with the data lines, wherein each of the gate transfer lines has: a plurality of first parts; a plurality of transfer parts connected to the corresponding first parts; a plurality of connection holes; and a plurality of A connection part is configured in a different layer from the first parts, wherein one of the connection parts is electrically connected to the corresponding first part through one of the connection holes.

The active array substrate provided by the present invention further includes: a plurality of switching elements, each of which is electrically connected to the corresponding data line and the corresponding scanning line; a plurality of pixel electrodes, each of which is connected to the corresponding The switching elements are electrically connected; and a plurality of common lines are arranged on the substrate, generally parallel to the scanning lines, and form a storage capacitor with a drain of the corresponding switching elements.

Each of the gate transfer lines of the active array substrate provided by the present invention further has an auxiliary insulating layer located between the first portions and one of the data lines.

Each of the gate transfer lines of the active array substrate provided by the present invention further has an auxiliary semiconductor layer located between the auxiliary insulating layer and the data lines.

Based on the above purpose, the present invention provides a method for manufacturing an active array substrate, comprising: providing a substrate; forming a first conductive layer on the substrate; patterning the first conductive layer to form a plurality of scanning lines , a plurality of gates, a plurality of first parts, and a transfer line part connected to the corresponding first parts; forming a gate insulating layer on the scanning lines, gates and first parts; forming a semiconductor layer on the gate insulating layer; patterning the semiconductor layer to form a plurality of channel layers above the corresponding gates; patterning the gate insulating layer to form a connection hole to expose the The transfer part; forming a second conductive layer on the semiconductor layer; patterning the second conductive layer to form a plurality of data lines, a plurality of source electrodes and drain electrodes, and a plurality of connection parts, wherein each The connection part is electrically connected to the corresponding transition part through the connection hole; a protective layer is formed on the entire surface; the protective layer is patterned to form a contact hole to expose the drain electrode; and a pixel electrode is formed on the The protective layer is electrically connected to the drain through the contact hole.

Based on the above purpose, the present invention provides a liquid crystal display panel, comprising the above-mentioned active array substrate, an opposite substrate, and a liquid crystal layer, located between the active array substrate and the opposite substrate.

The invention provides an active array substrate with a narrow frame or no frame and a manufacturing method thereof.

The invention provides an active array substrate with low load effect and a manufacturing method thereof.

According to the technical solution provided by the present invention, the generation of uneven load effect can be avoided, thereby improving the display quality.

Description of drawings

1 is a schematic diagram of a known liquid crystal display panel;

2A to 2G are flowcharts of a method for manufacturing an active array substrate according to a first embodiment of the present invention;

FIG. 3 is an active array substrate according to a second embodiment of the present invention;

FIG. 4 is an active array substrate according to a third embodiment of the present invention; and

FIG. 5 is a liquid crystal display panel of the present invention.

Reference number

1LCD display panel

100 LCD display panel

101 drive module

110 active array substrate

130 data line

150 grid lines

155 auxiliary grid lines

180 first border area

185 second border area

190 opposite substrate

195 image display area

200 LCD display panel

211 substrate

221 grid

240 auxiliary insulating layer

241 gate insulating layer

242 first protective layer

246 second protective layer

250 scan lines

252 Part 1

254 Transfer Department

256 connection part

260 pixel electrodes

270 shared line

272 capacitor lower electrode

281 channel layer

282 auxiliary semiconductor layer

290 data line

292 source

294 drain

296 capacitor upper electrode

300 liquid crystal layer

400 opposite substrate

H1, H2 connection hole

H3 contact hole

Detailed ways

In order to make the above and other objects, features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

For the descriptions of the following embodiments, reference may also be made to Taiwan Patent Application No. 98100467, the contents of which are included in the scope of the present invention for reference.

first embodiment

2A to 2G are flowcharts of a method for manufacturing an active array substrate according to a first embodiment of the present invention.

Please refer to FIG. 2A , first provide a substrate 211, form a first conductive layer (not shown) on the substrate 211, and then pattern the first conductive layer to form scanning lines 250, 250a, gates 221, 221a, and a common line 270 , the capacitor bottom electrode 272 , the first part 252 and the transfer line part 254 . The way of patterning the first conductive layer can be known methods such as exposure, development and etching, for example. The wire transfer part 254 is connected to the first part 252. For a pixel unit, both ends of the first part 252 can be respectively connected to a wire transfer part 254, that is, the first part 252 and the two wire transfer parts 254 can be roughly Constitute a reverse C-shaped or I-shaped, but not limited to this. The capacitor bottom electrode 272 is connected to the common line 270 .

Please refer to the sectional view corresponding to the sectional lines A-A' and B-B' in FIG. 2A. Referring to the sectional view of the section line A-A', the gate 221 corresponds to the switch element in the pixel unit, such as a thin film transistor, and the capacitor bottom electrode 272 corresponds to the storage capacitor. For the cross-sectional view of the section line BB', the first part 252 and the transfer part 254 are part of the gate transfer line (not marked), if the gate transfer line corresponding to the pixel unit is designed to be connected to the thin film transistor The gate 221a is connected to the corresponding scan line 250a, and the gate 221a is connected with the first part 252 or the transfer line part 254 in the step of patterning the first conductive layer, as shown in FIG. 2A .

2B, the auxiliary insulating layer 240 is formed on the first part 252, and can cover part of the scanning line 250, the common line 270 and/or the transfer line part 254. For example, the auxiliary insulating layer 240 can completely cover the first part. In a part 252 , the material of the auxiliary insulating layer 240 is, for example, an inorganic material or an organic material, and the inorganic material is, for example, silicon nitride or silicon oxide.

Please refer to FIG. 2C, a gate insulating layer 241 is formed in an all-round way to cover all the above-mentioned elements, and then a semiconductor layer (not shown) is formed on the gate insulating layer 241, and then the semiconductor layer is patterned to form a channel layer 281 and an auxiliary semiconductor layer. 282. The way of patterning the semiconductor layer can be, for example, known methods such as exposure, development and etching. It should be noted that the channel layer 281 is located above the gate 221 to form a part of the thin film transistor, and the auxiliary semiconductor layer 282 is located above the first portion 252 and the auxiliary insulating layer 240 and forms a part of the gate connection.

Next please refer to FIG. 2D , the patterned gate insulating layer 241 makes connection holes H1 and H2 formed above the transfer line portion 254 , as shown in FIG. 2D , for a single pixel unit, the gate insulation layer above the two transfer line portions 254 The layer 241 respectively has connection holes H1 and H2 to respectively expose the two transition line portions 254 .

Referring to FIG. 2E , a second conductive layer (not shown) is formed on the above elements, and the second conductive layer is patterned to form data lines 290 , source electrodes 292 , drain electrodes 294 , capacitor upper electrodes 296 and connection portions 256 . The connection holes H1 or H2 do not overlap with the data lines 290 . The method of patterning the second conductive layer may be known methods such as exposure, development and etching, for example. It should be noted that the data line 290 is substantially perpendicular to the common line 270 and the scanning line 250, and the connection portion 256 is located above the transfer portion 254 and is electrically connected to the transfer portion 254 through the connection holes H1 and H2. Therefore, the single connection portion 256 It is electrically connected with the transfer portion 254 of two adjacent pixel units, and in this way, the gate transfer wiring is completed. The single gate transfer line includes a plurality of first portions 252 , a plurality of transfer portions 254 and a plurality of connection portions 256 , and more optionally includes an auxiliary insulating layer 240 and/or (multiple) auxiliary semiconductor layers 282 .

Referring to FIG. 2F , the first protective layer 242 and the second protective layer 246 are formed to cover the above components, and then the first protective layer 242 and the second protective layer 246 are patterned to form a contact hole H3 to expose the drain 294, The first protection layer 242 and the second protection layer 246 can be selectively formed, and it is not limited here. The materials of the first protection layer 242 and the second protection layer 246 can be organic materials or non-organic insulating materials.

Finally, referring to FIG. 2G , a pixel electrode 260 is formed corresponding to each pixel unit. To complete the active array substrate of this embodiment, the material of the pixel electrode 260 can be reflective conductive metal or transparent conductive metal oxide. The active array substrate includes a substrate 211 , a plurality of scan lines 250 , a plurality of common lines 270 , a plurality of data lines 290 , a plurality of gate transfer lines, a plurality of switching elements and a plurality of pixel electrodes 260 . Each gate transfer wire has a plurality of first portions 252 , a plurality of transfer wire portions 254 , a plurality of connection holes H1 , H2 and a plurality of connection portions 256 . A plurality of connection portions 256 are formed in different layers from the first portions 252, wherein one of the connection portions 256 is connected to the corresponding first portion through one of the connection holes H1, H2. 252 electrical connections. A part of the first portions 252 overlaps with one of the data lines 290 . The connection portions 256 are of the same layer as the data lines 290 . Each of the gate transfer lines further has an auxiliary insulating layer 240 located between the first portions 252 and one of the data lines 290, and the gate transfer lines further have an auxiliary semiconductor layer 282 located between the auxiliary insulating layers. layer 240 and the data line 290 . The connection holes H1 , H2 do not overlap 290 the data lines 290 . Each of the switching elements is electrically connected to the corresponding data line 290 and the scanning line 250, each of the pixel electrodes 260 is electrically connected to the drain 294 of the corresponding switching element, and the common line 270 is generally connected to the corresponding These scan lines 250 are parallel to each other and form storage capacitors with corresponding capacitor upper electrodes 296 .

It should be particularly noted that due to the provision of the auxiliary insulating layer 240 and the auxiliary semiconductor layer 282, the loading effect between the first portion 252 and the data line 290 can be reduced, and the first portion 252 is generally shielded by the data line 290 to avoid The problem of lower aperture ratio. And because of the arrangement of the gate transfer wires, the arrangement of the auxiliary gate lines 155 in the first frame region 180 and/or the second frame region 185 can be reduced or omitted, so as to achieve the goal of narrow frame or no frame.

second embodiment

FIG. 3 is an active array substrate according to a second embodiment of the present invention.

Please refer to FIG. 3 , the only difference from the first embodiment is that only a part of the auxiliary semiconductor layer 282 and the data line 290 overlap with the first portion 252 , so as to reduce the load effect slightly. The remaining components and manufacturing methods are the same or similar to those of the first embodiment, and will not be repeated here.

third embodiment

FIG. 4 is an active array substrate according to a third embodiment of the present invention.

Please refer to FIG. 4 , the only difference from the first embodiment is that the auxiliary semiconductor layer 282 and the data line 290 are completely offset from and do not overlap with the first portion 252 , so as to reduce the load effect. The remaining components and manufacturing methods are the same or similar to those of the first embodiment, and will not be repeated here.

Fourth embodiment

The present invention further proposes a liquid crystal display panel. As shown in FIG. 5 , the liquid crystal display panel 1 includes any one of the active array substrates 200 of the above embodiments, an opposite substrate 400 and a liquid crystal layer 300 . The liquid crystal layer 300 is located between the active array substrate 200 and the opposite substrate 400 . The opposite substrate 400 can be a color filter substrate or an electrode substrate.

According to the technical solution provided by the present invention, the generation of uneven load effect can be avoided, thereby improving the display quality.

Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, this The protection scope of the invention shall be determined by the scope defined in the claims.

Claims (16)

1. an active array substrate is characterized in that, described active array substrate comprises:

One substrate;

The multi-strip scanning line is arranged on the described substrate;

Many data lines are arranged on the described substrate also vertical with described these sweep traces substantially; And

Many grid patchcords are arranged on the described substrate, and wherein each described grid patchcord is electrically connected with a corresponding gate line respectively, and each described grid patchcord is to be arranged in parallel with described these data lines substantially, and wherein each described grid patchcord has:

A plurality of first one;

A plurality of commentaries on classics line portion and described first corresponding connection;

A plurality of connections hole; And

A plurality of connecting portions, be with described these first one be the different layers configuration, be to connect one of holes and corresponding described first electrical connection one of in wherein said these connecting portions by described these.

2. active array substrate as claimed in claim 1 is characterized in that, described these parts of first one are to overlap with one of described these data lines.

3. active array substrate as claimed in claim 1 is characterized in that, described these connecting portions be with described these data lines be identical layer.

4. active array substrate as claimed in claim 1, it is characterized in that, each described grid patchcord has more an auxiliary insulating layer between one of described these first one and described these data lines, and wherein said grid patchcord has more a semiconductor-assisted layer between described auxiliary insulating layer and described data line.

5. active array substrate as claimed in claim 1 is characterized in that, it is not overlap with described these data lines that described these connect the hole.

6. active array substrate as claimed in claim 1 is characterized in that, described active array substrate more comprises:

A plurality of on-off elements, each described on-off element are to be electrically connected with corresponding described data line and described sweep trace;

A plurality of pixel electrodes, each described pixel electrode are to be electrically connected with corresponding described on-off element; And

Many shared lines are arranged on the described substrate, and are substantially parallel with described these sweep traces, and form a storage capacitors with a drain electrode of corresponding described on-off element.

7. active array substrate as claimed in claim 1 is characterized in that, described these first one is to overlap with the part of described these data lines.

8. active array substrate as claimed in claim 1 is characterized in that, described these first one is not overlap with one of described these data lines.

9. active array substrate as claimed in claim 1 is characterized in that, each described grid patchcord has more a semiconductor-assisted layer between one of described these first one and described these data lines.

10. a display panels is characterized in that, described display panels comprises:

As each described active array substrate in the claim 1 to 9;

One subtend substrate; And

One liquid crystal layer is between described active array substrate and described subtend substrate.

11. a method of making active array substrate is characterized in that, described method comprises:

One substrate is provided;

Form one first conductive layer on described substrate;

Described first conductive layer of patterning with form multi-strip scanning line, a plurality of grid, a plurality of first one and with the commentaries on classics line portion of corresponding described first connection;

Form a gate insulator on described these sweep traces, grid and first one;

Form semi-conductor layer on described gate insulator;

The described semiconductor layer of patterning is to form a plurality of channel layers in described these corresponding grid tops;

The described gate insulator of patterning connects the hole to expose described commentaries on classics line portion to form one;

Form one second conductive layer on described semiconductor layer;

Described second conductive layer of patterning is to form many data lines, a plurality of source electrode and drain electrode and a plurality of connecting portion, and wherein every described connecting portion is to be electrically connected with described corresponding switching part by described connection hole;

Form a protective seam comprehensively;

The described protective seam of patterning exposes described drain electrode to form a contact hole; And

Forming a pixel electrode also is electrically connected with described drain electrode by described contact hole on described protective seam.

12. method as claimed in claim 11 is characterized in that, the step of the described semiconductor layer of patterning comprises that more formation one semiconductor-assisted layer is in described first top.

13. method as claimed in claim 11 is characterized in that, before the step that forms described gate insulator, more comprises forming an auxiliary insulating layer on described these first one.

14. method as claimed in claim 11 is characterized in that, the step of described first conductive layer of patterning more comprises the many shared lines of formation.

15. method as claimed in claim 11 is characterized in that, described these first one is to overlap with described these data lines to small part.

16. method as claimed in claim 11 is characterized in that, described these first one is not overlap with described these data lines.

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