CN104749806A - Array substrate, display panel and display device - Google Patents

Abstract

Embodiments of the present invention provide an array substrate, a display panel, and a display device, which relate to the field of display technology, and can reduce the frame width of the display panel without affecting the packaging effect, which is more in line with the current market demand for narrow frame display products . The array substrate has a display area, a packaging area and a driving circuit area, and the driving circuit area is located between the display area and the packaging area; the array substrate specifically includes: a packaging metal layer arranged in the packaging area, and a packaging metal layer close to the driving circuit area At least one groove structure is arranged on the side; at least one driving unit is arranged in the driving circuit area, and the driving unit includes a capacitor structure; wherein: the capacitor structure is arranged in the groove structure, and one groove structure is used to accommodate one capacitor structure. It is used for the preparation of array substrates, display panels and display devices including the array substrates.

Description

Array substrate, display panel and display device

technical field

The present invention relates to the field of display technology, in particular to an array substrate, a display panel and a display device.

Background technique

Narrow bezel display products mean that the ratio of the display area (Active Area, AA area for short) to the non-display area is relatively large, and users can obtain a better experience when viewing image display. In addition, when a narrow frame display product, such as a display panel, is applied to a splicing screen, since the frame of a single display panel is very narrow, the width of the splicing seam can be reduced, which can significantly improve the overall display effect of the splicing screen. Therefore, the current market demand for narrow bezel display products is becoming more and more urgent.

At present, the design of narrow bezels for display products mainly has the following two constraints:

First, as shown in Figure 1, the current commonly used drive circuits in display technology, such as gate drive circuits, are GOA (Gate Driver on Array, array substrate row drive) circuits. In this technology, the GOA circuit is directly fabricated on the array On the substrate, thereby omitting the large-area gate drive IC (Integrated Circuit, integrated circuit), the COF (Chip On Film, flexible circuit film) used to fix the gate drive IC, and the corresponding leads on the traditional array substrate and other circuit structures. Therefore, compared with traditional display products, the array substrate with the GOA circuit can reduce a part of the non-display area of the boxed display panel.

However, since the GOA circuit is very simplified compared with the traditional gate driver IC, it is very difficult to simplify the GOA circuit. Therefore, it is difficult to further reduce the area of the non-display region occupied by the driving circuit region 03 .

Second, as shown in FIG. 1, for a display panel with a certain size, the required area of the encapsulation area 02 around the display area 01 is also certain; if the area of the encapsulation area 02 is too small, the display panel will be packaged. Serious defects such as poor quality and uneven box thickness will affect the normal display of the display panel. Therefore, it is also difficult to further reduce the area required for the packaging area.

Contents of the invention

In view of this, in order to solve the problems of the prior art, the embodiments of the present invention provide an array substrate, a display panel and a display device, which can reduce the frame width of the display panel without affecting the packaging effect, and are more in line with the current market The demand for display products with narrow borders.

In order to achieve the above object, the embodiments provided by the invention adopt the following technical solutions:

On the one hand, an embodiment of the present invention provides an array substrate, the array substrate has a display area, a packaging area, and a driving circuit area, and the driving circuit area is located between the display area and the packaging area; the array The substrate includes: an encapsulation metal layer disposed in the encapsulation area, at least one groove structure is disposed on a side of the encapsulation metal layer close to the drive circuit area; at least one drive unit disposed in the drive circuit area, The drive unit includes a capacitive structure; wherein: the capacitive structure is disposed in the groove structure, and one groove structure is used to accommodate one capacitive structure.

Preferably, the array substrate further includes an insulating layer; along the direction perpendicular to the plate surface of the array substrate, the capacitor structure includes: a first electrode and a second electrode that are oppositely arranged and insulated; the insulating layer is at least located on the between the first electrode and the second electrode; the encapsulation metal layer is provided on the same layer as the first electrode or the second electrode.

Further preferably, the driving unit further includes: at least one thin film transistor; the first electrode is arranged on the same layer as the gate metal layer of the thin film transistor; the second electrode is connected to the source and drain of the thin film transistor The pole metal layers are arranged on the same layer.

Preferably on the basis of the above, the driving circuit area includes a gate driving circuit area; the driving unit includes a gate driving unit located in the gate driving circuit area.

Preferably, on the basis of the above, the gate driving circuit area is located on one side or both sides of the display area along the direction of the gate lines.

Preferably on the basis of the above, the array substrate further includes: an encapsulation glue on the encapsulation metal layer.

On the other hand, an embodiment of the present invention further provides a display panel, including the above-mentioned array substrate.

In yet another aspect, an embodiment of the present invention further provides a display device, including the above-mentioned display panel.

Based on this, in the above-mentioned array substrate provided by the embodiment of the present invention, at least one groove structure is provided on the side of the packaging metal layer close to the driving circuit area, and one groove structure is used to accommodate a capacitor structure, that is, the groove There is a one-to-one correspondence between the structure and the capacitance structure. Therefore, the above structure is equivalent to interspersing the area occupied by the capacitor structure with a relatively large area into the packaging area, that is, the packaging area and the driving circuit area are close to each other in a concave-convex interspersed manner. Compared with the frame width a of the prior art, when the size of the display area remains unchanged and the facing area of the capacitive structure in the driving circuit does not change, the frame width a' of the array substrate provided by the embodiment of the present invention is obviously The width of the region occupied by the capacitor structure is reduced, so that the frame width a' of the array substrate provided by the embodiment of the present invention is significantly reduced from the frame width a of the prior art.

Moreover, since the groove structure is only arranged on the side of the packaging metal layer close to the driving circuit area, it has little influence on the overall area required for the packaging metal layer to achieve the corresponding packaging effect, so that the packaging effect can not be affected. The frame width of the prior art is significantly reduced.

In this way, for a display panel with the same size, since the above-mentioned array substrate provided by the embodiment of the present invention can have a smaller frame width a', the area of the display area can be made larger, so that the display area and The proportion of the non-display area is larger, and the user can obtain a better experience when viewing the image display; and, when the display panel using the above-mentioned array substrate is applied to the splicing screen, the splicing seam between each sub-screen is smaller, and the display effect is improved. better.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention. Those skilled in the art can also obtain other drawings based on these drawings without creative work.

FIG. 1 is a schematic diagram of a top view structure of each region of an array substrate provided in the prior art;

FIG. 2 is a schematic top view of an array substrate provided by an embodiment of the present invention;

Fig. 3 is AA' cross-sectional enlarged schematic diagram 1 in Fig. 2;

Fig. 4 is AA' cross-sectional enlarged schematic diagram II in Fig. 2;

FIG. 5 is the third enlarged schematic view of the section AA' in FIG. 2 .

Reference signs:

01-display area; 02-package area; 03-drive circuit area; 100-substrate substrate; 11-capacitance structure; 111-first electrode; 112-second electrode; 12-package metal layer; 120-groove structure ; 13-insulating layer; 14-gate metal layer; 15-source and drain metal layer.

Detailed ways

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

It should be noted that, unless otherwise defined, all terms (including technical and scientific terms) used in the embodiments of the present invention have the same meaning as commonly understood by those of ordinary skill in the art to which the present invention belongs. It should also be understood that terms such as those defined in common dictionaries should be interpreted as having meanings consistent with their meanings in the context of the relevant technology, and should not be interpreted in idealized or extremely formalized meanings, unless explicitly stated herein defined in this way.

An embodiment of the present invention provides an array substrate. As shown in FIG. 2, the array substrate has a display area 01, a packaging area 02, and a driving circuit area 03, and the driving circuit area 03 is located between the display area 01 and the packaging area 02; the array The substrate specifically includes: the packaging metal layer 12 arranged in the packaging area 02, at least one groove structure 120 is arranged on the side of the packaging metal layer 12 close to the driving circuit area 03; at least one driving unit arranged in the driving circuit area 03, driving The unit includes a capacitor structure 11 ; wherein: the capacitor structure 11 is disposed in a groove structure 120 , and one groove structure 120 is used to accommodate one capacitor structure 11 .

First, to facilitate understanding of the embodiments of the present invention, some concepts involved in the embodiments of the present invention are described as follows.

1. Packaging metal layer 12

Common LCD (Liquid Crystal Display, liquid crystal display) products or OLED (Organic Light-Emitting Display, organic electroluminescent display) products, the overall structure is composed of an array substrate and a box substrate (color film substrate or packaging substrate). To form a box, it is necessary to apply a packaging glue (usually frit glass glue) on the packaging area to make the two box together. In order to make the sealing glue uniform when heated and cure, and to improve the airtightness of the package, in the packaging area of the array substrate A packaging metal layer consisting of one or more metal layers is formed first, and then a sealant is coated on the packaging metal layer.

In the embodiment of the present invention, the encapsulation metal layer 12 may be a single metal and/or an alloy, and the specific material may follow the existing technology and is not limited.

2. Drive circuit area 03

The driving circuit area 03 mentioned above refers to a circuit for driving the display of the array substrate, and the driving circuit may include but not limited to a gate driving circuit (GOA) and a source driving circuit.

3. Capacitor structure 11

Taking the gate drive circuit as an example, a common gate drive circuit is composed of multiple cascaded gate drive units, and each gate drive unit includes a gate drive capacitor structure for storing electricity. According to the array substrate The structure of the gate drive circuit is also slightly different depending on the specific circuit design, and will not be described here, but its principle is to play the role of a shift register in the array substrate, so all gate drive circuits There must be the above-mentioned capacitor structure.

The embodiment of the present invention does not limit the rest of the circuit structures in the above-mentioned drive unit except the capacitor structure 11 , taking the gate drive unit as an example, and the design of the prior art can be used.

Here, because capacitors can be divided into many types, such as cylindrical capacitors, spherical capacitors, and flat-plate capacitors. Among them, the plate capacitor is composed of two electrode plates separated by a certain distance and separated by a space or a dielectric in the middle. The above-mentioned capacitor structure 11 involved in the specific embodiment of the present invention is a flat-plate capacitor.

In order to realize the above-mentioned function of the shift register in the entire gate drive circuit, the capacitor structure 11 needs to have a certain power storage capacity (characterized by C); and, when the gate drive circuit is applied to drive a display panel with a larger size In order to respond to the requirement of the large-size display panel for the row driving circuit, the capacitance C of the above-mentioned capacitance structure 11 will also increase accordingly.

The capacitance C of a plate capacitor has the following expression:

$\mathrm{<span\; class="notranslate">\; C</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; \&epsiv;</span>}<span\; class="notranslate">\; \&Center\; Dot;</span>\frac{\mathrm{<span\; class="notranslate">\; A</span>}}{\mathrm{<span\; class="notranslate">\; d</span>}}<span\; class="notranslate">\; ;</span>$

Among them, ε is the capacitance ratio of the medium, A is the facing area of the electrode plates, and d is the distance between the electrode plates.

It can be seen from the above expression that the capacitance C is related to the capacitance ratio ε of the medium, the facing area A of the electrode plates, and the distance d between the electrode plates.

For the capacitive structure 11 in the gate drive unit with certain design specification requirements, since the dielectric material used in the display panel is usually silicon nitride, silicon oxide and other materials, the value of the capacitance ratio ε is relatively fixed; and the electrode plate spacing It is difficult to further reduce the distance d. Therefore, for a display panel, it can be considered that the capacitance C of the above-mentioned capacitive structure 11 is proportional to the facing area A of the electrode plates.

Therefore, in order to meet the requirements of circuit design for the capacitance C of the capacitor structure 11 , the electrode plate in the capacitor structure 11 needs to have a relatively large facing area A, resulting in a larger area occupied by the capacitor structure 11 .

Based on this, in the above-mentioned array substrate provided by the embodiment of the present invention, at least one groove structure 120 is provided on the side of the packaging metal layer 12 close to the driving circuit area 03, and one groove structure 120 is used to accommodate a capacitor structure 11, that is, the positional relationship between the groove structure 120 and the capacitor structure 11 is a one-to-one correspondence. Therefore, the above structure is equivalent to inserting the area occupied by the capacitor structure 11 with a relatively large area into the packaging area 02, that is, along the lateral direction in FIG. approach each other. Referring to FIG. 3 together, compared with the frame width a of the prior art shown in FIG. 1 , when the size of the display area 01 remains unchanged and the area directly facing the capacitive structure in the driving circuit does not change, this The frame width a' of the above-mentioned array substrate provided by the embodiment of the present invention obviously reduces the width of the area occupied by the capacitive structure 11, so that the frame width a' of the above-mentioned array substrate provided by the embodiment of the present invention is significantly reduced in the prior art The border width a.

Moreover, since the groove structure 120 is only arranged on the side of the packaging metal layer 12 close to the driving circuit area 03, it has little influence on the overall area required for the packaging metal layer 12 to achieve the corresponding packaging effect, so that it can be used without affecting Under the premise of encapsulation effect, the frame width of the prior art is obviously reduced.

In this way, for a display panel with the same size, since the array substrate provided by the embodiment of the present invention can have a smaller frame width a', the area of the display area 01 can be made larger, so that the display area The ratio of 01 to the non-display area is larger, and the user can obtain a better experience when viewing the image display; and, when the display panel using the above-mentioned array substrate is applied to the splicing screen, the splicing seam between each sub-screen is smaller, The display effect is better.

Further, as shown in FIG. 4 and FIG. 5, the array substrate specifically includes an insulating layer 13; along the direction perpendicular to the surface of the array substrate (that is, the cross-sectional view shown in FIG. 4 and FIG. 5), the capacitor structure 11 includes a relatively The first electrode 111 and the second electrode 112 are arranged and insulated; the insulating layer 13 is located at least between the first electrode 111 and the second electrode 112 ;

It should be noted that the function of the first and insulating layer 13 is to separate the first electrode 111 and the second electrode 112 from each other to form the above-mentioned capacitor structure 11 . Therefore, the insulating layer 13 should be located at least between the above two electrodes. Certainly, in consideration of simplifying the overall manufacturing process of the array substrate, the insulating layer 13 may also be disposed in the encapsulation area 02 as shown in FIG. 4 or FIG. 5 , which is not specifically limited.

Second, the so-called "same-layer arrangement" refers to at least two kinds of graphics, and refers to a structure in which at least two kinds of graphics are arranged on the same layer of film. Specifically, the at least two patterns mentioned above can be formed on a film made of the same material through the same patterning process.

For example, as shown in FIG. 4, the packaging metal layer 12 and the first electrode 111 in the capacitor structure 11 are arranged on the base substrate 100 together; or, referring to FIG. 5, the packaging metal layer 12 and the capacitor structure 11 The second electrode 112 is also disposed on the insulating layer 13 . In this way, an electrode plate in the capacitor structure 11 can be prepared together when the packaging metal layer 12 is prepared, thereby improving the utilization rate of the patterning process of the array substrate and simplifying the preparation process.

Further, as shown in FIG. 4 , the drive unit also includes at least one thin film transistor (Thin Film Transistor, thin film transistor); the first electrode 111 is arranged in the same layer as the gate metal layer 14 of the thin film transistor; the second electrode 112 and the thin film transistor The source and drain metal layers 15 are set in the same layer.

It should be noted that the gate metal layer 14 refers to the pattern layer including the gate of the TFT; the source and drain metal layer 15 refers to the pattern layer including the source and drain of the TFT.

The number of TFTs in the driving unit is not limited, and the number of TFTs can be adjusted according to the specific circuit design of the driving circuit. When the number of TFTs in the drive unit is multiple, the above-mentioned gate metal layer 14 refers to the pattern layer including the gates of all TFTs, and the source and drain metal layer 15 refers to the source and drain electrodes including all TFTs. Drain pattern layer.

In this way, when the encapsulation metal layer 12 and the first electrode 111 are arranged on the same layer, since the first electrode 111 is also arranged on the same layer as the gate metal layer 14, the above-mentioned encapsulation metal layer 12 can be prepared under the same patterning process. , the first electrode 111 and the gate metal layer 14, or prepare the above-mentioned packaging metal layer 12, the second electrode 112 and the source and drain metal layers 15 under the same patterning process, thereby further simplifying the process and reducing costs .

Although not shown in the embodiment of the present invention, those skilled in the art should also understand that the display area 01 includes a plurality of pixel units arranged in a matrix, each pixel unit includes a TFT, and the first electrode 111 is connected with the driving While the gate metal layer 14 in the TFT of the unit is set on the same layer, it can also be set on the same layer as the gate metal layer of the TFT in the display area 01; of course, the second electrode 112 is in the same layer as the source and While the drain metal layer 15 is arranged on the same layer, it can also be arranged on the same layer as the source and drain metal layers of the TFT in the display area 01, so as to further improve the utilization rate of the patterning process and simplify the manufacturing process.

In this case, the insulating layer 13 may also extend to the display region 01 , and specifically may be a gate insulating layer covering the gate metal layers of the TFTs in each region.

Here, in FIG. 4, the first electrode 111 is located below and the second electrode 112 is located above the base substrate 100 as an example. The relative positions of the first electrode 111 and the second electrode 112 can be equivalent to Change, without limitation.

On the basis of the above, considering that the current driving circuit for direct plate-making on the array substrate is mainly a gate driving circuit, which can replace the traditional gate driving IC to directly scan and drive the gate lines, therefore, the embodiment of the present invention is further preferred , the above driving circuit area 03 includes a gate driving circuit area, and the driving unit includes a gate driving unit located in the gate driving circuit area.

Further, as shown in FIG. 2, when the driving circuit region 03 includes a gate driving circuit region, the gate driving circuit region is preferably arranged on one or both sides of the display region 01 along the direction of the gate lines, so that there is no need to set Additional circuit structures such as lead wires for connecting the gate driving circuit and the gate lines avoid increasing the area of the non-display area outside the display area 01 .

Further, the array substrate further includes: encapsulation glue on the encapsulation metal layer 12 .

Here, since the capacitive structure 11 is interspersed at the groove structure 120 of the package metal layer 12, when the glass glue is irradiated with laser to melt it, in order to avoid the influence of the laser irradiation on the device performance of the capacitive structure 11, the laser beam can be adjusted to The irradiation path is such that the laser only irradiates the part of the packaging metal layer 12, so as to avoid possible influence on the capacitive structure 11 due to the laser irradiation.

On the basis of the above, an embodiment of the present invention further provides a display panel, including the above-mentioned array substrate.

Further, an embodiment of the present invention also provides a display device, including the above-mentioned display panel.

Here, the above-mentioned display device may specifically be a liquid crystal display device, such as liquid crystal TV, OLED TV or electronic paper, digital photo frame, mobile phone, tablet computer, monitor, notebook computer, navigator and other products or components with any display function.

It should be noted that all the drawings of the present invention are simple schematic diagrams of the array substrate, which are only for clearly describing the structure related to the invention, and other structures that are not related to the invention are existing structures. Not reflected or only partially reflected.

The above is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Anyone skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present invention. Should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be determined by the protection scope of the claims.

Claims (8)

1. an array base palte, is characterized in that, described array base palte has viewing area, packaging area and drive circuit area, and described drive circuit area is between described viewing area and described packaging area;

Described array base palte comprises: the package metals layer being arranged on described packaging area, and described package metals layer is provided with at least one groove structure on the side of described drive circuit area;

Be arranged at least one driver element of described drive circuit area, described driver element comprises capacitance structure; Wherein:

Described capacitance structure is arranged in described groove structure, and a described groove structure is for holding a described capacitance structure.

2. array base palte according to claim 1, is characterized in that, described array base palte also comprises insulation course;

Along the direction, plate face perpendicular to described array base palte, described capacitance structure comprises: be oppositely arranged and the first electrode insulated and the second electrode; Described insulation course is at least between described first electrode and described second electrode;

Described package metals layer and described first electrode or described second electrode are arranged with layer.

3. array base palte according to claim 2, is characterized in that, described driver element also comprises: at least one thin film transistor (TFT);

The gate metal layer of described first electrode and described thin film transistor (TFT) is arranged with layer; Source electrode and the drain metal layer of described second electrode and described thin film transistor (TFT) are arranged with layer.

4. the array base palte according to any one of claims 1 to 3, is characterized in that,

Described drive circuit area comprises gate driving circuit region; Described driver element comprises the drive element of the grid being positioned at described gate driving circuit region.

5. the array base palte according to any one of claim 4, is characterized in that, described gate driving circuit region is positioned at the one or both sides of described viewing area along grid line direction.

6. the array base palte according to any one of claims 1 to 3, is characterized in that, described array base palte also comprises: be positioned at the packaging plastic on described package metals layer.

7. a display panel, is characterized in that, comprises the array base palte as described in any one of claim 1 to 6.

8. a display device, is characterized in that, comprises display panel as claimed in claim 7.